CN101303894A - Shift register and shift register apparatus - Google Patents
Shift register and shift register apparatus Download PDFInfo
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- CN101303894A CN101303894A CNA2007101068232A CN200710106823A CN101303894A CN 101303894 A CN101303894 A CN 101303894A CN A2007101068232 A CNA2007101068232 A CN A2007101068232A CN 200710106823 A CN200710106823 A CN 200710106823A CN 101303894 A CN101303894 A CN 101303894A
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Abstract
The invention relates to a shift register used for a data driver. The shift register of the invention consists of a shift register unit which selectively receives a clock pulse; wherein, the shift register unit consists of a trigger and a first selecting circuit; the first selecting circuit selectively transmits the clock pulse to the trigger according to a first selecting signal; wherein, before the trigger receives an enabled data signal, the first selecting circuit transmits the clock pulse to the trigger according to the first selecting signal so that the trigger can correctly output enabled data signals according to the clock pulse.
Description
Technical field
The invention relates to a kind of shift register that is used for data driver, and particularly relevant for a kind of shift register with power saving effect.
Background technology
Fig. 1 illustrates the Organization Chart of the part of traditional shift register.The shift register of Fig. 1 comprises several triggers.Please refer to Fig. 1, when trigger 110 receives a primary data signal DT who enables, according to the input clock pulse CK output one data-signal Q1 that enables.After trigger 120 received the data-signal Q1 that enables, the one data-signal Q2 that enables was to next stage trigger 130 in output.So analogize, each shift register is exported a data-signal that enables successively to circuit afterwards, as line latch (line latch), so that correct pixel data breech lock is lived.
For the trigger of shift register inside, the trigger of the data-signal of output enable only, and the trigger that receives this data-signal that enables needs operation.Yet no matter whether trigger receives or the data-signal of output enable, and trigger is all wanted the receive clock pulse and in running order, therefore consumes many unnecessary power supplys.
Summary of the invention
The present invention relates to a kind of shift register.In this shift register, for each shifting deposit unit, respectively to select circuit to control whether export the trigger of time clock independently to each shifting deposit unit.For the shifting deposit unit that be about to receive the data-signal that enables, it selects circuit is that time clock is sent to trigger in the shifting deposit unit, makes the trigger of shifting deposit unit be received the data-signal that enables.And when the trigger of shifting deposit unit all behind the data-signal of output enable, or the data-signal that enables apart from reception when the trigger of shifting deposit unit is still early the time, select circuit promptly to stop the transmission clock pulse trigger of shifting deposit unit so far, make the trigger of this shifting deposit unit not activate, reach the effect of power saving.
According to a first aspect of the invention, propose a kind of shift register, be used for a data driver.Shift register of the present invention comprises a shifting deposit unit.Shifting deposit unit optionally receives a time clock.Shifting deposit unit comprises a trigger and one first selection circuit.First selects circuit to select signal according to one first, and optionally the transmission clock pulse is to trigger.Wherein, before trigger received the data-signal enable, first selected circuit to select the pulse of signal transmission clock to trigger according to first, made trigger be able to correctly the data-signal according to the time clock output enable.
According to a second aspect of the invention, propose a kind of shift LD device, be used for a data driver.Shift LD device comprises a shift register.Shift register optionally receives a time clock.Shift register comprises that one first selects a circuit and a shifting deposit unit.First selects circuit to select signal, optionally transmission clock pulse according to one first.Shifting deposit unit comprises a trigger and one second selection circuit.The second selection circuit is selected signal according to one second, optionally transmits the time clock next by the first selection circuit transmission to trigger.Wherein, before trigger received the data-signal that enables, first selected circuit to select the pulse to the second of signal transmission clock to select circuit according to first.Before trigger received the data-signal enable, second selected circuit to select the pulse of signal transmission clock to trigger according to second, made trigger be able to correctly the data-signal according to the time clock output enable.
Further, this shift LD device can also comprise P shift register, optionally receives a time clock, and each this P shift LD device also comprises M shifting deposit unit, and whenever this M shifting deposit unit also comprises a plurality of triggers; Wherein, before the 1st trigger of the 1st shifting deposit unit of a k shift register of this P shift register received the data-signal that enables, this of this k shift register first selected circuit to transmit this time clock this second selection circuit to this shifting deposit unit whenever of this k shift register according to this first selection signal of this k shift register; Wherein, before the 1st trigger of an i shifting deposit unit of this M of this k shift register shifting deposit unit receives the data-signal that enables, this of this i shifting deposit unit second selects circuit second to select signal to transmit this time clock these all triggers to this i shifting deposit unit according to this of this i shifting deposit unit, makes these triggers of this i shifting deposit unit be able to the data-signal of correctly exporting according to this time clock that enables; Wherein, P is a positive integer, and k is the positive integer that is less than or equal to P; Wherein, M is a positive integer, and i is the positive integer that is less than or equal to M.
Further, behind the data-signal of last trigger output enable of M shifting deposit unit of this k shift register, this first selection circuit of this k shift register stops to transmit this time clock this second selection circuit to each this shifting deposit unit of this k shift register according to this first selection signal of this k shift register, so that these triggers of this M shifting deposit unit of this k shift register do not activate.
In above-mentioned shift LD device, in this k shift register, behind the data-signal of last trigger output enable of this i shifting deposit unit, this second selection circuit of this i shifting deposit unit stops to transmit this time clock these triggers to this i shifting deposit unit according to this second selection signal of this i shifting deposit unit, so that these triggers of this i shifting deposit unit do not activate.
In addition, each shifting deposit unit of each this shift register can comprise N trigger, in this k shift register, when the data-signal that enables that j trigger of this i shifting deposit unit receives, this second selection circuit of i+1 shifting deposit unit in these shifting deposit units is according to this second selection signal of this i+1 shifting deposit unit, this time clock is sent at least one this trigger of this i+1 shifting deposit unit, makes at least one this trigger of this i+1 shifting deposit unit be able to correctly data-signal according to this time clock output enable; Wherein, i is the positive integer less than M; Wherein, N is a positive integer, and j is the positive integer that is less than or equal to N.
In above-mentioned shift LD device, in this k shift register, before the data-signal that enables that j trigger of this i shifting deposit unit receives, this second selection circuit of this i+1 shifting deposit unit is according to this second selection signal of this i+1 shifting deposit unit, do not transmit this time clock these triggers, so that these triggers of this i+1 shifting deposit unit do not activate to this i+1 shifting deposit unit.
In an embodiment, this shifting deposit unit of each of each this shift register comprises N trigger, in this k shift register, when the data-signal that enables that j trigger of i+1 shifting deposit unit in these shifting deposit units receives, this second selection circuit of i shifting deposit unit in these shifting deposit units is according to this second selection signal of this i shifting deposit unit, stop to transmit this time clock these triggers, make these triggers of this i shifting deposit unit not activate to this i shifting deposit unit; Wherein, i is the positive integer less than M; Wherein, N is a positive integer, and j is the positive integer that is less than or equal to N.Wherein, these shift registers can be bidirectional shift register.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 illustrates the part Organization Chart of traditional shift register.
Fig. 2 illustrates the shift LD device of the embodiment of the invention.
Fig. 3 illustrates the part Organization Chart of the shift register of Fig. 2.
Fig. 4 illustrates the part-structure figure of the bidirectional shift register 400 of another embodiment of the present invention.
The primary clustering symbol description
110,120,130,311,312,31N, 321,322,32N, 411,412,41N, 421,422,42N: trigger
210,220,230: offset buffer
350,450: the first selection circuit
330,340,430,440: the second selected cells
Embodiment
Shift LD device of the present invention is used for a data driver.Shift LD device comprises a shift register.Shift register optionally receives a time clock.Shift register comprises that one first selects a circuit and a shifting deposit unit.First selects circuit to select signal, optionally transmission clock pulse according to one first.Shifting deposit unit comprises a trigger and one second selection circuit.The second selection circuit is selected signal according to one second, optionally transmits the time clock next by the first selection circuit transmission to trigger.Wherein, before trigger received the data-signal that enables, first selected circuit to select the pulse to the second of signal transmission clock to select circuit according to first.Before trigger received the data-signal enable, second selected circuit to select the pulse of signal transmission clock to trigger according to second, made trigger be able to correctly the data-signal according to the time clock output enable.
Fig. 2 illustrates the shift LD device 200 of the embodiment of the invention.Shift LD device 200 comprises shift register 210,220 and 230.Shift register 210 to 230 equal receive clock pulse CK.Shift register 210 receives the data-signal DT that enables, and according to time clock CK, the data-signal D1 of output enable.Shift register 220 receives the data-signal D1 that enables, and according to time clock CK, the data-signal D2 of output enable.Shift register 230 receives the data-signal D2 that enables, and according to time clock CK, the data-signal D3 of output enable.
Please refer to Fig. 3, it illustrates the part Organization Chart of the shift register 210 of Fig. 2.Shift register 210 comprises at least one shifting deposit unit and one first selection circuit 350.Each shifting deposit unit comprises N trigger and one second selection circuit.Wherein, N is a positive integer.Shift register 210 in the embodiment of the invention comprises shifting deposit unit 310 and 320.
First selects circuit 350 to select signal CS1 according to one, optionally exports time clock CK to the second and selects circuit 330 and 340.Select circuit 350 output time clock CK to the second to select circuit 330 with 340 the time when first, second selects circuit 330 and 340 foundation selection signal BS1 and BS2 respectively, optionally transmission clock pulse CK to trigger 311 to 31N, and 321 to 32N.Wherein, in the present embodiment, first select circuit 350, second select circuit 330 and 340 be with door (AND) be example.
The operation of the first selection circuit 350 of explanation shift register now.Before first trigger 311 of the 1st shifting deposit unit 310 of shift register 210 was about to receive the data-signal DT that will enable, selecting signal CS1 was the accurate position 1 of logic.Like this, first selects circuit 350 promptly to be exported time clock CK to the second selects circuit 330 and 340, so that all triggers in the shift register 210 are able to the data-signal of output enable correctly.
And behind the data-signal D1 of last trigger output enable of last shifting deposit unit of shift register 210, all triggers in the shift register 210 need not operated.At this moment, select signal CS1 to transfer the accurate position 0 of logic to.Like this, first selects circuit 350 to stop to export time clock CK to the second selects circuit 330 and 340, so that all triggers in the shift register 210 all do not activate, to save power supply.
Similarly, before first trigger (not shown) of the 1st shifting deposit unit of shift register 220 received the data-signal D1 that enables, first selected signal CS2 (not shown) to transfer the accurate position 1 of logic to.Like this, first of shift register 220 selects the circuit (not shown) promptly to be exported the second selection circuit (not shown) of time clock CK to shift register 220, so that all triggers of shift register 220 are able to the data-signal of output enable correctly.
The operation of shifting deposit unit 310 and 320 is described now.Before the 1st trigger 311 of shifting deposit unit 310 received the data-signal DT that enables, first of shift register 210 selected circuit 350 time clock CK to be sent to the second selection circuit of all shifting deposit units of shift register 210.
Select circuit 350 output time clock CK to the second selection circuit of each shifting deposit unit first, and before the trigger 311 of shifting deposit unit 310 receives the data-signal DT that enables, second of shifting deposit unit 310 is selected circuit 330, according to select signal BS1 transmission clock pulse CK to trigger 311 to 31N.Thus, trigger 311 is correctly received the data-signal DT that enables, and according to time clock CK, the data-signal Q11 of output enable is to next stage trigger 312.The operation of all the other triggers of shifting deposit unit 310 all by that analogy.
Therefore, when trigger 311 to 31N receives the data-signal that enables in regular turn, be able to correctly data-signal according to time clock CK output enable.In the present embodiment, selecting signal BS1 this moment is the accurate position 1 of logic, makes second to select circuit 310 output time clock CK.
Behind the data-signal Q1N of last trigger 31N output enable of shifting deposit unit 310, trigger 311 to 31N is the data-signal of output enable all, and therefore, trigger 311 to 31N need not operated.Therefore, second of shifting deposit unit 310 is selected circuit 330, according to select signal BS1 stop transmission clock pulse CK to trigger 311 to 31N, trigger 311 to 31N is not activated, thereby saves power supply.In embodiments of the present invention, selecting signal BS1 this moment is that the accurate position 0, the second of logic selects circuit 310 to stop to export time clock CK.
Wherein, in the present embodiment, data-signal Q1N is the data-signal D1 of Fig. 2.
For shifting deposit unit 320, before trigger 321 received the data-signal Q1 that enable next by trigger 31N transmission, second selected circuit 340 promptly according to selection signal BS2 time clock CK to be sent to all triggers 321 of shifting deposit unit 320 to 32N.Selecting signal BS2 this moment is the accurate position 1 of logic, makes second to select circuit 340 output time clock CK.
Therefore, when first trigger 321 of shifting deposit unit 320 is received the data-signal Q1N that enables, be able to correctly the data-signal Q21 that enables is sent to next stage trigger 322.And similarly, other trigger of shift register 320 also transmits the data-signal that enables toward the next stage trigger.
The shift register of the embodiment of the invention can be controlled in the following manner and whether export the trigger of time clock to each shifting deposit unit.Now be illustrated with shifting deposit unit 310 and 320.
At j trigger of shifting deposit unit 310, for example be N-1 trigger, receive before the data-signal that enables, selecting signal BS2 is the accurate position 0 of logic.Second of shifting deposit unit 320 selects circuit 340 according to selecting signal BS2 not export time clock CK to shifting deposit unit 320, makes the trigger 321 to 32N of shifting deposit unit 320 not activate, to save power supply.
And when j trigger of shifting deposit unit 310 receives the data-signal that enables, select signal BS2 to transfer the accurate position 1 of logic to.Second of shifting deposit unit 320 is selected circuit 340, just according to selecting signal BS2, time clock CK is sent to the trigger 321 of shifting deposit unit 320 to 32N.Like this, trigger 321 is able to behind the data-signal Q1N that reception enables, correctly according to the data-signal Q21 of time clock CK output enable to next stage trigger 322.All the other trigger operation of shifting deposit unit 320 do not repeat them here by that analogy.
Y trigger when shifting deposit unit 320, the 2nd trigger 322 for example, during data-signal that reception enables, all triggers of shifting deposit unit 310 had all been exported the data-signal that enables, so all triggers of shifting deposit unit 310 promptly need not operated.Therefore, select signal BS 1 to transfer the accurate position 0 of logic to.Second of shifting deposit unit 310 is selected circuit 330, according to select signal BS1 stop transmission clock pulse CK to the trigger 310 of shifting deposit unit 310 to 31N, so that trigger 310 to 31N do not activate, to save power supply.
More than be the structure and the operation of explanation shift register 210.The structure of shift register 220,230 is identical with shift register 210 with operation, does not repeat them here.
In embodiments of the present invention, selection signal CS1, BS1, the BS2 of shift register 210 cooperate time clock CK to be activated or do not activate.Shift LD device 200 comprises 3 shift registers, and each shift register for example comprises M shifting deposit unit, and each shifting deposit unit comprises N trigger.The time of the data-signal of each trigger reception or output enable is the one-period of time clock CK.Selection signal CS1 activates before first trigger of first shifting deposit unit of shift register 210 receives the data-signal that enables, and behind the data-signal D1 of last trigger output enable of its last shifting deposit unit, transfer to and not activating.Therefore select signal CS1 to enable M * N cycle every 3 * M * N cycle.And select signal BS1 before first trigger 311 of shifting deposit unit 310 receives the data-signal that enables, to be activated (enabling), and behind the data-signal of its last trigger 31N output enable, transfer to and not activating.Therefore select signal BS1 to enable N cycle every 3 * M * N cycle.Whether selection signal in other shift register and the shifting deposit unit enables to cooperate time clock CK equally, does not repeat them here.
Selection signal CS1, BS1, the BS2 of shift register 210 can be sent by a signal detector.Whether whether this signal detector data detection signal DT, Q11 to Q1N, Q21 to Q2N enable, decide and select signal CS1, BS1, BS2 to enable.The selection signal of other shift register also can be sent by above-mentioned signal detector, and whether decision enables.
The shift LD device of the embodiment of the invention is to be example to have 3 shift registers, in practical application, is not limited to 3 shift registers.Any shift LD device, so long as have at least one shift register, each shift register is to use the selection circuit, data-signal according to reception or output enable, determine whether exporting time clock to inner shifting deposit unit, reach power saving effect, all within the scope of the invention.
The effect of the shift LD device of the embodiment of the invention is described now.The shift LD device of the embodiment of the invention comprises several shift registers.Each shift register is selected circuit independently to control with one first respectively and whether is exported time clock to inner shifting deposit unit.For each shift register, when wherein trigger is about to receive or during the data-signal of output enable, it first selects circuit output time clock to second of its shifting deposit unit to select circuit.When wherein trigger all not the data-signal of output enable or distance receive the data-signal that enables still early the time, it first selects circuit promptly not export time clock to second of its shifting deposit unit to select circuit.
And traditional shift LD device, no matter shift register wherein has or not and receives the data-signal that enables, and all is provided with time clock.Therefore, even do not receive or during the data-signal of output enable, these triggers still can be operated, and expend unnecessary power supply at all triggers of shift register.Under comparing, the shift LD device of the embodiment of the invention has more power saving effect.
In addition, in shift register,, select circuit to control whether export the trigger of time clock independently with second respectively to each shifting deposit unit for each shifting deposit unit.For the shifting deposit unit that is about to receive the data-signal that enables, its second selection circuit just is sent to time clock the trigger in the shifting deposit unit, makes the trigger of shifting deposit unit be received the data-signal that enables.And when the equal data-signal of output enable of the trigger of shifting deposit unit, or the data-signal that enables apart from reception when the trigger of shifting deposit unit is still early the time, second selects the i.e. transmission clock pulse trigger of shifting deposit unit so far not of circuit, make the trigger of this shifting deposit unit not activate, also further reach the effect of power saving.
Shift LD device of the present invention also can be designed to one two-way (bi-directional) shift LD device, has at least one bidirectional shift register.Each bidirectional shift register comprises at least one shifting deposit unit.Fig. 4 illustrates the structural drawing of part of the bidirectional shift register 400 of another embodiment of the present invention.Fig. 4 only illustrates the shifting deposit unit 410 and 420 of bidirectional shift register 400.Shift register 400 has one first and selects circuit 450.Shifting deposit unit 410 comprises that second selects circuit 430 and several shifting deposit units 411 to 41N.Shifting deposit unit 420 comprises that second selects circuit 440 and several shifting deposit units 421 to 42N.
Wherein, all triggers all receive a control signal SHL.Control signal SHL is in order to select the direction of transfer of data-signal.Each trigger receives the data-signal of the trigger output on its left side according to control signal SHL, or the data-signal of the trigger on its right output.
In addition, the first selection circuit 450 of shift register 400 and the operation of the second selection circuit 430,440 do not repeat them here as hereinbefore.
In sum, though the present invention is illustrated with a preferred embodiment, it is not to be used for limiting the present invention.The ordinary technical staff in the technical field of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention should be as the criterion with the qualification of claims.
Claims (10)
1. a shift register is used for a data driver, comprising:
Shifting deposit unit, optionally receive clock pulse, described shifting deposit unit comprises:
Trigger; And
First selects circuit, according to the first selection signal, optionally transmits described time clock to described trigger;
Wherein, before described trigger receives the data-signal that enables, described first selects circuit to select signal to transmit described time clock to described trigger according to described first, makes described trigger be able to the data-signal of the described time clock output enable of foundation correctly.
2. shift register according to claim 1, wherein, behind the data-signal of described trigger output enable, described first selects circuit to select signal to stop to transmit described time clock to described trigger, so that described trigger does not activate according to described first.
3. shift register according to claim 1, wherein, described shift register comprises M shifting deposit unit, and each described M shifting deposit unit optionally receives described time clock, and each described M shifting deposit unit also comprises a plurality of triggers and the described first selection circuit;
Wherein, before the 1st trigger of i shifting deposit unit of a described M shifting deposit unit receives the data-signal that enables, described first of described i shifting deposit unit selects circuit to select signal to transmit described time clock these triggers to described i shifting deposit unit according to described first of described i shifting deposit unit, makes these triggers of described i shifting deposit unit be able to the data-signal of the described time clock output enable of foundation correctly;
Wherein, M is a positive integer, and i is the positive integer that is less than or equal to M.
4. shift register according to claim 2, wherein, behind the data-signal of last trigger output enable of described i shifting deposit unit, described first of described i shifting deposit unit selects circuit to select signal to stop to transmit the described at least one trigger of described time clock to described i shifting deposit unit according to first of described i shifting deposit unit, so that described at least one trigger of described i shifting deposit unit does not activate.
5. shift register according to claim 2, wherein, each described shifting deposit unit comprises N trigger, when j trigger of described i shifting deposit unit receives the data-signal that enables, described first of i+1 shifting deposit unit in these shifting deposit units selects circuit to select signal according to described first of described i+1 shifting deposit unit, described time clock is sent to described N trigger of described i+1 shifting deposit unit, makes described N trigger of described i+1 shifting deposit unit be able to correctly data-signal according to described time clock output enable;
Wherein, i is the positive integer less than M;
Wherein, N is a positive integer, and j is the positive integer that is less than or equal to N.
6. shift register according to claim 5, wherein, before j trigger of described i shifting deposit unit receives the data-signal that enables, described first of described i+1 shifting deposit unit selects circuit to select signal according to described first of described i+1 shifting deposit unit, do not transmit described N the trigger of described time clock, so that described N trigger of described i+1 shifting deposit unit do not activate to described i+1 shifting deposit unit.
7. shift register according to claim 3, wherein, each described shifting deposit unit comprises N trigger, when j trigger of described i+1 shifting deposit unit receives the data-signal that enables, described first of described i shifting deposit unit selects circuit to select signal to stop to transmit described N the trigger of described time clock to described i shifting deposit unit according to described first of described i shifting deposit unit, so that described N trigger of described i shifting deposit unit do not activate;
Wherein, i is the positive integer less than M;
Wherein, N is a positive integer, and j is the positive integer that is less than or equal to N.
8. shift register according to claim 3, wherein, described shift register comprises that also one second selects circuit, in order to according to one second selection signal, optionally exports described time clock these first selection circuit to described shifting deposit unit.
9. shift register according to claim 1, wherein, described shift register is a bidirectional shift register.
10. a shift LD device is used for a data driver, comprises shift register, optionally receives a time clock, and described shift register comprises:
First selects circuit, according to one first selection signal, optionally transmits described time clock;
Shifting deposit unit comprises:
Trigger; And
The second selection circuit according to one second selection signal, optionally transmits the described time clock next by the described first selection circuit transmission to described trigger;
Wherein, before described trigger received the data-signal that enables, described first selects circuit to select signal to transmit described time clock extremely described second according to described first selected circuit;
Wherein, before described trigger receives the data-signal that enables, described second selects circuit to select signal to transmit described time clock to described trigger according to described second, makes described trigger be able to the data-signal of the described time clock output enable of foundation correctly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101068232A CN101303894A (en) | 2007-05-10 | 2007-05-10 | Shift register and shift register apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101068232A CN101303894A (en) | 2007-05-10 | 2007-05-10 | Shift register and shift register apparatus |
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| CNA2007101068232A Pending CN101303894A (en) | 2007-05-10 | 2007-05-10 | Shift register and shift register apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102118780A (en) * | 2009-12-30 | 2011-07-06 | 中兴通讯股份有限公司 | Method and base station for using multiple clock sources |
| CN104217764A (en) * | 2014-08-29 | 2014-12-17 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, gate driving circuit and display device |
| CN106529067A (en) * | 2016-11-23 | 2017-03-22 | 中国电子科技集团公司第五十四研究所 | Double-clock flip-flop, and low-power clock dynamic management circuit and management method |
-
2007
- 2007-05-10 CN CNA2007101068232A patent/CN101303894A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102118780A (en) * | 2009-12-30 | 2011-07-06 | 中兴通讯股份有限公司 | Method and base station for using multiple clock sources |
| CN104217764A (en) * | 2014-08-29 | 2014-12-17 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, gate driving circuit and display device |
| CN106529067A (en) * | 2016-11-23 | 2017-03-22 | 中国电子科技集团公司第五十四研究所 | Double-clock flip-flop, and low-power clock dynamic management circuit and management method |
| CN106529067B (en) * | 2016-11-23 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of low power consuming clock dynamic management circuit and management method |
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Open date: 20081112 |