CN104217764A

CN104217764A - Shifting register, driving method thereof, gate driving circuit and display device

Info

Publication number: CN104217764A
Application number: CN201410438576.6A
Authority: CN
Inventors: 郭蕾; 朱红; 于洪俊; 王智勇
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2014-08-29
Filing date: 2014-08-29
Publication date: 2014-12-17

Abstract

The invention discloses a shifting register, a driving method thereof, a gate driving circuit and a display device. The shifting register comprises a first edge trigger, a second edge trigger and a data selector. The embodiment of the invention utilizes the edge triggers and the data selector to realize the shifting register. Since the edge triggers and the data selector are generally formed by NAND gate and circuit repeatability is high, the circuit repeatability in the shifting register can be improved so as to lower the design complexity of a GOA (Gate Driver on Array) layout. In addition, since the edge triggers have a function of keeping an output signal, a reset signal does not need to be input into the gate driving circuit formed by a plurality of shifting registers so as to omit a connecting wire used for transmitting the reset signal between two levels of shifting registers to further lower the design complexity of the GOA layout.

Description

Shift register, driving method thereof, gate driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register, a driving method thereof, a grid driving circuit and a display device.

Background

In the modern times of the growing technology, liquid crystal displays have been widely used in electronic display products, such as televisions, computers, mobile phones, and personal digital assistants. The lcd includes a data Driver (Source Driver), a Gate Driver (Gate Driver), and an lcd panel. The liquid crystal display panel is provided with a pixel array, and the grid driving device is used for sequentially opening corresponding pixel rows in the pixel array so as to transmit pixel data output by the data driver to the pixels and further display an image to be displayed.

At present, a Gate driving device is generally formed on an Array substrate of a liquid crystal display by an Array process, that is, a Gate Driver on Array (GOA) process of the Array substrate, and this integration process not only saves cost, but also can achieve a symmetric aesthetic design on both sides of a liquid crystal Panel (Panel), and simultaneously, a Bonding area of a Gate Integrated Circuit (IC) and a wiring space of a Fan-out (Fan-out) are also saved, thereby realizing a design of a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.

The conventional gate driving apparatus is generally composed of a plurality of cascaded shift registers, and each shift register includes a plurality of thin film transistors. However, in the conventional gate driving device, each thin film transistor in each stage of the shift register has an independent function, needs to be designed separately, and has low repeatability, so the design difficulty of the GOA layout (layout) is relatively high. In addition, in the conventional gate driving device, since the output signal of the shift register of the current stage is usually used as the input signal of the shift register of the next stage and the reset signal of the shift register of the previous stage at the same time, the design of layout and wiring of the GOA layout is also difficult.

Therefore, how to reduce the complexity of the design of the GOA layout is a technical problem that needs to be solved urgently by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present invention provide a shift register, a driving method thereof, a gate driving circuit and a display device, so as to improve circuit repeatability inside the shift register and reduce the number of connecting lines between each stage of shift register, thereby solving the problem of high complexity of the GOA layout design in the prior art.

Therefore, an embodiment of the present invention provides a shift register, including: a first edge flip-flop, a second edge flip-flop, and a data selector, wherein;

the first edge trigger is used for outputting a first signal to the data selector under the control of a first clock signal and an input signal or under the control of a second clock signal and the input signal; wherein a width of the active pulse of the first signal is 2 times a width of the active pulse of the input signal, the active pulse of the first signal is in the same phase as the active pulse of the input signal, and the active pulse of the first signal is delayed from the active pulse of the input signal by 1/2 cycles of the first clock signal or 1/2 cycles of the second clock signal;

the second edge flip-flop is used for outputting a second signal to the data selector under the control of the second clock signal and the input signal; wherein the phase of the second signal is opposite to the phase of the active pulse of the first signal;

the data selector is used for selecting the first signal or the second signal to be output through an output signal end under the control of a third clock signal;

the first clock signal is in phase opposition to the second clock signal.

In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the first edge flip-flop and the second edge flip-flop are both rising edge triggered D flip-flops or both falling edge triggered D flip-flops;

the input end of the first edge trigger is connected with the input signal, the clock signal input end of the first edge trigger is connected with the first clock signal, and the output end of the first edge trigger is connected with the first input end of the data selector;

the input end of the second edge trigger is connected with the input signal, the clock signal input end of the second edge trigger is connected with the second clock signal, and the output end of the second edge trigger is connected with the second input end of the data selector.

In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the first edge flip-flop is a D flip-flop triggered by a rising edge, and the second edge flip-flop is a D flip-flop triggered by a falling edge; or the first edge trigger is a D trigger triggered by a falling edge, and the second edge trigger is a D trigger triggered by a rising edge;

the input end of the first edge trigger is connected with the input signal, the clock signal input end of the first edge trigger is connected with the second clock signal, and the output end of the first edge trigger is connected with the first input end of the data selector;

In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the selection terminal of the data selector is connected to a third clock signal, and is configured to output the first signal received by the first input terminal when the third clock signal is a high-level signal, and output the second signal received by the second input terminal when the third clock signal is a low-level signal; or when the third clock signal is a low level signal, outputting the first signal received by the first input end, and when the third clock signal is a high level, outputting the second signal received by the second input end.

In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the data selector specifically includes: the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate; wherein,

the second input end of the first NAND gate is connected with the first input end of the second NAND gate and the second input end of the second NAND gate and is a selection end of the data selector;

the output end of the first NAND gate is connected with the first input end of the fourth NAND gate;

the output end of the second NAND gate is connected with the first input end of the third NAND gate;

the output end of the third NAND gate is connected with the second input end of the fourth NAND gate;

the output end of the fourth NAND gate is connected with the output signal end of the shift register;

the first input end of the first nand gate is the first input end of the data selector, and the second input end of the third nand gate is the second input end of the data selector; or the first input end of the first nand gate is the second input end of the data selector, and the second input end of the third nand gate is the first input end of the data selector.

Further, in the shift register provided in the embodiment of the present invention, when both the first edge flip-flop and the second edge flip-flop are rising edge triggered D flip-flops, or the first edge flip-flop is a falling edge triggered D flip-flop and the second edge flip-flop is a rising edge triggered D flip-flop, a valid pulse of the input signal is delayed within 90 degrees with respect to a rising edge of the second clock signal; and the width of the effective pulse of the input signal is 1/2 period width of the second clock signal;

when the first edge trigger and the second edge trigger are both falling edge triggered D triggers, or the first edge trigger is a rising edge triggered D trigger, and the second edge trigger is a falling edge triggered D trigger, the effective pulse of the input signal is delayed within 90 degrees relative to the falling edge of the second clock signal; and the width of the active pulse of the input signal is 1/2 cycles of the second clock signal.

Further, in the shift register provided in the embodiment of the present invention, when both the first edge flip-flop and the second edge flip-flop are rising edge triggered D flip-flops, or when the first edge flip-flop is a falling edge triggered D flip-flop and the second edge flip-flop is a rising edge triggered D flip-flop, the third clock signal is the second clock signal, the first input end of the first nand gate is the second input end of the data selector, and the second input end of the third nand gate is the first input end of the data selector;

when the first edge flip-flop and the second edge flip-flop are both D flip-flops triggered by a rising edge, the third clock signal is the first clock signal, the first input end of the first nand gate is the first input end of the data selector, and the second input end of the third nand gate is the second input end of the data selector;

when the first edge flip-flop and the second edge flip-flop are both falling edge triggered D flip-flops, or when the first edge flip-flop is a rising edge triggered D flip-flop and the second edge flip-flop is a falling edge triggered D flip-flop, the third clock signal is the second clock signal, the first input end of the first nand gate is the first input end of the data selector, and the second input end of the third nand gate is the second input end of the data selector;

when the first edge flip-flop and the second edge flip-flop are both D flip-flops triggered by a falling edge, the third clock signal is the first clock signal, the first input end of the first nand gate is the second input end of the data selector, and the second input end of the third nand gate is the first input end of the data selector.

Correspondingly, an embodiment of the present invention further provides a driving method of a shift register, where the shift register includes: a first edge trigger, a second edge trigger and a data selector; the driving method includes:

inputting a first clock signal and an input signal or a second clock signal and the input signal to the first edge flip-flop, and simultaneously inputting the second clock signal and the input signal to the second edge flip-flop;

the first edge trigger outputs a first signal to the data selector after receiving the first clock signal and the input signal or the second clock signal and the input signal; wherein a width of the active pulse of the first signal is 2 times a width of the active pulse of the input signal, the active pulse of the first signal is in the same phase as the active pulse of the input signal, and the active pulse of the first signal is delayed from the active pulse of the input signal by 1/2 cycles of the first clock signal or 1/2 cycles of the second clock signal;

the second edge flip-flop outputs a second signal to the data selector after receiving the second clock signal and the input signal; wherein the phase of the second signal is opposite to the phase of the active pulse of the first signal;

the data selector receives a third clock signal while receiving the first signal and the second signal, and selects to output the first signal or the second signal according to the third clock signal;

the first clock signal is in phase opposition to the second clock signal.

Preferably, in the driving method provided by the embodiment of the present invention, the first edge flip-flop and the second edge flip-flop are both rising edge triggered D flip-flops, or the first edge flip-flop is a falling edge triggered D flip-flop, and the second edge flip-flop is a rising edge triggered D flip-flop;

the effective pulse of the input signal is delayed within 90 degrees relative to the rising edge of the second clock signal; and the width of the effective pulse of the input signal is 1/2 period width of the second clock signal;

the third clock signal is the same as the first clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a high-level signal, and outputs the second signal received by the second input terminal when the third clock signal is a low-level signal; or the third clock signal is the same as the second clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a low-level signal, and outputs the second signal received by the second input terminal when the third clock signal is a high-level signal.

Preferably, in the driving method provided by the embodiment of the present invention, the first edge flip-flop and the second edge flip-flop are both D flip-flops triggered by falling edges, or the first edge flip-flop is a D flip-flop triggered by rising edges, and the second edge flip-flop is a D flip-flop triggered by falling edges;

the effective pulse of the input signal is delayed within 90 degrees relative to the falling edge of the second clock signal; and the width of the effective pulse of the input signal is 1/2 period width of the second clock signal;

the third clock signal is the same as the first clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a low-level signal, and outputs the second signal received by the second input terminal when the third clock signal is a high-level signal; or the third clock signal is the same as the second clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a high-level signal, and outputs the second signal received by the second input terminal when the third clock signal is a low-level signal.

Correspondingly, the embodiment of the invention also provides a gate driving circuit, which comprises a plurality of shift registers which are connected in series and provided by the embodiment of the invention; wherein,

the input signal of the first stage shift register is input from the initial signal end, and the input signals of the other shift registers except the first stage shift register are input from the output signal end of the shift register at the previous stage.

Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the gate driving circuits provided by the embodiment of the invention.

The shift register, the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention comprise: a first edge flip-flop, a second edge flip-flop, and a data selector, wherein; the first edge trigger is used for outputting a first signal to the data selector under the control of a first clock signal and an input signal or under the control of a second clock signal and the input signal; the second edge trigger is used for outputting a second signal to the data selector under the control of a second clock signal and the input signal; the data selector is used for selecting the first signal or the second signal to be output through the output signal terminal under the control of the third clock signal. The embodiment of the invention realizes the shift register by utilizing the edge trigger and the data selector, and the edge trigger and the data selector are both composed of the NAND gate generally, so that the circuit repeatability is high, the circuit repeatability in the shift register can be improved, and the complexity of GOA layout design is reduced. In addition, because the edge trigger has the function of keeping the output signal, a reset signal does not need to be input into the gate drive circuit consisting of a plurality of shift registers, so that a connecting line for transmitting the reset signal between two stages of shift registers can be omitted, and the complexity of GOA layout design is further reduced.

Drawings

Fig. 1a and fig. 1b are schematic structural diagrams of a shift register according to an embodiment of the present invention, respectively;

fig. 2a is a schematic structural diagram of a data selector according to an embodiment of the present invention;

FIG. 2b is a circuit timing diagram of the data selector provided in FIG. 2 a;

fig. 3a to fig. 3d are schematic diagrams illustrating timing relationships between an input signal and a second clock signal in a shift register according to an embodiment of the invention;

fig. 4a to fig. 4f are schematic structural diagrams of a shift register according to an embodiment of the present invention;

fig. 5a to fig. 5d are schematic circuit timing diagrams of a shift register according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 7 is a schematic structural diagram of a nand gate according to an embodiment of the present invention;

fig. 8 is a flowchart illustrating a driving method of a shift register according to an embodiment of the present invention.

Detailed Description

The following describes in detail specific embodiments of a shift register, a driving method thereof, a gate driving circuit, and a display device according to an embodiment of the present invention with reference to the accompanying drawings.

A shift register according to an embodiment of the present invention, as shown in fig. 1a and 1b, includes: a first edge flip-flop 100, a second edge flip-flop 200, and a data selector 300, wherein;

the first edge flip-flop 100 is configured to output a first signal Out1 to the data selector 300 under the control of the first clock signal CLK1 and the Input signal Input, as shown in fig. 1a, or under the control of the second clock signal CLK2 and the Input signal Input, as shown in fig. 1 b; the width of the effective pulse of the first signal Out1 is 2 times the width of the effective pulse of the Input signal Input, the effective pulse of the first signal Out1 has the same phase as the effective pulse of the Input signal Input, and the effective pulse of the first signal Out1 is delayed from the effective pulse of the Input signal Input by 1/2 cycles of the first clock signal CLK1 or 1/2 cycles of the second clock signal CLK 2;

the second edge flip-flop 200 is configured to output a second signal Out2 to the data selector 300 under the control of the second clock signal CLK2 and the Input signal Input; wherein the phase of the second signal Out2 is opposite to the phase of the valid pulse of the first signal Out 1;

the data selector 300 is used for selecting the first signal Out1 or the second signal Out2 to be Output through the Output signal terminal Output under the control of the third clock signal CLK 3;

the first clock signal CLK1 is in phase opposition to the second clock signal CLK 2.

The shift register provided in the embodiment of the present invention includes: a first edge flip-flop, a second edge flip-flop, and a data selector, wherein; the first edge trigger is used for outputting a first signal to the data selector under the control of a first clock signal and an input signal or under the control of a second clock signal and the input signal; the second edge trigger is used for outputting a second signal to the data selector under the control of a second clock signal and the input signal; the data selector is used for selecting the first signal or the second signal to be output through the output signal terminal under the control of the third clock signal. The embodiment of the invention realizes the shift register by utilizing the edge trigger and the data selector, and the edge trigger and the data selector are both composed of the NAND gate generally, so that the circuit repeatability is high, the circuit repeatability in the shift register can be improved, and the complexity of GOA layout design is reduced. In addition, because the edge trigger has the function of keeping the output signal, a reset signal does not need to be input into the gate drive circuit consisting of a plurality of shift registers, so that a connecting line for transmitting the reset signal between two stages of shift registers can be omitted, and the complexity of GOA layout design is further reduced.

Specifically, in the shift register provided in the embodiment of the present invention, both the first edge flip-flop and the second edge flip-flop may be flip-flops triggered by rising edges or both flip-flops triggered by falling edges, and certainly, the first edge flip-flop may be a flip-flop triggered by rising edges, and the second edge flip-flop may be a flip-flop triggered by falling edges, or the first edge flip-flop is a flip-flop triggered by falling edges and the second edge flip-flop is a flip-flop triggered by rising edges, which is not limited herein.

Specifically, when the first edge flip-flop and the second edge flip-flop may be both rising edge triggered flip-flops or both falling edge triggered flip-flops, the clock signal controlling the first edge flip-flop and the clock signal controlling the second edge flip-flop are clock signals with opposite phases. When the first edge trigger is a rising edge triggered trigger, the second edge trigger is a falling edge triggered trigger, or the first edge trigger is a falling edge triggered trigger and the second edge trigger is a rising edge triggered trigger, the clock signal for controlling the first edge trigger and the clock signal for controlling the second edge trigger are the same clock signal.

Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 1a, the first edge flip-flop 100 and the second edge flip-flop 200 may be both rising edge triggered D flip-flops, or the first edge flip-flop 100 and the second edge flip-flop 200 may be both falling edge triggered D flip-flops;

the Input end D of the first edge flip-flop 100 is connected to the Input signal Input, the clock signal Input end Clk of the first edge flip-flop 100 is connected to the first clock signal Clk1, and the output end Q of the first edge flip-flop is connected to the first Input end a of the data selector 300;

the Input D of the second edge flip-flop 200 is coupled to the Input signal Input, the clock signal Input Clk of the second edge flip-flop 200 is coupled to the second clock signal Clk2, and the output Q of the second edge flip-flop 200 is coupled to the second Input B of the data selector 300.

Alternatively, in the shift register provided in the embodiment of the present invention, as shown in fig. 1b, the first edge flip-flop 100 is a D flip-flop triggered by a falling edge, and the second edge flip-flop 200 is a D flip-flop triggered by a rising edge; or the first edge flip-flop 100 is a D flip-flop triggered by a rising edge, and the second edge flip-flop 200 is a D flip-flop triggered by a falling edge;

the Input end D of the first edge flip-flop 100 is connected to the Input signal Input, the clock signal Input Clk of the first edge flip-flop 100 is connected to the second clock signal Clk2, and the output end Q of the first edge flip-flop 100 is connected to the first Input end a of the data selector 001;

the Input D of the second edge flip-flop 200 is connected to the Input signal Input, the clock signal Input Clk of the second edge flip-flop 200 is connected to the second clock signal Clk2, and the output Q of the second edge flip-flop 200 is connected to the second Input B of the data selector 002.

Specifically, in the shift register provided in the embodiment of the present invention, the specific structures of the rising edge triggered D flip-flop and the falling edge triggered D flip-flop are the same as those of the existing rising edge triggered D flip-flop and falling edge triggered D flip-flop, and are not described in detail herein.

Specifically, in the shift register provided in the embodiment of the present invention, the working principle of the rising edge triggered D flip-flop is as follows: when the clock signal at the clock signal input end changes from low potential to high potential, the trigger can latch and latch the signal at the current input end D, output the signal at the current input end D from the output end Q, and keep the signal at the output end Q as the signal at the current input end D until the next time the clock signal changes from low potential to high potential. The working principle of the D trigger triggered by the falling edge is as follows: when the clock signal at the clock signal input end changes from high potential to low potential, the trigger can latch and latch the signal at the current input end D, output the signal at the current input end D from the output end Q, and keep the signal at the output end Q as the signal at the current input end D until the next time the clock signal changes from high potential to low potential.

Specifically, the shift register provided in the embodiment of the present invention is only illustrated by taking an edge flip-flop as an edge triggered D flip-flop, and may be other edge triggered flip-flops, which is not limited herein.

Further, in the shift register provided in the embodiment of the present invention, as shown in fig. 1a and 1B, the selection terminal S of the data selector 300 is connected to the third clock signal CLK3, and is configured to output the first signal Out1 received by the first input terminal a when the third clock signal CLK3 is a high-level signal, and output the second signal Out2 received by the second input terminal B when the third clock signal CLK3 is a low-level signal; or when the third clock signal CLK3 is a low level signal, the first signal Out1 received by the first input terminal a is output, and when the third clock signal CLK3 is a high level signal, the second signal Out2 received by the second input terminal B is output.

Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a, the data selector 300 specifically includes: a first nand gate 301, a second nand gate 302, a third nand gate 303 and a fourth nand gate 304; wherein,

a second input end of the first nand gate 301 is connected with a first input end of the second nand gate 302 and a second input end of the second nand gate 302, and is a selection end S of the data selector 300;

the output end of the first nand gate 301 is connected with the first input end of the fourth nand gate 304;

the output end of the second nand gate 302 is connected with the first input end of the third nand gate 303;

the output end of the third nand gate 303 is connected with the second input end of the fourth nand gate 304;

the Output end of the fourth nand gate 304 is connected with the Output signal end Output of the shift register;

a first input terminal of the first nand gate 301 is a first input terminal a of the data selector 300, and a second input terminal of the third nand gate 303 is a second input terminal B of the data selector 300; or the first input terminal of the first nand gate 301 is the second input terminal B of the data selector 300, and the second input terminal of the third nand gate 303 is the first input terminal a of the data selector 300.

The above is merely an example of the specific structure of the data selector in the shift register, and in the specific implementation, the specific structure of the data selector is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known by those skilled in the art, and is not limited herein.

Specifically, when the data selector in the shift register provided by the embodiment of the present invention adopts the four nand gates as a specific structure, the working principle is as follows: 1. when the signal at the select terminal S is high, the signal at the output terminal of the second nand gate 302 is low, and at this time, the signal at the output terminal of the third nand gate 303 is high no matter the signal at the second input terminal of the third nand gate 303 is high or low; when the signal at the selection end S is at a high potential, and when the signal at the first input end of the first nand gate 301 is at a high potential, the signal at the output end of the first nand gate 301 is at a low potential; the signal at the output of the fourth nand gate 304 is high; when the signal at the selection end S is at a high potential, and when the signal at the first input end of the first nand gate 301 is at a low potential, the signal at the output end of the first nand gate 301 is at a high potential; the signal at the output of the fourth nand gate 304 is low; that is, when the signal at the select terminal S is at a high level, the signal at the output terminal of the fourth nand gate 304 is identical to the signal at the first input terminal of the first nand gate 301; 2. when the signal at the selection end S is at a low potential, the signal at the output end of the first nand gate 301 is at a high potential no matter the signal at the first input end of the first nand gate 301 is at a high potential or a low potential; when the signal at the select terminal S is at a low potential, the signal at the output terminal of the second nand gate 302 is at a high potential, and at this time, when the signal at the second input terminal of the third nand gate 303 is at a high potential, the signal at the output terminal of the third nand gate 303 is at a low potential, and the signal at the output terminal of the fourth nand gate 304 is at a high potential; when the signal at the second input terminal of the third nand gate 303 is at a low potential, the signal at the output terminal of the third nand gate 303 is at a high potential, and the signal at the output terminal of the fourth nand gate 304 is at a low potential; that is, when the signal at the select terminal S is low, the signal at the output terminal of the fourth nand gate 304 is identical to the signal at the second input terminal of the third nand gate 303.

Specifically, the timing chart of the input and output signals of the select terminal, the first input terminal of the first nand gate 301, the second input terminal of the third nand gate 303, and the output terminal of the fourth nand gate 304 is shown in fig. 2b, where 301_1 in fig. 2b represents the signal of the first input terminal of the first nand gate 301, 303_2 represents the signal of the second input terminal of the third nand gate 303, 304_ O represents the signal of the output terminal of the fourth nand gate 304, and S represents the signal of the select terminal.

Further, in the shift register provided by the embodiment of the present invention, a specific structure of the nand gate may include three N-type switching transistors T1, T2, and T3 connected in series as shown in fig. 7; wherein,

a first switch transistor T1, having a gate being a first input terminal In1 of the nand gate, a source connected to the first reference voltage terminal VSS, and a drain connected to the source of the second switch transistor T2;

a second switch transistor T2, the gate of which is a second input terminal In2 of the nand gate, and the drain of which is connected to the drain of the third switch transistor T3 and the output terminal Out of the nand gate, respectively;

and a third switching transistor T3 having a gate and a source connected to the second reference voltage terminal VDD.

The nand structure is merely illustrated, and in particular, in the implementation, the nand structure may also be another existing structure, which is not limited herein.

Further, in the shift register provided in the embodiment of the present invention, when both the first edge flip-flop and the second edge flip-flop are rising edge triggered D flip-flops, or the first edge flip-flop is a falling edge triggered D flip-flop and the second edge flip-flop is a rising edge triggered D flip-flop, as shown in fig. 3a and 3b, the effective pulse of the Input signal Input is delayed within 90 degrees (as shown by θ in fig. 3a and 3 b) with respect to the rising edge of the second clock signal CLK 2; and the width of the active pulse of the Input signal is 1/2 cycles of the second clock signal CLK 2;

when the first edge flip-flop and the second edge flip-flop are both falling-edge triggered D flip-flops, or the first edge flip-flop is a rising-edge triggered D flip-flop and the second edge flip-flop is a falling-edge triggered D flip-flop, as shown in fig. 3c and 3D, the effective pulse of the Input signal Input is delayed within 90 degrees from the falling edge of the second clock signal CLK2 (as shown by θ in fig. 3c and 3D); and the width of the active pulse of the Input signal Input is 1/2 cycles of the second clock signal CLK 2.

Specifically, in the shift register provided in the embodiment of the present invention, the input signal may be an active pulse when the input signal is at a high level, or may be an active pulse when the input signal is at a low level, which is not limited herein. In fig. 3a and 3c, the active pulse is taken as an example when the Input signal Input is at a high level, and in fig. 3b and 3d, the active pulse is taken as an example when the Input signal Input is at a low level.

In a specific implementation, in the shift register provided in the embodiment of the present invention, the third clock signal for controlling the data selector may be the same as the first clock signal, or the same as the second clock signal, which is not limited herein.

Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 4a, when the first edge flip-flop 100 and the second edge flip-flop 200 are both rising edge triggered D flip-flops, or as shown in fig. 4B, when the first edge flip-flop 100 is a falling edge triggered D flip-flop and the second edge flip-flop 200 is a rising edge triggered D flip-flop, the third clock signal CLK3 is the second clock signal CLK2, the first input terminal of the first nand gate 301 is the first input terminal a of the data selector 300, and the second input terminal of the third nand gate 303 is the second input terminal B of the data selector 300;

as shown in fig. 4c, when the first edge flip-flop 100 and the second edge flip-flop 200 are both rising edge triggered D flip-flops, the third clock signal CLK3 is the first clock signal CLK1, the first input terminal of the first nand gate 301 is the first input terminal a of the data selector 300, and the second input terminal of the third nand gate 303 is the second input terminal B of the data selector 300;

as shown in fig. 4D, when the first edge flip-flop 100 and the second edge flip-flop 200 are both falling-edge triggered D flip-flops, or as shown in fig. 4e, when the first edge flip-flop 100 is a rising-edge triggered D flip-flop and the second edge flip-flop 200 is a falling-edge triggered D flip-flop, the third clock signal CLK3 is the second clock signal CLK2, the first input terminal of the first nand gate 301 is the first input terminal a of the data selector 300, and the second input terminal of the third nand gate 303 is the second input terminal B of the data selector 300;

as shown in fig. 4f, when the first edge flip-flop 100 and the second edge flip-flop 200 are both falling edge triggered D flip-flops, the third clock signal CLK3 is the first clock signal CLK1, the first input terminal of the first nand gate 301 is the second input terminal B of the data selector 300, and the second input terminal of the third nand gate 303 is the first input terminal a of the data selector 300.

The operation of the shift register according to the embodiment of the present invention will be described below by taking the shift registers shown in fig. 4a to 4f as examples. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.

Example one:

the operation of the shift register is described by taking the structure of the shift register shown in fig. 4a as an example, and the corresponding input/output timing diagram is shown in fig. 5 a. Specifically, five times T1, T2, T3, T4 and T5 in the input-output timing diagram shown in fig. 5a and four stages T1, T2, T3 and T4 located between the 5 times are selected.

At time t1, the Input signal Input remains at 0, the first clock signal CLK1 changes from 1 to 0, and the first edge flip-flop is a rising edge controlled D flip-flop, so the first signal Out1 output by the first edge flip-flop is still at 0 in accordance with Input before time t 1; the second clock signal CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still consistent with the Input before time t1 at time t1 and after a delay time, the second signal Out2 output by the second edge flip-flop is still consistent with the Input at time t1 and is still 0.

At the stage T1, Input changes from 0 to 1, CLK1 equals 0, and CLK2 equals 1, and since both CLK1 and CLK2 do not change, the first signal Out1 output by the first edge flip-flop is still 0, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, since CLK2 is 1, CLK2 controls the data selector to Output the second signal Out2 input to the second input terminal thereof to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time T2, Input is kept at 1, CLK2 changes from 1 to 0, and since the second edge flip-flop is a rising edge controlled D flip-flop, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with Out2 at stage T1; CLK1 changes from 0 to 1, and since the first edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK1 triggers the first edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the first signal Out1 output by the first edge flip-flop still coincides with the output 1 at the T1 stage at time T2 and is 0, and after a delay time, the first signal Out1 output by the first edge flip-flop coincides with the Input at time T2 and becomes 1.

At the stage T2, Input changes from 1 to 0, and since both CLK1 and CLK2 do not change, the first signal Out1 output by the first edge flip-flop changes from 0 to 1 after a delay time and keeps at 1 all the time, and the second signal Out2 output by the second edge flip-flop is still at 0; at this stage, since CLK2 is 0, CLK2 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output changes from 0 to 1 after a delay time and remains 1 all the time.

At time T3, Input is kept at 0, CLK1 changes from 1 to 0, and since the first edge flip-flop is a rising edge controlled D flip-flop, the first signal Out1 output by the first edge flip-flop is still consistent with Out1 at stage T2 as 1; CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still 0 at time T3 in accordance with the output Out2 at time T2, and after a delay time, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with the Input at time T3.

At stage T3, Input remains at 0, and since both CLK1 and CLK2 have not changed, the first signal Out1 output by the first edge flip-flop is still 1, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, since CLK2 is 1, CLK2 controls the data selector to Output the second signal Out2 input to its second input terminal to the Output signal terminal Output of the shift register, and the signal of Output changes from 1 to 0 and remains at 0 all the time after a delay time due to the delay of signal transmission.

At time T4, Input is kept at 0, CLK2 changes from 1 to 0, and since the second edge flip-flop is a rising edge controlled D flip-flop, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with Out2 at stage T3; CLK1 changes from 0 to 1, and since the first edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK1 triggers the first edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the first signal Out1 output by the first edge flip-flop still coincides with the output 2 at the T3 stage at time T4 to be 1, and after a delay time, the first signal Out1 output by the first edge flip-flop coincides with the Input at time T4 to be 0.

At stage T4, Input is kept at 0, and since neither CLK1 nor CLK2 changes, the first signal Out1 output by the first edge flip-flop changes from 1 to 0 after a delay time and keeps at 0 all the time, and the second signal Out2 output by the second edge flip-flop is still at 0; at this stage, since CLK2 is equal to 0, CLK2 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time T5, Input is kept at 0, CLK1 changes from 1 to 0, and since the first edge flip-flop is a rising edge controlled D flip-flop, the first signal Out1 output by the first edge flip-flop is still consistent with Out1 at stage T4 and is 0; CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still 0 at time T5 in accordance with the output Out2 at time T4, and after a delay time, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with the Input at time T5.

The shift register realizes the function of the shift register by utilizing the edge trigger and the data selector, and the edge trigger and the data selector are both composed of NAND gates generally, so that the circuit repeatability is high, the circuit repeatability in the shift register can be improved, and the complexity of GOA layout design is reduced. In addition, because the edge trigger has the function of keeping the output signal, a reset signal does not need to be input into the gate drive circuit consisting of a plurality of shift registers, so that a connecting line for transmitting the reset signal between two stages of shift registers can be omitted, and the complexity of GOA layout design is further reduced.

Example two:

the operation of the shift register is described by taking the structure of the shift register shown in fig. 4b as an example, and the corresponding input/output timing diagram is shown in fig. 5 b. Specifically, five times T1, T2, T3, T4 and T5 in the input-output timing diagram shown in fig. 5b and four stages T1, T2, T3 and T4 located between the 5 times are selected.

At time t1, the Input signal Input remains at 0, the second clock signal CLK2 changes from 0 to 1, and the first edge flip-flop is a falling edge controlled D flip-flop, so the first signal Out1 output by the first edge flip-flop is still consistent with the Input before time t1 being 0; the second clock signal CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still consistent with the Input before time t1 at time t1 and after a delay time, the second signal Out2 output by the second edge flip-flop is still consistent with the Input at time t1 and is still 0.

At stage T1, Input changes from 0 to 1, CLK2 equals 1, and since CLK2 does not change, the first signal Out1 output by the first edge flip-flop is still 0, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, since CLK2 is 1, CLK2 controls the data selector to Output the second signal Out2 input to the second input terminal thereof to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time T2, Input is kept at 1, CLK2 changes from 1 to 0, and since the second edge flip-flop is a rising edge controlled D flip-flop, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with Out2 at stage T1; CLK2 changes from 1 to 0, and since the first edge flip-flop is a falling edge controlled D flip-flop, the falling edge of CLK2 triggers the first edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the first signal Out1 output by the first edge flip-flop still coincides with the output 1 at the T1 stage at time T2 and is 0, and after a delay time, the first signal Out1 output by the first edge flip-flop coincides with the Input at time T2 and is 1.

At stage T2, Input changes from 1 to 0, and since CLK2 does not change, the first signal Out1 output by the first edge flip-flop changes from 0 to 1 after a delay time and keeps at 1 all the time, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, since CLK2 is 0, CLK2 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output changes from 0 to 1 after a delay time and remains 1 all the time.

At time T3, Input is kept at 0, CLK2 changes from 0 to 1, and since the first edge flip-flop is a falling edge controlled D flip-flop, the first signal Out1 output by the first edge flip-flop is still consistent with Out1 at stage T2 as 1; CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still 0 at time T3 in accordance with the output Out2 at time T2, and after a delay time, the second signal Out2 output by the first edge flip-flop is still 0 in accordance with the Input at time T3.

At stage T3, Input remains at 0, and since CLK2 has not changed, the first signal Out1 output by the first edge flip-flop is still 1, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, since CLK2 is 1, CLK2 controls the data selector to Output the second signal Out2 input to its second input terminal to the Output signal terminal Output of the shift register, and the signal of Output changes from 1 to 0 and remains at 0 all the time after a delay time due to the delay of signal transmission.

At time T4, Input is kept at 0, CLK2 changes from 1 to 0, and since the second edge flip-flop is a rising edge controlled D flip-flop, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with Out2 at stage T3; CLK2 changes from 1 to 0, and since the first edge flip-flop is a falling edge controlled D flip-flop, the falling edge of CLK2 triggers the first edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the first signal Out1 output by the first edge flip-flop still coincides with the output 2 at the T3 stage at time T4 and is 1, and after a delay time, the first signal Out1 output by the first edge flip-flop coincides with the Input at time T4 and becomes 0.

At stage T4, Input is kept at 0, and since CLK2 has not changed, the first signal Out1 output by the first edge flip-flop changes from 1 to 0 after a delay time and keeps at 0 all the time, and the second signal Out2 output by the second edge flip-flop is still at 0; at this stage, since CLK2 is equal to 0, CLK2 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time T5, Input is kept at 0, CLK2 changes from 0 to 1, and since the first edge flip-flop is a falling edge controlled D flip-flop, the first signal Out1 output by the first edge flip-flop is still consistent with Out1 at stage T4 as 0; CLK2 changes from 0 to 1, and since the second edge flip-flop is a rising edge controlled D flip-flop, the rising edge of CLK2 triggers the second edge flip-flop to latch and output the Input at the current time, and since the flip-flop generally has some delay, the second signal Out2 output by the second edge flip-flop is still 0 at time T5 in accordance with the output Out2 at time T4, and after a delay time, the second signal Out2 output by the second edge flip-flop is still 0 in accordance with the Input at time T5.

Example three:

the operation of the shift register is described by taking the structure of the shift register shown in fig. 4c as an example, and the corresponding input/output timing diagram is the same as that of fig. 5 a. Specifically, five times T1, T2, T3, T4 and T5 in the input-output timing diagram shown in fig. 5a and four stages T1, T2, T3 and T4 located between the 5 times are selected.

At time t1, the operation principle is the same as that at time t1 in the first embodiment, and the detailed description is omitted here.

At stage T1, the first signal Out1 output by the first edge flip-flop is still 0, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, CLK1 is equal to 0, and CLK1 controls the data selector to Output the second signal Out2 input to the second input terminal of the data selector to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time t2, the operation principle is the same as that at time t2 in the first embodiment, and the detailed description is omitted here.

At stage T2, the first signal Out1 output by the first edge flip-flop changes from 0 to 1 after a delay time and keeps at 1 all the time, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, CLK1 is 1, and CLK1 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output changes from 0 to 1 after a delay time and remains 1 all the time.

At time t3, the operation principle is the same as that at time t3 in the first embodiment, and the detailed description is omitted here.

At stage T3, the first signal Out1 output by the first edge flip-flop is still 1, and the second signal Out2 output by the second edge flip-flop is still 0; at this stage, CLK1 is 0, and CLK1 controls the data selector to Output the second signal Out2 input to its second input terminal to the Output signal terminal Output of the shift register, and the signal of Output changes from 1 to 0 after a delay time and remains at 0 all the time due to the delay of signal transmission.

At time t4, the operation principle is the same as that at time t4 in the first embodiment, and the detailed description is omitted here.

At stage T4, the first signal Out1 output by the first edge flip-flop changes from 1 to 0 after a delay time and keeps at 0 all the time, and the second signal Out2 output by the second edge flip-flop is still at 0; at this stage, CLK1 is 1, and CLK1 controls the data selector to Output the first signal Out1 input to its first input terminal to the Output signal terminal Output of the shift register, so that the signal of Output is 0.

At time t5, the operation principle is the same as that at time t5 in the first embodiment, and the detailed description is omitted here.

Example four:

specifically, the structure of the shift register shown in fig. 4D is similar to the operating principle of the shift register in the first example for illustrating the operating process thereof, and the difference is that the first edge flip-flop and the second edge flip-flop in the first example are both rising edge triggered D flip-flops, so that the rising edge time of the first clock signal and the rising edge time of the second clock signal respectively latch the Input at the current time and output the Input, while in the fourth example, the first edge flip-flop and the second edge flip-flop are both falling edge triggered D flip-flops, so that the falling edge time of the first clock signal and the falling edge time of the second clock signal respectively latch the Input at the current time and output the Input, which is not described herein again, and the specific timing diagram of the fourth example is shown in fig. 5 c.

Example five:

specifically, the structure of the shift register shown in fig. 4e is similar to the operating principle of the shift register in the second example for the operating process, and the difference is that the first edge flip-flop in the second example is a D flip-flop triggered by falling, and the second edge flip-flop is a D flip-flop triggered by rising, so that the first edge flip-flop latches and outputs the Input at the current time at the time of falling of the first clock signal, and the second edge flip-flop latches and outputs the Input at the current time at the time of rising of the second clock signal; in the fifth embodiment, the first edge flip-flop is a rising edge triggered D flip-flop, and the second edge flip-flop is a falling edge triggered D flip-flop, so that the first edge flip-flop latches and outputs the Input at the current time at the rising edge of the first clock signal, and the second edge flip-flop latches and outputs the Input at the current time at the falling edge of the second clock signal.

Example six:

specifically, the structure of the shift register shown in fig. 4f is similar to the working principle of the shift register in example four in the working process thereof, the working timing diagram is also the same as the working timing diagram corresponding to example four, detailed description of the working process is omitted here, and the specific timing diagram of example six is shown in fig. 5 c.

Specifically, the above six examples of the present invention are described by taking the valid pulse of the input signal as the high level signal as an example, the principle that the valid pulse of the Output signal is the low level signal is the same, and the corresponding timing diagram only needs to invert the phases of Out1, Out2, and Output in fig. 5a to 5d, and the specific working process is not repeated here.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 6, including a plurality of shift registers connected in series: SR (1), SR (2) … SR (N) … SR (N-1), SR (N) (N shift registers in total, N is more than or equal to 1 and less than or equal to N), the Input signal Input of the first stage shift register SR (1) is Input from the start signal end STV, and the Input signals Input of the other shift registers SR (N) are Input from the Output signal end Output _ N-1 of the previous stage shift register SR (N-1) except the first stage shift register SR (1). The gate driving circuit sequentially outputs the gate driving signals Output from the Output signal terminal Output _ n of each stage of the shift register sr (n).

Further, in the gate driving circuit provided in the embodiment of the present invention, the clock signal is input to each shift register.

Specifically, the specific structure of each shift register in the gate driving circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the gate driving circuit, where the gate driving circuit provides a scan signal for each gate line on an array substrate in the display device, and specific implementation of the display device may refer to the description of the gate driving circuit, and details of the same are omitted.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a shift register, where the shift register is shown in fig. 1a and 1b, and includes: a first edge flip-flop 100, a second edge flip-flop 200, and a data selector 300; as shown in fig. 8, the driving method may include the steps of:

s801, inputting a first clock signal and an input signal or a second clock signal and an input signal to a first edge trigger, and simultaneously inputting a second clock signal and an input signal to a second edge trigger;

s802, after receiving a first clock signal and an input signal or a second clock signal and the input signal, the first edge trigger outputs a first signal to the data selector;

the width of the effective pulse of the first signal is 2 times of the width of the effective pulse of the input signal, the effective pulse of the first signal has the same phase with the effective pulse of the input signal, and the effective pulse of the first signal is delayed by 1/2 cycles of the first clock signal or 1/2 cycles of the second clock signal relative to the effective pulse of the input signal;

s803, the second edge trigger outputs a second signal to the data selector after receiving the second clock signal and the input signal;

wherein the phase of the second signal is opposite to the phase of the effective pulse of the first signal;

s804, the data selector receives the first signal and the second signal and simultaneously receives a third clock signal, and selects to output the first signal or the second signal according to the third clock signal;

the first clock signal is in phase opposition to the second clock signal.

Specifically, in practical implementation, when both the first edge flip-flop and the second edge flip-flop are rising edge triggered D flip-flops, or the first edge flip-flop is a falling edge triggered D flip-flop, and the second edge flip-flop is a rising edge triggered D flip-flop:

the third clock signal is the same as the first clock signal, and the data selector outputs the first signal received by the first input end when the third clock signal is a high-level signal and outputs the second signal received by the second input end when the third clock signal is a low-level signal; or the third clock signal is the same as the second clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a low-level signal and outputs the second signal received by the second input terminal when the third clock signal is a high-level signal.

Or, specifically, in practical implementation, when both the first edge flip-flop and the second edge flip-flop are D flip-flops triggered by a falling edge, or the first edge flip-flop is a D flip-flop triggered by a rising edge, and the second edge flip-flop is a D flip-flop triggered by a falling edge:

the third clock signal is the same as the first clock signal, the data selector outputs the first signal received by the first input end when the third clock signal is a low-level signal, and outputs the second signal received by the second input end when the third clock signal is a high-level signal; or the third clock signal is the same as the second clock signal, and the data selector outputs the first signal received by the first input terminal when the third clock signal is a high-level signal and outputs the second signal received by the second input terminal when the third clock signal is a low-level signal.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register, comprising: a first edge flip-flop, a second edge flip-flop, and a data selector, wherein;

the first clock signal is in phase opposition to the second clock signal.

2. The shift register of claim 1, wherein the first edge flip-flop and the second edge flip-flop are both rising edge triggered D flip-flops or both falling edge triggered D flip-flops;

3. The shift register of claim 1, wherein the first edge flip-flop is a rising edge triggered D flip-flop, and the second edge flip-flop is a falling edge triggered D flip-flop; or the first edge trigger is a D trigger triggered by a falling edge, and the second edge trigger is a D trigger triggered by a rising edge;

4. A shift register as claimed in claim 2 or 3, characterized in that the selection terminal of the data selector is connected to a third clock signal for outputting the first signal received at the first input terminal when the third clock signal is a high level signal and outputting the second signal received at the second input terminal when the third clock signal is a low level signal; or when the third clock signal is a low level signal, the first signal received by the first input terminal is output, and when the third clock signal is a high level, the second signal received by the second input terminal is output.

5. The shift register of claim 4, wherein the data selector specifically comprises: the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate; wherein,

6. The shift register of claim 5, wherein:

when the first edge trigger and the second edge trigger are both rising edge triggered D triggers, or the first edge trigger is a falling edge triggered D trigger, and the second edge trigger is a rising edge triggered D trigger, the effective pulse of the input signal is delayed within 90 degrees relative to the rising edge of the second clock signal; and the width of the effective pulse of the input signal is 1/2 period width of the second clock signal;

7. The shift register of claim 6, wherein:

when the first edge flip-flop and the second edge flip-flop are both rising edge triggered D flip-flops, or when the first edge flip-flop is a falling edge triggered D flip-flop and the second edge flip-flop is a rising edge triggered D flip-flop, the third clock signal is the second clock signal, the first input end of the first nand gate is the second input end of the data selector, and the second input end of the third nand gate is the first input end of the data selector;

8. A method of driving a shift register, the shift register comprising: a first edge trigger, a second edge trigger and a data selector; the driving method includes:

the first clock signal is in phase opposition to the second clock signal.

9. The driving method according to claim 8, characterized in that: the first edge trigger and the second edge trigger are both D triggers triggered by rising edges, or the first edge trigger is a D trigger triggered by falling edges, and the second edge trigger is a D trigger triggered by rising edges;

10. The driving method according to claim 8, characterized in that: the first edge trigger and the second edge trigger are both D triggers triggered by falling edges, or the first edge trigger is a D trigger triggered by rising edges, and the second edge trigger is a D trigger triggered by falling edges;

11. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 7 connected in series; wherein,

12. A display device comprising the gate driver circuit according to claim 11.