CN205028629U - A drive circuit , In -cell touch panel and display device for touch -sensitive screen - Google Patents
A drive circuit , In -cell touch panel and display device for touch -sensitive screen Download PDFInfo
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Abstract
The utility model discloses a drive circuit, in -cell touch panel and display device for touch -sensitive screen controls supply circuit through time schedule controller and at the clock signal that the output of the shift register of very first time duan xiangdi N+1 -n level to the N level in demonstration stage has first amplitude, controls supply circuit and export the clock signal who has the second amplitude to shift register at different levels at the second time quantum that shows the stage, so that the height of the scanning signal's of the shift register of N+1 -n level to N level output current potential than the output of other grade of shift register, even thereby can guarantee that these scanning signal can attenuate in the touch time section, but the current potential after the decay still can guarantee the N+1 level to N+n level shift register can the normal output, and then solved among the prior art because scanning signal attenuate the N+1 that leads to and walked to the short and display effect problem dark partially of production of the capable pixel's of N+n charge time in the touch time section.
Description
Technical field
The utility model relates to technical field of touch control, espespecially a kind of driving circuit for touch-screen, In-cell touch panel and display device.
Background technology
Along with the develop rapidly of display technique, display presents the development trend of high integration and low cost.Wherein, GOA (GateDriveronArray, array base palte row cutting) technology is by TFT (ThinFilmTransistor, thin film transistor (TFT)) gate switch circuit be integrated in display panel array base palte on to form the turntable driving to display panel, thus grid integrated circuits (IC can be saved, IntegratedCircuit) binding (Bonding) region and the wiring space in fan-out (Fan-out) region, not only can reduce cost of products in material cost and manufacture craft two, and display panel can be made to accomplish the design for aesthetic of both sides symmetry and narrow frame, further, this integrated technique can also save the Bonding technique in controlling grid scan line direction, thus improves production capacity and yield.
Usually, gate driver circuit is made up of multiple shift registers of cascade usually, and an output signal end corresponding grid line respectively of shift register at different levels, for exporting sweep signal to many grid lines line by line successively.The resolution required along with large-sized monitor is more and more higher, gate driver circuit realizes often through precharge, namely the shift registers at different levels in gate driver circuit export according to the order of sequence, each clock signal has the overlapping of 1/n pulse width successively, makes when the sweep signal of shift register output of prime and the sweep signal of upper level shift register output have the overlapping of 1/n pulse width.For n=3, as shown in Figure 1a, gate driver circuit generally needs connection 6 clock cables (CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6), in gate driver circuit, except rear 3 grades of shift registers (in Fig. 1 a SR (M), SR (M-1) and SR (M-2)), the output signal end Output_m of shift register SR (m) at different levels is connected with the input signal end Input of 3rd level shift register SR (m+3) thereafter respectively; Sequential chart corresponding to gate driver circuit as shown in Figure 1 b, the sequential of the sweep signal that the output signal end Output that wherein illustrate only front 8 grades of shift registers in Fig. 1 b exports.
But in the display device that touch-control and display timesharing drive, need within the time period of display one frame, insert multiple touch-control time period, with n=3, and the shift register shown in Fig. 1 c is example, the touch-control time period is inserted before supposing to start to export sweep signal to N+1 level shift register after N level shift register output sweep signal, within the touch-control time period, N+1, N+2, the input signal of the input signal end Input of the shift register of N+3 level is effective, the voltage of corresponding pull-up node PU is driven high, but due to the existence of leakage current, there is decay (Drop) in the voltage of pull-up node PU, cause after the touch-control time period terminates, N+1, N+2, the switching transistor M3 opening degree of the shift register of N+3 level is not enough, thus when clock signal terminal ck1 is high level, the sweep signal that output signal end Output exports is due to switch transistors M3 charging ability deficiency, the sweep signal rise time is caused to increase, and then cause N+1, N+2, the duration of charging of the capable pixel cell of N+3 shortens, the picture display effect of this three row pixel cell corresponding will be partially dark.
Utility model content
In view of this, the utility model embodiment provides a kind of driving circuit for touch-screen, In-cell touch panel and display device, cause N+1 level longer to the rise time of the sweep signal of N+n level shift register output in order to solve in prior art because N+1-n level to the sweep signal of N level shift register output decays within the touch-control time period, and then cause the duration of charging of the capable pixel cell of N+1, N+2, N+3 to shorten, the problem that corresponding picture display effect is partially dark.
Therefore, a kind of driving circuit for touch-screen that the utility model embodiment provides, comprise the gate driver circuit be made up of the M level shift register of cascade, the feed circuit of clock signal are provided for described shift register each in described gate driver circuit; In described gate driver circuit, except M+1-n level is to except M level shift register, the output signal end of shift register at different levels is connected with the input signal end of n-th grade of shift register thereafter respectively, and wherein n is greater than 0 and is less than the positive integer of M; Described driving circuit also comprises: time schedule controller; Wherein, described time schedule controller is used for:
In the touch-control time period, controlling described feed circuit to described shift register output amplitude at different levels is the clock signal of 0; Wherein, the described touch-control time period be N level shift register output sweep signal after and N+1 level shift register start to export sweep signal before preset time period, N is the positive integer being greater than n and being less than M;
In the display stage, control described feed circuit have the first amplitude to the shift register output of N level to N+1-n level clock signal in first time period, and control described feed circuit and to described shift register output at different levels, there is the clock signal of the second amplitude in the second time period; Wherein,
Described first time period is the time period of described N+1-n to the shift register output sweep signal of N level, and described second time period is the time period in described displaying time section except described first time period; First amplitude of described clock signal is greater than the second amplitude.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described time schedule controller, also for:
The output situation of shift register at different levels in described gate driver circuit is detected in displaying time section;
The progression determining the shift register exporting sweep signal is all first time period at N-1-n to the time period in the scope of N level, and the progression determining the shift register exporting sweep signal was not all the second time period at N-1-n to the time period in the scope of N level.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described sequential control implement body comprises: testing circuit, be connected to control circuit between described testing circuit and described feed circuit; Wherein,
Described testing circuit is used for: the output situation detecting shift register at different levels in described gate driver circuit in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and the first control signal is exported to described control circuit in described first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported the second control signal to described control circuit within described second time period;
Described control circuit is used for: when receiving the first control signal that described testing circuit sends, control described feed circuit have the first amplitude to clock signal from the shift register output of N level to N+1-n level; When receiving the second control signal that described testing circuit sends, control described feed circuit have clock signal from the second amplitude to described shift register output at different levels.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described sequential control implement body comprises: testing circuit, the second control circuit being connected to the first control circuit between described testing circuit and described feed circuit and being connected between described testing circuit and described feed circuit;
Described testing circuit is used for: the output situation detecting shift register at different levels in described gate driver circuit in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and control signal is exported to described first control circuit in described first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported control signal to described second control circuit within described second time period;
Described first control circuit is used for: when receiving the control signal that described testing circuit sends, control described feed circuit have the first amplitude to clock signal from the shift register output of N level to N+1-n level;
Described second control circuit is used for: when receiving the control signal that described testing circuit sends, control described feed circuit have clock signal from the second amplitude to described shift register output at different levels.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described feed circuit specifically comprise: with the power supply electronic circuit of described time schedule controller downlink connection, and be connected to the level conversion sub-circuit between described power supply electronic circuit and shift register at different levels; Wherein,
Described power supply electronic circuit is used for: in described first time period, under the control of described time schedule controller, exports the first high-potential voltage and low-potential voltage to described level conversion sub-circuit simultaneously; In described second time period, under the control of described time schedule controller, export the second high-potential voltage and low-potential voltage to described level conversion sub-circuit; Wherein said first high-potential voltage is higher than described second high-potential voltage;
Described level conversion sub-circuit is used for: when receiving the first high-potential voltage and low-potential voltage that described power supply electronic circuit provides, have the clock signal of the first amplitude to shift register output at different levels; When receiving the second high-potential voltage and low-potential voltage that described power supply electronic circuit provides, there is to shift register output at different levels the clock signal of the second amplitude.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described first amplitude equals the difference of described first high-potential voltage and described low-potential voltage, and described second amplitude equals the difference of described second high-potential voltage and described low-potential voltage.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, described time schedule controller is connected by I2C interface with described feed circuit.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, the described touch-control time period is longer, and the difference of described first amplitude and described second amplitude is larger.
Correspondingly, the utility model embodiment still provides a kind of In-cell touch panel, comprises any one driving circuit above-mentioned that the utility model embodiment provides.
Correspondingly, the utility model embodiment still provides a kind of display device, comprises the above-mentioned In-cell touch panel that the utility model embodiment provides.
The above-mentioned driving circuit for touch-screen, In-cell touch panel and display device that the utility model embodiment provides, control by time schedule controller feed circuit to have the first amplitude to the shift register output of N level to N+1-n level clock signal in the first time period in display stage, control second time period of feed circuit in the display stage has clock signal from the second amplitude to shift register output at different levels; To make N+1-n level high compared with the current potential of the sweep signal of other grade of shift register output to the current potential of the sweep signal of the n level shift register output of N level, even if thus can ensure that these sweep signals can decay within the touch-control time period, but the current potential after decay still can ensure that N+1 level can normally export to N+n level shift register, and then solve in prior art because decay within the touch-control time period N+1 that causes of sweep signal walks to duration of charging of the capable pixel cell of N+n shorter and problem that display effect that is that produce is partially dark.
Accompanying drawing explanation
Fig. 1 a is the structural representation of existing a kind of gate driver circuit;
Fig. 1 b is sequential chart corresponding to the gate driver circuit shown in Fig. 1 a;
Fig. 1 c is the structural representation of existing a kind of shift register;
The structural representation of the driving circuit for touch-screen that Fig. 2 provides for the utility model embodiment;
Fig. 3 a and Fig. 3 b is respectively the concrete structure schematic diagram of the driving circuit that the utility model embodiment provides.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of the driving circuit for touch-screen, In-cell touch panel and display device that the utility model embodiment provides is described in detail.
A kind of driving circuit for touch-screen that the utility model embodiment provides, as shown in Figure 2, comprise the gate driver circuit 3 (in Fig. 2 not shown M level shift register) be made up of the M level shift register of cascade, for providing the feed circuit 2 of clock signal to each shift register in gate driver circuit 3; Particularly, the cascade connection of gate driver circuit 3 as shown in Figure 1a (for n=3 in Fig. 1 a), except M+1-n level to M level shift register (SR (M+1-n) ..., SR (M)) outward, the output signal end Output_m of shift register SR (m) at different levels is connected with the input signal end Input of grade shift register SR (m+n) of n-th thereafter respectively, and wherein n is greater than 0 and is less than the positive integer of M; This driving circuit also comprises: time schedule controller 1; Wherein, time schedule controller 1 for:
In the touch-control time period, controlling feed circuit 2 is the clock signal of 0 to shift register output amplitude at different levels; Wherein, the touch-control time period be after N level shift register SR (N) exports sweep signal and N+1 level shift register start to export sweep signal before preset time period, N is the positive integer being greater than n and being less than M;
In the display stage, control feed circuit 2 have the first amplitude to the shift register output of N level to N+1-n level clock signal in first time period, and control feed circuit 2 has the clock signal of the second amplitude in the second time period to shift register output at different levels; Wherein,
First time period is the time period of N+1-n to the shift register output sweep signal of N level, and the second time period was the time period in displaying time section except first time period; First amplitude of clock signal is greater than the second amplitude.
The above-mentioned driving circuit that the utility model embodiment provides, control by time schedule controller feed circuit to have the first amplitude to the shift register output of N level to N+1-n level clock signal in the first time period in display stage, control second time period of feed circuit in the display stage has clock signal from the second amplitude to shift register output at different levels; To make N+1-n level high compared with the current potential of the sweep signal of other grade of shift register output to the current potential of the sweep signal of the n level shift register output of N level, even if thus can ensure that these sweep signals can decay within the touch-control time period, but the current potential after decay still can ensure that N+1 level can normally export to N+n level shift register, and then solve in prior art because decay within the touch-control time period N+1 that causes of sweep signal walks to duration of charging of the capable pixel cell of N+n shorter and problem that display effect that is that produce is partially dark.
It should be noted that, the above-mentioned driving circuit that the utility model embodiment provides, N can for being greater than n and being less than any one or more positive integers in M, when N only gets 1 positive integer, a touch-control time period is only inserted in the time period section meaning scanning one frame, when N gets multiple positive integer, in the time period meaning scanning one frame, insert multiple touch-control time period.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, the touch-control time period is longer, and the difference of the first amplitude and the second amplitude is larger.This is because the touch-control time period is longer, the degree that sweep signal decays after the touch-control time period is larger, therefore will ensure that the current potential of the sweep signal after decaying meets the requirement of node voltage, and the difference of the first amplitude and the second amplitude wants large.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, time schedule controller, also for:
The output situation of shift register at different levels in gate driver circuit is detected in displaying time section;
The progression determining the shift register exporting sweep signal is all first time period at N-1-n to the time period in the scope of N level, and the progression determining the shift register exporting sweep signal was not all the second time period at N-1-n to the time period in the scope of N level.
Below in conjunction with accompanying drawing, the embodiment of the driving circuit that the utility model embodiment provides is described in detail.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, as shown in Figure 3 a, time schedule controller 1 specifically comprises: testing circuit 11, be connected to control circuit 12 between testing circuit 11 and feed circuit 2; Wherein,
Testing circuit 11 is for the output situation that detects shift register at different levels in gate driver circuit 3 in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and the first control signal is exported to control circuit 12 in first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported the second control signal to control circuit 12 within the second time period;
Control circuit 12 for: when receiving the first control signal that testing circuit 11 sends, controlling feed circuit 2, to N+1-n level to the shift register output of N level, there is the clock signal of the first amplitude; When receiving the second control signal that testing circuit 11 sends, control feed circuit 2 have clock signal from the second amplitude to shift register output at different levels.
Or, preferably, in the above-mentioned driving circuit that the utility model embodiment provides, as shown in Figure 3 b, time schedule controller 1 specifically comprises: testing circuit 11, the second control circuit 14 being connected to the first control circuit 13 between testing circuit 11 and feed circuit 2 and being connected between testing circuit 11 and feed circuit 2; Wherein,
Testing circuit 11 is for the output situation that detects shift register at different levels in gate driver circuit 3 in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and control signal is exported to first control circuit 13 in first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported control signal to second control circuit 14 within the second time period;
First control circuit 13 for: when receiving the control signal that testing circuit 11 sends, controlling feed circuit 2, to N+1-n level to the shift register output of N level, there is the clock signal of the first amplitude;
Second control circuit 14 for: when receiving the control signal that testing circuit 11 sends, controlling feed circuit 2 and there is to shift register output at different levels the clock signal of the second amplitude.
In the above-mentioned time schedule controller that the utility model embodiment provides, testing circuit, control circuit, first control circuit or second control circuit all can be realized by the semiconductor circuit of entity.
Preferably, in the above-mentioned driving circuit that the utility model embodiment provides, as shown in Figure 3 a and Figure 3 b shows, feed circuit 2 specifically comprise: the power supply electronic circuit 21 be connected with time schedule controller 1, and are connected to the level conversion sub-circuit 22 between power supply electronic circuit 21 and shift register at different levels; Wherein,
Power supply electronic circuit 21 for: in first time period, under the control of time schedule controller 1, export the first high-potential voltage and low-potential voltage to level conversion sub-circuit 22 simultaneously; In the second time period, under the control of time schedule controller 1, export the second high-potential voltage and low-potential voltage to level conversion sub-circuit 22 simultaneously; Wherein the first high-potential voltage is higher than the second high-potential voltage;
Level conversion sub-circuit 22 for: when receiving the first high-potential voltage and low-potential voltage that power supply electronic circuit 21 provides, there is to shift register output at different levels the clock signal of the first amplitude; When receiving the second high-potential voltage and low-potential voltage that power supply electronic circuit 21 provides, there is to shift register output at different levels the clock signal of the second amplitude.
In the specific implementation, in the above-mentioned driving circuit that the utility model embodiment provides, the first amplitude equals the difference of the first high-potential voltage and low-potential voltage, and the second amplitude equals the difference of the second high-potential voltage and low-potential voltage.
In the specific implementation, in the above-mentioned driving circuit that the utility model embodiment provides, power supply electronic circuit is generally DC-DC converter, and certain power supply electronic circuit may also be the hardware that other can realize identical function, in this no limit.
In the specific implementation, in the above-mentioned driving circuit that the utility model embodiment provides, level conversion sub-circuit is generally level translator, and certain level conversion sub-circuit may also be the hardware that other can realize identical function, in this no limit.
Preferably, in the above-mentioned drive unit that the utility model embodiment provides, as shown in Figure 3 a and Figure 3 b shows, time schedule controller 1 is connected by I2C interface 4 with feed circuit 2.
Conceive based on same utility model, the utility model embodiment still provides a kind of In-cell touch panel, comprises any one driving circuit for touch-screen above-mentioned that the utility model embodiment provides.The principle of dealing with problems due to this In-cell touch panel is similar to aforementioned a kind of driving circuit, and therefore the enforcement of this In-cell touch panel see the enforcement of aforementioned driving circuit, can repeat part and repeat no more.
Conceive based on same utility model, the utility model embodiment still provides a kind of display device, comprises the above-mentioned In-cell touch panel that the utility model embodiment provides.This display device can be: any product or parts with Presentation Function such as mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.The enforcement of this display device see the embodiment of above-mentioned In-cell touch panel, can repeat part and repeats no more.
A kind of driving circuit for touch-screen, In-cell touch panel and display device that the utility model embodiment provides, control by time schedule controller feed circuit to have the first amplitude to the shift register output of N level to N+1-n level clock signal in the first time period in display stage, control second time period of feed circuit in the display stage has clock signal from the second amplitude to shift register output at different levels; To make N+1-n level high compared with the current potential of the sweep signal of other grade of shift register output to the current potential of the sweep signal of the n level shift register output of N level, even if thus can ensure that these sweep signals can decay within the touch-control time period, but the current potential after decay still can ensure that N+1 level can normally export to N+n level shift register, and then solve in prior art because decay within the touch-control time period N+1 that causes of sweep signal walks to duration of charging of the capable pixel cell of N+n shorter and problem that display effect that is that produce is partially dark.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (10)
1. for a driving circuit for touch-screen, comprise the gate driver circuit be made up of the M level shift register of cascade, the feed circuit of clock signal are provided for described shift register each in described gate driver circuit; In described gate driver circuit, except M+1-n level is to except M level shift register, the output signal end of shift register at different levels is connected with the input signal end of n-th grade of shift register thereafter respectively, and wherein n is greater than 0 and is less than the positive integer of M; It is characterized in that, described driving circuit also comprises: time schedule controller; Wherein, described time schedule controller is used for:
In the touch-control time period, controlling described feed circuit to described shift register output amplitude at different levels is the clock signal of 0; Wherein, the described touch-control time period be N level shift register output sweep signal after and N+1 level shift register start to export sweep signal before preset time period, N is the positive integer being greater than n and being less than M;
In the display stage, control described feed circuit have the first amplitude to the shift register output of N level to N+1-n level clock signal in first time period, and control described feed circuit and to described shift register output at different levels, there is the clock signal of the second amplitude in the second time period; Wherein,
Described first time period is the time period of described N+1-n to the shift register output sweep signal of N level, and described second time period is the time period in described displaying time section except described first time period; First amplitude of described clock signal is greater than the second amplitude.
2. driving circuit as claimed in claim 1, is characterized in that, described time schedule controller, also for:
The output situation of shift register at different levels in described gate driver circuit is detected in displaying time section;
The progression determining the shift register exporting sweep signal is all first time period at N-1-n to the time period in the scope of N level, and the progression determining the shift register exporting sweep signal was not all the second time period at N-1-n to the time period in the scope of N level.
3. driving circuit as claimed in claim 2, it is characterized in that, described sequential control implement body comprises: testing circuit, be connected to control circuit between described testing circuit and described feed circuit; Wherein,
Described testing circuit is used for: the output situation detecting shift register at different levels in described gate driver circuit in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and the first control signal is exported to described control circuit in described first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported the second control signal to described control circuit within described second time period;
Described control circuit is used for: when receiving the first control signal that described testing circuit sends, control described feed circuit have the first amplitude to clock signal from the shift register output of N level to N+1-n level; When receiving the second control signal that described testing circuit sends, control described feed circuit have clock signal from the second amplitude to described shift register output at different levels.
4. driving circuit as claimed in claim 2, it is characterized in that, described sequential control implement body comprises: testing circuit, the second control circuit being connected to the first control circuit between described testing circuit and described feed circuit and being connected between described testing circuit and described feed circuit; Wherein,
Described testing circuit is used for: the output situation detecting shift register at different levels in described gate driver circuit in the display stage, the time period of progression all in the scope of N-1-n to N of shift register cell determining the sweep signal exported is first time period, and control signal is exported to described first control circuit in described first time period, the time period of progression all not in the scope of N-1-n to N of shift register cell determining the sweep signal exported was the second time period, and exported control signal to described second control circuit within described second time period;
Described first control circuit is used for: when receiving the control signal that described testing circuit sends, control described feed circuit have the first amplitude to clock signal from the shift register output of N level to N+1-n level;
Described second control circuit is used for: when receiving the control signal that described testing circuit sends, control described feed circuit have clock signal from the second amplitude to described shift register output at different levels.
5. driving circuit as claimed in claim 1, it is characterized in that, described feed circuit specifically comprise: the power supply electronic circuit be connected with described time schedule controller, and are connected to the level conversion sub-circuit between described power supply electronic circuit and shift register at different levels; Wherein,
Described power supply electronic circuit is used for: in described first time period, under the control of described time schedule controller, exports the first high-potential voltage and low-potential voltage to described level conversion sub-circuit simultaneously; In described second time period, under the control of described time schedule controller, export the second high-potential voltage and low-potential voltage to described level conversion sub-circuit simultaneously; Wherein said first high-potential voltage is higher than described second high-potential voltage;
Described level conversion sub-circuit is used for: when receiving the first high-potential voltage and low-potential voltage that described power supply electronic circuit provides, have the clock signal of the first amplitude to shift register output at different levels; When receiving the second high-potential voltage and low-potential voltage that described power supply electronic circuit provides, there is to shift register output at different levels the clock signal of the second amplitude.
6. driving circuit as claimed in claim 5, it is characterized in that, described first amplitude equals the difference of described first high-potential voltage and described low-potential voltage, and described second amplitude equals the difference of described second high-potential voltage and described low-potential voltage.
7. driving circuit as claimed in claim 5, it is characterized in that, described time schedule controller is connected by I2C interface with described feed circuit.
8. the driving circuit as described in any one of claim 1-4, is characterized in that, the described touch-control time period is longer, and the difference of described first amplitude and described second amplitude is larger.
9. an In-cell touch panel, is characterized in that comprising the driving circuit as described in any one of claim 1-8.
10. a display device, is characterized in that, comprises In-cell touch panel as claimed in claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139798A (en) * | 2015-10-20 | 2015-12-09 | 京东方科技集团股份有限公司 | Driving circuit for touch screen, embedded touch screen and display device |
| JP2020531877A (en) * | 2017-08-16 | 2020-11-05 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, shift register unit drive method, gate driver on array and display device |
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2015
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139798A (en) * | 2015-10-20 | 2015-12-09 | 京东方科技集团股份有限公司 | Driving circuit for touch screen, embedded touch screen and display device |
| WO2017067407A1 (en) * | 2015-10-20 | 2017-04-27 | 京东方科技集团股份有限公司 | Touch screen driver circuit , embedded touch screen and display device |
| US9953555B2 (en) | 2015-10-20 | 2018-04-24 | Boe Technology Group Co., Ltd. | Driving circuit for touch screen, in-cell touch screen and display apparatus |
| JP2020531877A (en) * | 2017-08-16 | 2020-11-05 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, shift register unit drive method, gate driver on array and display device |
| JP7040732B2 (en) | 2017-08-16 | 2022-03-23 | 京東方科技集團股▲ふん▼有限公司 | Shift register unit, shift register unit drive method, gate driver on array and display device |
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