CN102193888A - Data transmission system and programmable serial peripheral interface controller - Google Patents
Data transmission system and programmable serial peripheral interface controller Download PDFInfo
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- CN102193888A CN102193888A CN201010132312XA CN201010132312A CN102193888A CN 102193888 A CN102193888 A CN 102193888A CN 201010132312X A CN201010132312X A CN 201010132312XA CN 201010132312 A CN201010132312 A CN 201010132312A CN 102193888 A CN102193888 A CN 102193888A
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Abstract
The embodiment of the invention provides a data transmission system and a programmable serial peripheral interface controller. The data transmission system comprises a serial peripheral interface and a programmable controller. The serial peripheral interface is coupled between a first device and at least one second device. The programmable controller is used for controlling the serial peripheral interface to be switched between a single-port data transmission mode and a multi-port data transmission mode, wherein when more than one second device is coupled to the serial peripheral interface, the serial peripheral interface is switched to the multi-port data transmission mode and used for controlling multi-port data transmission between the first device and the second device, the first device simultaneously transmits data to each second device through a first transmission bus end of the serial peripheral interface, and the first device simultaneously receives data from each second device through a second transmission bus end of the serial peripheral interface.
Description
Technical field
The present invention is about a kind of data transmission system, especially in regard to a kind of data transmission system that programmable Multi-ported Data transmission is provided by Serial Peripheral Interface (Serial Peripheral Interface is called for short SPI).
Background technology
Serial Peripheral Interface (Serial Peripheral Interface, be called for short SPI) is a kind of 4 line locking sequence data transportation protocols, and its framework be from/main structure, is present a kind of element and interelement connecting interface of being widely used in.
Yet, because the restriction of framework makes that present Serial Peripheral Interface is limited to single main device and from installing the application of data transmission (single port data transmission), promptly single master goes out from going into (MOSI), leading from going out (MISO) data transmission.For day by day novel system applies, especially calculate simultaneously and the system of immediate reaction data content at needs, only provide the element of the Serial Peripheral Interface of single port data transmission all can't satisfy the system requirements of this respect at present.
Therefore, the Serial Peripheral Interface that needs a kind of improvement, it can utilize existing hardware structure that the data transmission of multiport (multi port) is provided, and can have more programmable characteristic, in order to flexibly to switch on the data transmission of single port and multiport, make under fixing hardware structure, can satisfy different system requirements.
Summary of the invention
The Serial Peripheral Interface that the present invention provides in a plurality of embodiment utilize existing hardware structure that the Multi-ported Data transmission is provided, and the Serial Peripheral Interface of Improvement type can further switch on the data-transmission mode of single port and multiport.
According to one embodiment of the invention, a kind of data transmission system comprises Serial Peripheral Interface and Programmable Logic Controller.Serial Peripheral Interface is coupled between first device and at least one second device, comprise in order to the transmission clock signal in first the device at least one therewith second the device between sequence clock pulse end, in order to the transmission chip select signal in first the device at least one therewith second the device between, by this chip selecting side of the transmission of log-on data, in order to the transmission data from first the device so far at least one second the device one first transfer bus end and in order to the transmission data at least one since then second the device so far first the device one second transfer bus end.Programmable Logic Controller switches on single port data transmission mode and Multi-ported Data transmission mode in order to the control Serial Peripheral Interface, wherein when being coupled to Serial Peripheral Interface more than one second device, Serial Peripheral Interface switches to the Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and these second devices, this moment first, device transferred data to each second device simultaneously by the first transfer bus end, and first device receives data from each second device simultaneously by the second transfer bus end.
According to another embodiment of the present invention, a kind of data transmission system comprises a serial peripheral interface and a Programmable Logic Controller.Serial Peripheral Interface is coupled to one first device, comprise in order to transmit a clock pulse signal to a sequence clock pulse end of at least one second device, in order to transmit a chip select signal, by this chip selecting side of the transmission of log-on data, in order to transmit data to the first transfer bus end of at least one second device and in order to receive the second transfer bus end of the data that this at least one second device transmits.Programmable Logic Controller switches on single port data transmission mode and Multi-ported Data transmission mode in order to control this Serial Peripheral Interface, wherein when being coupled to Serial Peripheral Interface more than one second device, Serial Peripheral Interface switches to the Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and described these second devices, this moment first, device transferred data to each second device simultaneously by the first transfer bus end, and first device receives data from each second device simultaneously by the second transfer bus end.
According to another embodiment of the present invention, propose a kind of Serial Peripheral Interface controller able to programme, in order to control the data-transmission mode of a serial peripheral interface, comprise a data transmission selector switch, in order to carry out data allocations according to the port number controlled variable.Wherein the port number controlled variable is represented the number that carries out at least one second device of data transmission simultaneously with one first device, this data-transmission mode is changeable in a single port data transmission mode and a Multi-ported Data transmission mode, this first device transmits data bit with at least one second device by this Serial Peripheral Interface, when being coupled to Serial Peripheral Interface more than one second device, Serial Peripheral Interface is switched to this Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and these second devices, this moment first, device transferred data to each second device simultaneously by the first transfer bus end, and first device receives data from each second device simultaneously by the second transfer bus end.
The Serial Peripheral Interface that the embodiment of the invention provides, it can utilize existing hardware structure that the data transmission of multiport (multi port) is provided, and can have more programmable characteristic, in order to flexibly to switch on the data transmission of single port and multiport, make under fixing hardware structure, can satisfy different system requirements.In addition, the data transmission system framework that the embodiment of the invention proposed can be reached and utilize Serial Peripheral Interface (SPI) to carry out the purpose that reads or write of long numeric data simultaneously, improves the using value of Serial Peripheral Interface (SPI) by this.
Description of drawings
Fig. 1 shows according to the described data transmission system of one embodiment of the invention;
Fig. 2 shows according to the described Programmable Logic Controller calcspar of one embodiment of the invention;
Fig. 3 shows according to the described data transmission flow process figure in data transmission system of one embodiment of the invention;
Fig. 4 A and Fig. 4 B show according to the signal waveforms in the described data transmission system of one embodiment of the invention;
Fig. 5 shows a described according to another embodiment of the present invention data transmission system.
Drawing reference numeral
100,500～data transmission system;
101,102-0,102-n, 501-0,501-1,502-0,502-1,502-2,502-3,502-4,502-5,502-6,502-7～data transmission device;
103,503-0,503-1～Serial Peripheral Interface;
104,200～Programmable Logic Controller;
105,105-0,105-1,105-2,105-3,106,106-0,106-1,106-2,106-3～shift register;
201～data transmission selector switch;
202～transmission digit counter;
203～logic comparator;
204～package comparer;
205～port number controlled variable;
206～transmission position parameter;
207～transmission package parameter;
DI[0], DI[1], DI[2], DI[3], DI[n], DO[0], DO[1], DO[2], DO[3], DO[n], SPI_DI[n:0], SPI_DI1[3:0], SPI_DI2[3:0], SPI_DO[n:0], SPI_DO1[3:0], SPI_DO2[3:0]～data bit;
MOSI, MISO～transfer bus end;
MOSI[n:0], MISO[n:0]～transfer bus;
SCLK～sequence clock pulse end;
SS～chip selecting side;
SPI_SCLK～clock signal;
SPI_SS, SPI_SS1, SPI_SS2～chip select signal.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a plurality of embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Fig. 1 shows according to the described data transmission system 100 of one embodiment of the invention, comprises a plurality of data transmission devices 101 and 102-0～102-n and is coupled to a serial peripheral interface 103 between the data transmission device.Wherein data transmission device can comprise a main device (for example, 101) and at least one from device (for example, 102-0～102-n, n are positive integer).Serial Peripheral Interface 103 comprises sequence clock pulse end SCLK, chip selecting side SS and the transfer bus end MOSI (master goes out from going into) and MISO (master goes into from going out) that is coupled between the data transmission device.Main device 101 transmits a clock pulse signal SPI_SCLK extremely from device 102-0～102-n by sequence clock pulse end SCLK, in order to provide clock signal extremely from device, and transmit a chip select signal SPI_SS to from device 102-0～102-n by chip selecting side SS, carry out data transmission from device in order to start by chip select signal.
According to one embodiment of the invention, transfer bus MOSI[n:0] in order to provide autonomous device to single position or bits of data transmission from device, data bit SPI_DO[n:0 as shown in the figure], and transfer bus MISO[n:0] in order to data bit SPI_DI[n:0 as shown in the figure to be provided since single position or the bits of data transmission of device to main device].In embodiments of the invention, clock signal SPI_SCLK and chip select signal SPI_SS are common to a plurality of between the device, so when a plurality of when device is selected, respectively can carry out two-way data transmission with main device simultaneously from device, that is, a plurality of data bit can be transmitted in parallel and two-wayly main device and from the device between.
According to one embodiment of the invention, data transmission system 100 can also comprise a Programmable Logic Controller (Serial Peripheral Interface controller able to programme), data-transmission mode in order to Serial Peripheral Interface 103 in the control data transmission system 100, wherein Programmable Logic Controller can be disposed at separately in the data transmission system, perhaps flexibly be integrated in main device 101 (Programmable Logic Controller 104 as shown in Figure 1), at least one in device or Serial Peripheral Interface 103, therefore hardware configuration of the present invention is not limited to the category shown in first figure.According to one embodiment of the invention, Programmable Logic Controller can switch on a single port (single port) transmission mode and a multiport (multi port) data-transmission mode according to system requirements, wherein when more than one when device is coupled to Serial Peripheral Interface 103, Programmable Logic Controller can switch to the Multi-ported Data transmission mode in response to system requirements, in order to control main device and to transmit from carrying out Multi-ported Data between the device, as above-mentioned, this moment data bit can be transmitted in parallel and two-wayly main device with from (following will do more detailed introduction) between installing at single port data transmission mode and Multi-ported Data transmission mode.
Fig. 2 shows according to the described Programmable Logic Controller calcspar of one embodiment of the invention.As above-mentioned, Programmable Logic Controller can be disposed at data transmission system separately, perhaps flexibly is integrated in main device, at least one in device or Serial Peripheral Interface, and therefore enforcement of the present invention is not limited to any hardware configuration.As shown in Figure 2, Programmable Logic Controller 200 can comprise data transmission selector switch 201, transmission digit counter 202, logic comparator 203 and package comparer 204.Data transmission selector switch 201 is in order to carry out data allocations according to a port number controlled variable 205.Port number controlled variable 205 can be carried out the number from device of data transmission simultaneously in order in the setting data transmission system with main device.For example, when data transmission system can provide 4 at most when device simultaneously carries out data transmission with main device, port number controlled variable 205 can be set at 1～4, wherein when port number controlled variable 205 is set at 1, the representative data transmission system is single port data transmission mode at present, therefore the same time only one carry out data transmission from device and main device, on the other hand, when port number controlled variable 205 is set at 4, therefore the representative data transmission system is the Multi-ported Data transmission mode at present, and the same time can have 4 to carry out data transmission with main device simultaneously from device.
Fig. 2 demonstrates one 4 port data transmission mode examples, under this pattern, port number controlled variable 205 is set to 4, therefore can support 4 at most and carry out data transmission simultaneously from device and 1 main device, transfer bus MOSI[3:0 wherein], MISO[3:0] each transmission line be respectively coupled to main device as shown in Figure 1 and respectively between the device, in order to transmit everybody (DO[0 as shown in Figure 1]～DO[n] and DI[0]～DI[n]) self-corresponding to each from device.According to one embodiment of the invention, main device can comprise multi-level input shift register 105 and multi-level Output Shift Register 106 (as shown in Figure 1), be received from respectively data bit in order to deposit respectively, and the respectively data bit from installing is delivered in tendency to develop from installing.More particularly, 4 port data transmission mode examples as shown in Figure 2, main device can comprise a plurality of input shift register 105-0～105-3 and Output Shift Register 106-0～106-3, each input shift register is self-corresponding from installing (from one of device 102-0～102-n in order to store respectively, n=3 in this example wherein) data bit that receives, and each Output Shift Register is delivered to the corresponding data bit from device in order to store tendency to develop respectively.
In the process of the data transmission of Multi-ported Data transmission mode, but 201 parallel processing of data transmission selector switch from respectively from the device data bit, in order to being distributed, described these data bit are stored in corresponding input shift register 105-0～105-3, and parallel processing is from each Output Shift Register 106-0～106-3 position, and is corresponding to device in order to described these data bit are exported to.Therefore, input shift register 105-0～105-3 can be self-corresponding respectively from installing parallel reception data (promptly, while receives data from each correspondence from device), and Output Shift Register 106-0～106-3 can parallel output data to respectively from device (that is, simultaneously output data to each correspondence from device).Thus, main device can transfer data to each from device simultaneously by transfer bus end MOSI, and receives data from each from device simultaneously by transfer bus end MISO.
Fig. 3 shows according to the described data transmission flow process figure in data transmission system of one embodiment of the invention.When the transmission beginning (step S301), Programmable Logic Controller judges according to system requirements whether the needs Multi-ported Data is transmitted (step S302) at present.If not, Programmable Logic Controller is set corresponding systematic parameter (for example, port number controlled variable 205, transmission position parameter 206 and transmission package parameter 207 etc.) (step S303), and then begins to carry out single port data transmission and reception (step S304).On the other hand, if Programmable Logic Controller is set corresponding systematic parameter (step S305), and then begin to carry out the Multi-ported Data transmission and receive (step S306).Then, whether the transmission of Programmable Logic Controller judgment data finishes (step S307), and as above-mentioned, Programmable Logic Controller judges whether also have package to need to transmit in this transmission, if not having package need be transmitted, then to represent this transmission to finish.If also have package to be transmitted, the representative transmission does not finish as yet, and Programmable Logic Controller can further be set corresponding systematic parameter (step S305) according to system requirements, and continues the Multi-ported Data transmission and receive (step S306).
Fig. 4 A and Fig. 4 B show according to the signal waveforms in the described data transmission system of one embodiment of the invention, are a pair of port data transmission mode example at this.According to one embodiment of the invention, chip select signal SPI_SS can be designed to the control signal with low state action (active low), therefore when chip select signal SPI_SS transfers low level to by high levels, main device and from the device between data transmission start, and in the cycle until chip select signal SPI_SS is pulled high levels, may be defined as a transmission cycle.Therefore, Fig. 4 A and Fig. 4 B show the signal waveforms in the transmission cycle, and wherein the difference of Fig. 4 A and Fig. 4 B only is, Fig. 4 A can express the data bit content change, and Fig. 4 B can express the transmission sequence of data bit.
Shown in Fig. 4 A, transfer bus MISO[0] and MISO[1] and MOSI[0] and MOSI[1] can carry out the transmission of bit data simultaneously, therefore the same time can receive and transmit 2 data simultaneously for main device.Fig. 4 B clearly shows the transmission sequence of data bit, wherein respectively import data bit DI and outputs data bits DO respectively with two numerical codings, DI nm as shown in the figure and DO nm (n=0～1, m=0～f), wherein the first yardage word n represents the bit data of n transfer bus, it is m position that second yard m represents what transmitted on this transfer bus, so DI 0f represents the 16th position of being transmitted on the 0th transfer bus.As shown in the figure, data bit is transmitted on transfer bus in regular turn, and be stored to corresponding shift register (or in regular turn be transferred into corresponding transfer bus from shift register), therefore in embodiments of the invention, processor in the data transmission system (figure does not show) can directly take out data (or transmitting data to corresponding shift register) from shift register, and does not need to carry out extra bit data reorganization.
As above-mentioned, Programmable Logic Controller is in order to the data-transmission mode of control system, wherein according to one embodiment of the invention, under single port data transmission mode and Multi-ported Data transmission mode, systematic parameter all can flexibly be set, make data transmission system under fixing hardware structure, the demand that also can reach different application (for example, many package transmission of multidigit or the many package transmission of unit etc.), below will set and do more detailed description at the systematic parameter of single port data transmission mode and Multi-ported Data transmission mode.
Suppose as shown in Figure 2, data transmission system can support at most 4 from the device with 1 main device carry out data transmission simultaneously, therefore the same time can have 4 data to be transfused to simultaneously and output at most, so under the Multi-ported Data transmission mode, port number controlled variable 205 can be set to 2,3 or 4.When port number controlled variable 205 is set to 4, main device can be simultaneously be coupled to 4 of Serial Peripheral Interface and carry out two-way data transmission from device.When port number controlled variable 205 is set to 2 or 3, main device can be simultaneously be coupled to 2 or 3 of Serial Peripheral Interface and carry out two-way data transmission from device.According to one embodiment of the invention, do not couple from the transfer bus end pin position MOSI and the MISO of device this moment can be universal input and output (General Purpose InputOutput by default, be called for short GPIO) use of pin position, therefore would not cause the waste of pin position.
And under single port data transmission mode, port number controlled variable 205 is set 1, main device be coupled to 1 of Serial Peripheral Interface and carry out two-way data transmission from device.This moment is in order to increase the utilization rate of multi-level input and Output Shift Register, data transmission selector switch 201 can be orderly sent to each input shift register with the data bit from device input by correspondence, and the data bit that will be stored in each Output Shift Register is orderly sent to corresponding to device.In particular, with reference to figure 2, under single port data transmission mode, port number controlled variable 205 is set 1, transmit package parameter 207 and can be set at 1～4 this moment, and when transmission package parameter 207 was set at 4, representing had 4 packages to be transmitted in the transmission cycle.Therefore, in transmission cycle, data transmission selector switch 201 can be orderly sent to the data bit from each package of device input by correspondence in input shift register 105-0,105-1,105-2 and the 105-3, and will be stored in each interior packet data position of each Output Shift Register 106-0,106-1,106-2 and 106-3 and be orderly sent to corresponding to installing.The shift register degree of depth of supposing the system is 16, therefore in a transmission cycle, the data of 16 * 4=64 position can be arranged by transmitted in both directions at most.Identical notion also can be applicable under the Multi-ported Data transmission mode, the setting value of port number controlled variable 205 less than can be simultaneously with main device carry out data transmission under the situation of a maximum quantity of device (for example this example, port number controlled variable 205 is set to 2 or 3).Thus, even system is not applied to the transmission mode of maximum port number, no matter be that transfer bus end pin position MOSI and MISO or I/O shift register all can effectively be used, can not cause waste.
Fig. 5 shows a described according to another embodiment of the present invention data transmission system 500.Data transmission system 500 comprises a plurality of data transmission device 501-0～501-1 and 502-0～502-7 and is coupled to Serial Peripheral Interface 503-0 and 503-1 between the data transmission device, wherein data transmission device 501-0 and 501-1 are main device, and 502-0～502-7 is from device.In this embodiment, clock signal SPI_SCLK is common between the data transmission device, main device 501-0 selects first group from device 502-0～502-3 by chip select signal SPI_SS1, and main device 501-1 selects second group from device 502-4～502-7 by chip select signal SPI_SS2.Main device 501-0 transmits data bit SPI_DO1[3:0 by transfer bus] to from device 502-0～502-3, wherein each data bit DO[0], DO[1], DO[2] with DO[3] be transferred in regular turn corresponding to installing 502-0～502-3.Main device 501-0 also by transfer bus since device 502-0～502-3 data with clock information SPI_DI1[3:0], each data bit DI[0 wherein], DI[1], DI[2] and DI[3] self-correspondingly in regular turn be transferred into main device 501-0 from device 502-0～502-3.Similarly, main device 501-1 transmits data bit SPI_DO2[3:0 by transfer bus] to from device 502-4～502-7, wherein each data bit DO[0], DO[1], DO[2] with DO[3] be transferred in regular turn corresponding to installing 502-4～502-7.Main device 501-1 also by transfer bus since device 502-4～502-7 data with clock information SPI_DI2[3:0], each data bit DI[0 wherein], DI[1], DI[2] and DI[3] self-correspondingly in regular turn be transferred into main device 501-1 from device 502-4～502-7.
The data transfer mode that is applied to data transmission system 500 can repeat no more in this with reference to figure 1 and relevant paragraph.By finding out among Fig. 1, Fig. 2, Fig. 5, each element and data transmission device in the data transmission system can flexibly be configured, wherein the transmission figure place that can support at most of data transmission system also can flexibly be designed according to different application demands, therefore above-described embodiment in order to clear elaboration notion of the present invention, is not in order to limit scope of the present invention only.In addition, according to data transmission system framework proposed by the invention, the data-transformation facility that not only can keep the Serial Peripheral Interface (SPI) of original four-wire system, more can by the setting of systematic parameter (for example port number controlled variable 205, transmission position parameter 206 and transmission package parameter 207 etc.) will import and the output data proper placement to each multi-level shift LD, utilize Serial Peripheral Interface (SPI) to carry out the purpose that reads or write of long numeric data simultaneously to reach, improve the using value of Serial Peripheral Interface (SPI) by this.
Though the present invention discloses as above with embodiment; right its is not in order to limiting scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claim institute confining spectrum.
Claims (11)
1. a data transmission system is characterized in that, described data transmission system comprises:
One serial peripheral interface is coupled between one first device and at least one second device, comprising:
One sequence clock pulse end is in order to transmit a clock pulse signal between described first device and described at least one second device;
One chip selecting side is in order to transmit a chip select signal between described first device and described at least one second device, the transmission of log-on data by this;
One first transfer bus end installs from described first device extremely described at least one second in order to the transmission data; And
One second transfer bus end installs from described at least one second device extremely described first in order to the transmission data; And
One Programmable Logic Controller switches on a single port data transmission mode and a Multi-ported Data transmission mode in order to control described Serial Peripheral Interface;
Wherein when being coupled to described Serial Peripheral Interface more than described second device, described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between described first device and described second device, this moment, described first device transferred data to each described second device simultaneously by the described first transfer bus end, and described first device receives data from each described second device simultaneously by the described second transfer bus end.
2. data transmission system as claimed in claim 1 is characterized in that, described Programmable Logic Controller is integrated in described first device, at least one described second device or the described Serial Peripheral Interface.
3. data transmission system as claimed in claim 2, it is characterized in that, described data transmission system also comprises a plurality of input shift registers and a plurality of Output Shift Register, be arranged in described first device, when described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, described input shift register is respectively from the parallel reception data of described second device, and the parallel output data of described Output Shift Register difference is to described second device.
4. data transmission system as claimed in claim 3 is characterized in that, described Programmable Logic Controller comprises:
One data transmission selector switch, in order to carry out data allocations according to a port number controlled variable, wherein said port number controlled variable is represented the number that carries out described at least one second device of data transmission simultaneously with described first device.
5. data transmission system as claimed in claim 4 is characterized in that, described Programmable Logic Controller also comprises:
One transmission digit counter is in order to be accumulated at a data bits that has been transmitted in the transmission cycle, to obtain a count results;
One logic comparator, in order to a described count results and a transmission position parameter are compared, obtaining a bit comparison result, wherein said transmission position parameter depend on each input shift register with and/or the degree of depth of each Output Shift Register; And
One package comparer, in order to a described bit comparison result and a transmission package parameter are compared, to obtain a package comparative result, the package sum that wherein said transmission package parameter representative is transmitted in described transmission cycle domestic demand, and the position sum that each package comprised is according to the parameter decision of described transmission position.
6. a data transmission system is characterized in that, described data transmission system comprises:
One serial peripheral interface is coupled to one first device, comprising:
One sequence clock pulse end is in order to transmit a clock pulse signal at least one second device;
One chip selecting side is in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end is in order to transmit data to described at least one second device; And
One second transfer bus end is in order to receive the data that described at least one second device transmits; And
One Programmable Logic Controller switches on a single port data transmission mode and a Multi-ported Data transmission mode in order to control described Serial Peripheral Interface;
Wherein when being coupled to described Serial Peripheral Interface more than described second device, described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between described first device and described second device, this moment, described first device transferred data to each described second device simultaneously by the described first transfer bus end, and described first device receives data from each described second device simultaneously by the described second transfer bus end.
7. a Serial Peripheral Interface controller able to programme in order to control a data-transmission mode of a serial peripheral interface, is characterized in that, described Serial Peripheral Interface controller able to programme comprises:
One data transmission selector switch is in order to carry out data allocations according to a port number controlled variable;
Wherein said port number controlled variable is represented the number that carries out at least one second device of data transmission simultaneously with one first device, described data-transmission mode switches on a single port data transmission mode and a Multi-ported Data transmission mode, described first device transmits data bit with described at least one second device by described Serial Peripheral Interface, when being coupled to described Serial Peripheral Interface more than described second device, described Serial Peripheral Interface is switched to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between described first device and described second device, this moment, described first device transferred data to each described second device simultaneously by one first transfer bus end, and described first device receives data from each described second device simultaneously by one second transfer bus end.
8. Serial Peripheral Interface controller able to programme as claimed in claim 7, it is characterized in that, when described Multi-ported Data transmission mode, a plurality of input shift registers that described data transmission selector switch is controlled described first device with respectively from the parallel reception data of each described second device, and a plurality of Output Shift Registers of controlling described first device with parallel output data respectively to each described second device.
9. Serial Peripheral Interface controller able to programme as claimed in claim 8 is characterized in that, described Serial Peripheral Interface controller able to programme also comprises:
One transmission digit counter is in order to be accumulated at a data bits that has been transmitted in the transmission cycle, to obtain a count results; And
One logic comparator, in order to a described count results and a transmission position parameter are compared, obtaining a bit comparison result, wherein said transmission position parameter depend on each input shift register with and/or the degree of depth of each Output Shift Register.
10. Serial Peripheral Interface controller able to programme as claimed in claim 8, it is characterized in that, when a setting value of described port number controlled variable equals can be simultaneously to carry out a maximum quantity that described at least one second of data transmission installs with described first device, described data transmission selector switch will be sent to each corresponding described input shift register respectively by the described data bit of the parallel input of described second device, and will be stored in parallel one second device that is sent to correspondence of described data bit of described Output Shift Register respectively.
11. Serial Peripheral Interface controller able to programme as claimed in claim 8, it is characterized in that, when a setting value of described port number controlled variable when can be simultaneously carrying out a maximum quantity that described at least one second of data transmission installs with described first device, described data transmission selector switch will be orderly sent to described input shift register by the described data bit of the described second device input of correspondence, and the described data bit that will be stored in described Output Shift Register is orderly sent to corresponding described second device.
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| CN102693200A (en) * | 2012-01-12 | 2012-09-26 | 河南科技大学 | SPI (serial peripheral interface) communication port based on CPLD (complex programmable logic device) |
| CN104077080A (en) * | 2013-03-29 | 2014-10-01 | 联发科技股份有限公司 | Memory access method, memory access control method, SPI flash memory device and controller thereof |
| CN104238957A (en) * | 2013-06-13 | 2014-12-24 | 联发科技股份有限公司 | Serial peripheral interface controller, serial peripheral interface flash memory, access method and access control method |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN106802871A (en) * | 2015-11-26 | 2017-06-06 | 新唐科技股份有限公司 | Bus system |
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| CN102693200A (en) * | 2012-01-12 | 2012-09-26 | 河南科技大学 | SPI (serial peripheral interface) communication port based on CPLD (complex programmable logic device) |
| CN104077080A (en) * | 2013-03-29 | 2014-10-01 | 联发科技股份有限公司 | Memory access method, memory access control method, SPI flash memory device and controller thereof |
| CN104238957A (en) * | 2013-06-13 | 2014-12-24 | 联发科技股份有限公司 | Serial peripheral interface controller, serial peripheral interface flash memory, access method and access control method |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN104503934B (en) * | 2014-12-02 | 2017-10-24 | 天津国芯科技有限公司 | A kind of expansible serial transmission device |
| CN106802871A (en) * | 2015-11-26 | 2017-06-06 | 新唐科技股份有限公司 | Bus system |
| CN107219822A (en) * | 2016-03-22 | 2017-09-29 | 发那科株式会社 | Serial communication branch equipment and serial communication system |
| CN107219822B (en) * | 2016-03-22 | 2019-09-17 | 发那科株式会社 | Serial communication branch equipment and serial communication system |
| CN112506839A (en) * | 2020-12-07 | 2021-03-16 | 天津津航计算技术研究所 | One-to-many SPI bus switching method and device |
| CN112506839B (en) * | 2020-12-07 | 2023-02-03 | 天津津航计算技术研究所 | One-to-many SPI bus switching method and device |
| CN115037411A (en) * | 2021-03-05 | 2022-09-09 | 信骅科技股份有限公司 | Signal receiving and transmitting system and signal receiver thereof |
| CN115037411B (en) * | 2021-03-05 | 2024-03-19 | 信骅科技股份有限公司 | Signal receiving and transmitting system and signal receiver thereof |
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