CN115037411B - Signal receiving and transmitting system and signal receiver thereof - Google Patents

Signal receiving and transmitting system and signal receiver thereof Download PDF

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Publication number
CN115037411B
CN115037411B CN202111481191.4A CN202111481191A CN115037411B CN 115037411 B CN115037411 B CN 115037411B CN 202111481191 A CN202111481191 A CN 202111481191A CN 115037411 B CN115037411 B CN 115037411B
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data
signal
bit
index value
output interface
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CN115037411A (en
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林鸿明
毛志强
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Xinhua Technology Co ltd
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Xinhua Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

The invention provides an adaptive serial general purpose input output (Adaptive serial general purpose input output, ASGPIO) interface and a signal receiver thereof, which are applicable to a security control module (Secure Control Module, SCM). The adaptive serial universal input output interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transfer data and provides previous transfer data. The comparator receives the current transmission data and receives the previous transmission data. In the first mode, the comparator compares the previous transmission data with the current transmission data to generate data difference information. The encoder generates at least one index value and a corresponding indication signal according to the data difference information in the first mode. The signal transmitter transmits at least one index value and an indication signal which are serial signals to a signal receiver.

Description

Signal receiving and transmitting system and signal receiver thereof
Technical Field
The present invention relates to an adaptive serial universal input/output interface and a signal receiver thereof, and more particularly, to an adaptive serial universal input/output interface and a signal receiver thereof capable of reducing transmission delay.
Background
In the present technical field, a general purpose input output (General Purpose Input Output, GPIO) interface is a common Input Output (IO) port, and is widely used in remote platform control management architecture, and is often used in a security control module (Secure Control Module, SCM). For example, in battery management chips (Battery Management Integrated Circuit, BMICs), the general purpose input/output interface is mainly used to transmit relevant information about voltage/temperature and fan monitoring. In design, to reduce the number of pins (pins) required for a universal input output interface, a serial universal input output interface (Serial General Purpose Input Output, SGPIO) is often used.
The following can refer to the system architecture diagram of the security control module (DC-SCM) of the data center of various common general knowledge shown in fig. 1A to 1E. In FIG. 1A, a security control system of a data center may have a baseboard management controller (Baseboard Management Controller, BMC) 111 and a data center security control interface (Datacenter-ready Secure Control Interface, DC-SCI) 112. The baseboard management controller 111 can communicate with the data center security control interface 112 through a variety of interfaces. Wherein, the baseboard management controller 111 and the data center security control interface 112 can communicate with each other through the general purpose input/output interface by using a programmable logic device (Programmable Logical Device, PLD) 113. The data center security control interface 112 may receive and transmit serial general input/output signals SGPIO0 and SGPIO1, and the baseboard management controller 111 may receive and transmit parallel general input/output signals through the general input/output signal pin GPIOs. The programmable logic device 113 is used to perform signal conversion operation between the serial general input/output signals SGPIO0, SGPIO1 and parallel general input/output signals.
In the security control system of the data center in fig. 1B, the main board 121 and the security control module 123 are connected through the data center security control interface 122. Wherein the motherboard 121 carries a central processor 1211 and a bridge 1212. The security control module 123 has a baseboard management controller 1231 thereon. The bridge 1212 and baseboard management controller 1231 can communicate via general purpose input/output signals, and the data center security control interface 122 can mediate the conversion of general purpose input/output signals between serial and parallel formats.
In the security control system of the data center in fig. 1C, the main board 131 and the security control module 1331 are connected through the data center security control interface 132. The security control module 1331 is disposed on a circuit board 133, and the circuit board 133 carries a baseboard management controller 1332. The motherboard 131 has a main processor module (Host Processor Module, HPM) 1312 and a cpu 1311 thereon. The main processor module 1312 is configured to receive and send a serial general input/output signal SGPIO and communicate with the security control module 1331 via the data center security control interface 132.
In the data center security control system of fig. 1D, the host processor module 1412 and the baseboard management controller 1431 are connected through the data center security control interface 142. The baseboard management controller 1431 and the peripheral extender 1432 are disposed together on a circuit board 143. The main processor module 1412 and the cpu 1411 are disposed on the motherboard 141. The main processor 1412 is configured to receive and send a serial general input/output signal SGPIO and communicate with the baseboard management controller 1431 through the data center security control interface 142. In addition, the baseboard management controller 1431 and the peripheral expander 1432 can also communicate via a serial general input/output signal SGPIO.
In the security control system of the data center in fig. 1E, the cpu 1511, the baseboard management controller 1512, and the peripheral expander 1513 may be disposed on the motherboard 151. The baseboard management controller 1512 and the peripheral expander 1513 can communicate via a serial general input output signal SGPIO.
However, the serial general input/output interface is used for data transmission, which can reduce the demands of pins on hardware, but causes the problem of insufficient data transmission speed. Especially when there is only one bit difference between the previous data and the current data, the common general serial input/output interface still needs to transmit all the data bits. Therefore, how to reduce the data transmission delay (latency) of the serial universal input/output interface becomes an important issue for those skilled in the art.
Disclosure of Invention
The invention is directed to an adaptive serial universal input/output interface and a signal receiver, which can effectively reduce the signal transmission delay (latency) of the universal input/output interface.
According to an embodiment of the invention, the adaptive serial universal input output interface comprises a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transfer data and provides previous transfer data. The comparator is coupled to the first data buffer, receives the current transmission data, and receives the previous transmission data from the first data buffer. In the first mode, the comparator compares the previous transmission data with the current transmission data to generate data difference information. The encoder is coupled to the comparator, and generates at least one index value and a corresponding indication signal according to the data difference information in the first mode. The signal transmitter transmits at least one index value and an indication signal which are serial signals to a signal receiver.
According to an embodiment of the invention, the signal receiver comprises a decoder. The decoder is coupled to the signal transmitter, and is configured to receive the transmission signal based on the indication signal, decode the transmission signal to obtain at least one position of at least one variation bit, and adjust at least one bit of a previous received data according to the at least one position to generate the current received data.
In the adaptive serial general input/output interface according to the present invention, the signal transmitter can compare the previous transmitted data with the current transmitted data to obtain the data difference information, and the signal receiver can adjust the previous received data according to the data difference information to obtain the correct current received data by transmitting only the data difference information to the signal receiver. Therefore, the adaptive serial general input/output interface does not need to carry out all-bit-by-bit transmission action on the current transmission data every time, and can reduce the transmission delay generated in the transmission process.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 1A-1E are diagrams of various conventional security control module (DC-SCM) architectures of data centers, respectively;
FIG. 2 is a schematic diagram of an adaptive serial universal input/output interface according to an embodiment of the present invention;
FIG. 3A is a waveform diagram of a serial signal generated by an encoder according to an embodiment of the present invention;
FIG. 3B is a waveform diagram of a serial signal generated by an encoder according to another embodiment of the present invention;
FIG. 4 is a schematic waveform diagram of an adaptive serial universal input/output interface according to an embodiment of the present invention operating in different modes;
FIG. 5 is a schematic diagram of an adaptive serial universal input/output interface according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a mode signal generation mechanism according to an embodiment of the present invention;
fig. 7A and fig. 7B are waveforms of serial signals generated by an encoder according to another embodiment of the present invention.
Description of the reference numerals
200. 500: an adaptive serial universal input/output interface;
111. 1231, 1332, 1431, 1512: a baseboard management controller;
112. 122, 132, 142: a data center security control interface;
113: a programmable logic device;
GPIO: a general input/output signal pin;
SGPIO0, SGPIO1, SGPIO: serial universal input/output signals;
121. 131, 141, 151: a main board;
1312. 1412: a main processor module;
123. 1331: a safety control module;
1211. 1311: a central processing unit;
1212: a network bridge;
133. 143: a circuit board;
1432. 1513: a peripheral expander;
210. 510: a signal transmitter;
211. 511, 512, 522: a data buffer;
212. 513: a comparator;
213. 514: an encoder;
515: a controller;
516: an internal circuit;
520: a signal receiver;
521: a decoder;
530: an external circuit;
b0 to B127, A to Z: a bit;
CD: currently transmitting data;
CLK: a frequency signal;
DINF: data difference information;
DO: outputting a signal;
DA n 、DA n+1 、DA n+2 、DA n+3 、DB m 、DB m+1 、DB m+2 、DB m+3 、DA 7 ～DA 15 : updating data;
ID A ～ID Z : an index value;
IdA0 to IdA2, idB0 to IdB3: a digital code;
IdDA, idDB: updating data;
ld_t: an indication signal;
MD1: a first mode;
MD2: a second mode;
MS: a mode selection signal;
PD: previously transmitting data;
REG1 to REGN: a buffer;
TA, TB: a time interval;
TA1, TA2, TB1, TB2: a sub-time interval;
TXD: transmitting data;
W A ～W Z : a weight value;
XOR: exclusive or gate.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Referring to fig. 2, fig. 2 is a schematic diagram of an adaptive serial universal input/output interface according to an embodiment of the invention. The adaptive serial universal input output interface 200 includes a signal transmitter 210. The signal transmitter 210 includes a data buffer 211, a comparator 212, and an encoder 213. The data buffer 211 receives the transmission data TXD and temporarily stores the transmission data TXD. In the embodiment of the present invention, the data buffer 211 is controlled by the clock signal CLK. The data buffer 211 provides the previous transmission data PD according to the buffered transmission data TXD based on the clock signal CLK. The data buffer 211 may be one register REG or may have a plurality of registers REG 1-REGN, the register REG may perform a single-bit storing and outputting operation of the transmission data TXD according to the clock signal CLK, and the registers REG 1-REGN may perform a plurality of bits storing and outputting operation of the transmission data TXD according to the clock signal CLK. In addition, the present invention may have more than one stage of data buffer 211, and may have more than two stages of data buffers.
In addition, the comparator 212 is coupled to the data buffer 211. The comparator 212 receives the current transmission data CD and the previous transmission data PD. When the adaptive serial general input output interface 200 is operated in the first mode, the comparator 212 compares the plurality of bits of the current transmission data CD with the plurality of bits of the previous transmission data PD, respectively. In this embodiment, the transmission data TXD can be used as the current transmission data CD and is directly received by the comparator 212, and the previous transmission data PD is provided by the data buffer 211, and the current transmission data CD and the previous transmission data PD have the same bit number.
The comparator 212 generates the data difference information DINF by comparing the plurality of bits of the current transmission data CD with the plurality of bits of the previous transmission data PD, respectively, and according to one or more bits of the current transmission data CD that change from the previous transmission data PD. The data difference information DINF may describe which position(s) of the bits of the current transmission data CD change from the previous transmission data PD.
In this embodiment, the comparator 212 may be implemented by using a plurality of exclusive or gates XOR. The number of exclusive-or gates XOR may be the same as the number of bits of the current transfer data CD (the current transfer data CD has the same number of bits as the previous transfer data PD). Taking the example that the current transmission data CD and the previous transmission data PD each have eight bits, the corresponding exclusive or gate XOR may generate an output equal to logic 1 if the current transmission data CD is different from the nth bit of the previous transmission data PD, and the corresponding exclusive or gate XOR may generate an output equal to logic 0 if the current transmission data CD is identical to the mth bit of the previous transmission data PD, where m and n are different positive integers.
According to the above description, the exclusive or gates XOR in the comparator 212 can generate the data difference information DINF with multiple bits according to the comparison result of the corresponding bits of the current transmission data CD and the previous transmission data PD. In this embodiment, the bit of the data difference information DINF is a logical 1, which indicates that the corresponding data of the bit of the current transmission data CD is different from the data of the bit of the previous transmission data PD.
It should be noted that any circuit capable of performing data comparison can be applied to the comparator 212 for implementing the present invention, and the implementation of the comparator 212 by exclusive or gate XOR in fig. 2 is merely an illustrative example, and is not intended to limit the scope of the present invention. The present invention is also not limited to the bit of the data difference information DINF being logic 1, which indicates that the corresponding data of the bit of the current transmission data CD is different from the data of the bit of the previous transmission data PD. A logic 1 may also be used to indicate that the corresponding currently transmitted data CD is the same as the data of the bits of the previously transmitted data PD.
The encoder 213 is coupled to the comparator 212. The encoder 213 receives the data difference information DINF generated by the comparator 212, and generates at least one index value and a corresponding indication signal according to the data difference information DINF in the first mode. Herein, please refer to fig. 2 and fig. 3A in synchronization, wherein fig. 3A is a waveform diagram of a serial signal generated by an encoder according to an embodiment of the present invention. The encoder 213 generates an index value according to the position of the changed bit, which is indicated in the data difference information DINF, between the previous transmission data PD and the current transmission data CD. For example, if the P-th bit and the Q-th bit of the previous data PD change from the current data CD, the encoder 213 may encode P to generate an index value combined by codes (e.g., binary codes) IdA 0-IdA 2, and the encoder 213 may encode Q to generate an index value combined by codes IdB 0-IdB 3, wherein P, Q is a positive integer.
The encoder 213 sequentially concatenates the codes IdA 0-IdA 2 and the codes IdB 0-IdB 3 into a serial signal in the time interval TA and the time interval TB based on the frequency signal CLK. Correspondingly, the encoder 213 can correspondingly generate the indication signal LD_T according to the contents of the digits IdA 0-IdA 2 and the digits IdB 0-IdB 3. In this embodiment, the waveform of the indication signal ld_t may be generated according to the corresponding index value. The index value of the index codes IdA0 to IdA2 corresponding to 3 bits, the indication signal ld_t may be kept equal to logic 1 in the sub-time period TA1 corresponding to 2 bits, and pulled down to logic 0 in the sub-time period TA2 corresponding to 1 bit. In addition, the index value composed of the numbers IdB0 to IdB3 corresponding to 4 bits, the indication signal ld_t may be kept equal to logic 1 in the sub-period TB1 corresponding to 3 bits, and pulled down to logic 0 in the sub-period TB2 corresponding to 1 bit. In this embodiment, the sub-time intervals TA2 and TB2 pulled down to logic 0 respectively correspond to the last bit of different index values.
In addition, in the present embodiment, the bit number of the index value may be determined by the position size of the variation bit that varies between the transmission data PD and the current transmission data CD. When the first bit is the 4 th bit, the numbers IdA0 to IdA2 may be 0, 1, respectively. When the second variation is the 10 th bit, the numbers IdB0 to IdB3 may be 0, 1, respectively. And when the position of the metamorphic bit is greater than 15 (for example, equal to 16), the index value may have five bits of data and be 0, 1, respectively.
The transmission order of the index values in the present embodiment is not specific, and the time interval TB in fig. 3A may also occur before the time interval TA. In one embodiment, the encoder 213 may adjust the arrangement order of the index values according to the importance of the variation bits.
Incidentally, in the present embodiment, the number of bits of the index value is not less than 3. When the position of the variation bit is not less than 4, the most significant bit in the data of the index value is equal to 1. If the position of the index value is smaller than 4, the most significant bit in the data of the index value may be 0.
In the present embodiment, the signal transmitter 210 may transmit a serial signal composed of one or more index values to a signal receiver through the output signal DO based on the frequency signal CLK. The signal transmitter 210 transmits the indication signal ld_t to the signal receiver corresponding to the output signal DO.
The encoder 213 in this embodiment may be constructed by a digital circuit. Encoder 213 may be implemented by a truth table, a carnot, a hardware description language, or any other digital circuit design method known to those of ordinary skill in the art, without limitation.
It should be noted that, in the present embodiment, the signal transmitter 210 only transmits the previous transmission data PD and the current transmission data CD at the different positions. In this way, the signal receiver can obtain the position of the bit that is changed according to the index value, and can obtain the current received data equal to the current transmitted data CD by performing a transition operation on one or more bits of the bit that is changed in the previous received data. Based on the above, the time for data update in the adaptive serial universal input/output interface 200 can be effectively reduced, and the working efficiency of the system can be improved.
Incidentally, in the present embodiment, in the initial state, the signal transmitter 210 needs to perform the bit-by-bit transmission of the transmission data TXD for the signal receiver at least once in the second mode, and enables the signal receiver to have the previously received data. The subsequent signal transmitter 210 may enter the first mode and perform the update action of the transmitted data by transmitting only the index value and the indication signal.
Based on the fact that in the second mode, the data buffer 211 and the comparator 212 do not need to perform actions, the data buffer 211 and the comparator 212 can be disabled to save power consumption.
It should be noted that, in the embodiment of the present invention, in order to ensure the correctness of the data, the signal transmitter 210 may perform a counting operation and generate the refresh time period according to the counting operation. The signal transmitter 210 may also cause the transmission data TXD to be transmitted to the signal receiver bit by bit in a serial manner based on the frequency signal according to the refresh time period. That is, the gpio interface 200 of the present embodiment may periodically perform the data transfer operation of the second mode.
On the other hand, the signal transmitter 210 may also perform the above-mentioned data refreshing operation according to the demand command received by the external electronic device, and serially transmit the transmission data TXD to the signal receiver bit by bit based on the frequency signal.
It should be noted that the counting operation performed by the signal transmitter 210 may be reset after each data refreshing operation is completed. In brief, after each data transfer operation of the second mode of the adaptive serial-to-universal-input-output interface 200 is completed, the counting operation performed by the signal transmitter 210 may be restarted.
Referring to fig. 2 and fig. 3B, fig. 3B is a waveform diagram of a serial signal generated by an encoder according to another embodiment of the invention. In the present embodiment, the encoder 213 generates the index value and the update data corresponding to the index value according to the obtained data difference information DINF and the current transmission data CD in the first mode. In this embodiment, the encoder 213 generates the serial signal according to the index value generated by the position of the metamorphic position. The encoder 213 generates an update data according to the bit value corresponding to the different strain in the current transmission data CD, and generates a serial signal according to the index value and the corresponding update data. In fig. 3B, the encoder 213 may encode the position for the first variant bit, and generate an index value combined by the numbers IdA0 to IdA2 (e.g., binary codes). The encoder 213 also encodes the position for the second variant bit to generate an index value combined by the numbers IdB0 to IdB 3. The encoder 213 generates the update data IdDA and IdDB according to the data corresponding to the first and second variations in the current transmission data CD. The encoder 213 sequentially concatenates the digital codes IdA 0-IdA 2, the update data IdDA, the digital codes IdB 0-IdB 3, and the update data IdDB into a serial signal, and sends the serial signal to a signal receiver through the output signal DO.
In this embodiment, the encoder 213 may pull down the indication signal ld_t during the sub-time periods TA2, TB2 corresponding to the transmission of the update data IdDA, idDB. The instruction signal LD_T is maintained at logic 1 during the sub-time periods TA1, TB1 of the index value-transmitting numerals IdA0 to IdA2, idB0 to IdB 3.
Referring to fig. 4, fig. 4 is a schematic waveform diagram of an adaptive serial universal input/output interface according to an embodiment of the invention. The signal transmitter of the adaptive serial universal input/output interface may perform the transmission actions with the index value and the corresponding update data in the first mode MD1 as in the embodiment of fig. 3B. And, after the first mode MD1, the adaptive serial universal input/output interface can be switched in real time to be executed in the second mode MD2, and the output signal DO is matched with the clock signal CLK and the indication signal ld_t to transmit the plurality of bits B0-B127 of the current transmission data bit by bit.
It should be noted that, in the second mode, the indication signal ld_t may be used as a synchronization signal. At the point when the indication signal ld_t is pulled up from logic 0 to logic 1, it indicates that the transmission of the current transmission data is started. The next time the indication signal LD_T is pulled high from logic 0 to logic 1 indicates that all bit transfers of the currently transmitted data are complete.
In the second mode MD2, the indication signal ld_t is pulled up to logic 1 for a period of time equal to only one period of the clock signal CLK, corresponding to a period of time for transmitting one bit. In this way, the signal receiver can determine that the signal transmitter performs the signal transmission operation according to the protocol of the first mode MD1 or the protocol of the second mode MD2 according to the change of the indication signal ld_t. In other words, when the transmission operation with the index value and the corresponding update data in the embodiment of fig. 3B is performed in the first mode MD1, it should be noted that the index value needs two bits at the minimum, so as to ensure that the signal receiver can determine whether the signal transmitter is according to the protocol of the first mode MD1 or the protocol of the second mode MD2 according to the change of the indication signal ld_t. Accordingly, when the index value is less than two bits, the embodiment of fig. 3B is required to complement the index value by two bits. Similarly, when the transmission operation with only the index value is performed in the first mode MD1 as in the embodiment of fig. 3A, it should be noted that the index value needs three bits at the minimum, so as to ensure that the signal receiver can determine whether the signal transmitter is according to the protocol of the first mode MD1 or the protocol of the second mode MD2 according to the change of the indication signal ld_t. Accordingly, when the index value is less than three bits, the embodiment of fig. 3A complements the index value by three bits.
Here, the indication signal ld_t is an output signal corresponding to the signal transmitter, and the output signal DO is an output signal of the signal transmitter as well. The indication signal LD_T is an input signal corresponding to the signal receiver, and the output signal DO is an input signal of the signal receiver.
Referring to fig. 5, fig. 5 is a schematic diagram of an adaptive serial universal input/output interface according to another embodiment of the invention. The adaptive serial universal input output interface 500 includes a signal transmitter 510 and a signal receiver 520. The signal transmitter 510 is coupled to the signal receiver 520. The signal transmitter 510 includes data buffers 511, 512, a comparator 513, an encoder 514, a controller 515, and an internal circuit 516. The signal transmitter 510 may be further coupled to an external circuit 530. The data buffer 511 is used as a first-stage data buffer, and is capable of receiving the transmission data TXD from the internal circuit 516 or the external circuit 530 and temporarily storing the transmission data TXD. The data buffer 511 is operable according to the clock signal CLK, and transfers the buffered transmission data TXD to the second-stage data buffer 512, and provides the transmission data TXD as the current transmission data CD to the comparator 513. The data buffer 512 also operates according to the clock signal CLK, and can be used to provide the previous transfer data PD to the comparator 513. The data buffers 511 and 512 may be a single register REG, or may have a plurality of registers REG 1-REGN, wherein the register REG may perform a single-bit storing and outputting operation of the transmission data TXD according to the clock signal CLK, and the registers REG 1-REGN may perform a plurality of bits storing and outputting operation of the transmission data TXD according to the clock signal CLK.
The comparator 513 is configured to compare the previous data PD with the current data CD in the first mode, and generate data difference information to indicate the position of the changed bit. In one embodiment, the encoder 514 receives the data difference information and encodes the data difference information according to the position of the variation, the mode selection signal MS and the clock signal CLK to generate a data output signal with an index value and a corresponding indication signal. In another embodiment, the encoder 514 receives the data difference information and encodes the data according to the position of the changed bit and the currently transmitted data CD to generate a data output signal having an index value and updated data and a corresponding indication signal.
Details of the operation of the signal transmitter 510 are described in the foregoing embodiments, and are not repeated here.
In this embodiment, the encoder 514 may have a parallel-to-serial circuit, and may convert the data difference information of the parallel signal and output the index value and the indication signal as the serial signal.
Incidentally, in the present embodiment, the signal transmitter 510 includes a controller 515. The controller 515 is configured to generate a mode selection signal MS, wherein the controller 515 is configured to operate in the first mode or the second mode by the mode selection signal MS. The controller 515 may calculate a time required for the data transfer operation of transferring data in the second mode (e.g., equal to the time TN), and set a critical time according to the time TN. In addition, the controller 515 may calculate a time (e.g., equal to the time TM) required for performing the data transmission operation of the index value by using the first mode according to the number and the position of the variation bits in the data difference information, and generate the mode selection signal MS by comparing whether the time TM is greater than the critical time.
In detail, when the time TM is less than the critical time, the controller 515 may generate the mode selection signal MS to be a first logic value and operate the signal transmitter 510 in the first mode. When the time TM is not less than the critical time, the controller 515 may generate the mode selection signal MS having the second logic value and operate the signal transmitter 510 in the second mode. Wherein the first logic value is opposite to the second logic value.
It is noted that the critical time may be equal to or less than time TN.
In another aspect, the signal receiver 520 includes a decoder 521 and a data buffer 522. Decoder 521 receives the data output signal (e.g., output signal DO of fig. 4), the indication signal ld_t, and the frequency signal CLK from the signal transmitter 510. The decoder 521 can learn the operation mode of the signal transmitter 510 by decoding the indication signal ld_t based on the frequency signal CLK. The decoder 521 decodes the data output signal based on the clock signal CLK according to the operation mode of the signal transmitter 510, and may obtain one or more bit-shifted positions or further obtain one or more updated data. In another embodiment, the decoder 521 may not directly receive the clock signal CLK, but only receive any signal of the clock signal CLK of the synchronous signal transmitter 510, and generate the clock signal CLK by using the local clock signal CLK 1. The decoder 521 may toggle one or more bits of the previously received data according to the position of the variation bit, or perform an update operation on the previously received data according to the position of the variation bit and the corresponding update data. Thus, the correct current received data can be obtained.
The currently received data may be stored in the data buffer 522. The decoder 521 may have a serial-to-parallel circuit, and may convert the received serial signal into a parallel signal and store the parallel signal in the data buffer 522. The data buffer 522 may be composed of a plurality of buffers, and the number of buffers may be the same as the number of bits of the currently received data.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a mode signal generation mechanism according to an embodiment of the invention. It is noted that in the embodiment of the present invention, the index value ID generated by the encoder of the signal transmitter A ～ID Z The number of bits of (2) varies with the position of the variant bit. For example, index value ID A Having a+1 bits; index value ID B Having B-A bits; index value ID C Having C-B bits; index value IDz has Z-Y bits.
Specifically, the index value generated for the variant bit of the relatively low significant bit may have a first number of bits. The index value generated for the variant bits compared to the relatively more significant bits may have a second number of bits, which may be greater than the first number of bits. Therefore, in the present embodiment, a plurality of time weight values WA to WZ can be set for different positions corresponding to the variation bits, respectively. When the signal transmitter is to transmit data, the controller can calculate the sum of the time weight values corresponding to all the variation bits, and then compare the sum of the time weight values with a preset critical time value, so as to be used as the basis for generating the mode selection signal. When the sum of the time weight values is smaller than a preset critical time value, the signal transmitter can select a first mode to operate, and when the sum of the time weight values is not smaller than the preset critical time value, the signal transmitter can select a second mode to operate.
Referring to fig. 7A and fig. 7B, fig. 7A and fig. 7B are waveform diagrams of serial signals generated by an encoder according to another embodiment of the invention. Fig. 7A and 7B illustrate a burst data transfer mode (third mode) according to an embodiment of the invention. Fig. 7A and 7B are applicable to the systems of fig. 2 and 5, and are described below with reference to fig. 2 only. Please refer to fig. 2 and fig. 7A synchronously. In fig. 7A, the encoder 213 may generate the index value according to the position of the start bit of the variation bit that varies between the previous transmission data PD and the current transmission data CD as indicated in the data difference information DINF. For example, if the nth bit and the mth bit start to change between the previous data PD and the current data CD, the encoder 213 may encode n to generate an index value combined by the digits IdA0 to IdA2 (e.g. binary digits), and the encoder 213 encodes m to generate an index value combined by the digits IdB0 to IdB3, where n and m are positive integers.
The start bit of the variation bit may be set according to the grouping condition of the bit sequence of the variation bit between the previous transmission data PD and the current transmission data CD. For example, when the metamorphosis can be divided into two groups, the first metamorphosis of the first group can be the nth bit, and the first metamorphosis of the second group can be the mth bit.
The encoder 213 concatenates the digital codes IdA 0-IdA 2 into a serial signal during the sub-time period TA1 based on the clock signal CLK. The encoder 213 generates the indication signal LD_T according to the contents of the codes IdA 0-IdA 2. The index value formed by the digits IdA0 to IdA2 corresponding to 3 bits, the indication signal ld_t may be kept equal to logic 1 in the sub-time interval TA1 corresponding to 3 bits, and pulled down to logic 0 in the subsequent sub-time interval TA 2. Note that in the burst mode, the indication signal ld_t is maintained equal to the logic 0 for a period of time corresponding to a plurality of periods of the clock signal CLK. And, when the indication signal ld_t remains equal to logic 0, the encoder 213 causes the output signal DO to start from the nth bit, and sequentially transfers the update data DA to be updated according to the bit order in the sub-time period TA2 n 、DA n+1 、DA n+2 DA (data acquisition) system n+3 Until the indication signal ld_t is pulled back high to logic 1.
Then, the encoder 213 generates the indication signal ld_t according to the contents of the digits IdB0 to IdB 3. The index value formed by the numbers IdB0 to IdB3 corresponding to 4 bits, the indication signal ld_t may be kept equal to logic 1 in the sub-period TB1 corresponding to 4 bits, and pulled down to logic 0 in the subsequent sub-period TB 2. Here, the indication signal ld_t is maintained equal to the logic 0 for a period of time, which corresponds to a plurality of periods of the clock signal CLK. And, when the indication signal LD_T remains equal to logic 0, the output signal DO starts from the mth bit and sequentially transfers the update data DB to be updated according to the bit order m 、DB m+1 、DB m+2 DB (database) m+3 … until the indication signal ld_t is pulled back high to logic 1.
In addition, in fig. 7B, the encoder 213 may detect that the start bit of the mutated bit is the 7 th bit according to the data difference information DINF, and that there are a plurality of consecutive or non-consecutive bits after the 7 th bit. At this time, the encoder 213 may encode 7 and generate the numbers IdA0 to IdA2, and the numbers IdA0 to IdA2 may be equal to 1, 1. Encoder 213 and maintains the indication signal LD_T equal to the logic during the sub-time period TA1Edit 1. The sub-time period TA1 corresponds to a transmission time of three bits. In a sub-period TA2 following the sub-period TA1, the encoder 213 changes the instruction signal LD_T to logic 0 and transmits the update data DA to be updated in accordance with the output signal DO in bit order 7 、DA 8 、DA 9 …DA 15 …. It should be noted that the above-mentioned transmission of updated data may be continued until the indication signal ld_t is pulled up again to logic 1.
It should be noted that if the transmission of the update data is maintained to the last bit, the encoder 213 may pull the indication signal ld_t high to logic 1 after all the update data are transmitted. At this time, the signal transmitter 210 may perform a data re-refresh action or perform a dummy (dummy) data refresh action. In the data re-refresh action, the signal transmitter 210 may perform a data transfer action of the second mode. The data transmission operation of the second mode is described in detail in the foregoing embodiments, and will not be repeated here. In the dummy data refresh operation, the signal receiver corresponding to the signal transmitter 210 does not perform the data update operation according to the received output signal DO.
According to the above, the data transmitter of the adaptive serial universal input output interface of the present invention may not transmit data for all bits of transmission data, but only transmit the bit positions of the variation bits. In this way, the delay of data transmission can be effectively reduced in the case that only a part of the currently transmitted data is different from the previously transmitted data.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (21)

1. An adaptive serial universal input output interface comprising:
a signal transmitter, comprising:
a first data buffer for receiving the current transmission data and providing the previous transmission data;
a comparator coupled to the first data buffer, receiving the current transmission data and receiving the previous transmission data from the first data buffer, and comparing the previous transmission data and the current transmission data to generate data difference information in a first mode; and
the encoder is coupled with the comparator and generates at least one index value and a corresponding indication signal according to the data difference information in the first mode;
wherein the signal transmitter transmits the at least one index value as a serial signal and the indication signal,
the indication signal is used for indicating the last bit of the corresponding index value by a first logic value and indicating at least one non-last bit of the corresponding index value by a second logic value, wherein the first logic value is different from the second logic value, and the bit number of the indication signal is not less than 3.
2. The adaptive serial universal input/output interface according to claim 1, wherein said comparator compares a plurality of bits of said previously transmitted data with a plurality of bits of said currently transmitted data, respectively, to generate said data difference information according to at least one position of at least one variant bit that is different.
3. The adaptive serial universal input output interface according to claim 2, wherein the encoder generates the at least one index value as a function of a binary number of the at least one location.
4. The adaptive serial universal input output interface according to claim 3, wherein the at least one index value has at least three bits.
5. The adaptive serial universal input output interface of claim 2, further comprising:
a signal receiver, comprising:
a decoder, coupled to the signal transmitter, for receiving the at least one index value based on the indication signal, and decoding the at least one index value to obtain the at least one position of the at least one metamorphic bit; and
the controller is coupled to the decoder and generates a current received data according to at least one bit of the at least one position in the previous received data.
6. The adaptive serial universal input output interface according to claim 2, wherein the encoder generates at least one update data corresponding to the at least one index value according to the data difference information and the currently transmitted data in the first mode.
7. The adaptive serial universal input output interface according to claim 6, wherein the signal transmitter sends a serial signal formed by the at least one index value and the corresponding at least one update data.
8. The adaptive serial universal input output interface according to claim 7, further comprising:
a signal receiver, comprising:
the decoder is coupled to the signal transmitter, and is configured to receive the at least one index value based on the indication signal, decode the at least one index value to obtain the at least one position of the at least one variation bit, and generate a currently received data by changing at least one bit of the previously received data according to the at least one position and the at least one updated data.
9. The adaptive serial universal input output interface according to claim 1, wherein said signal transmitter further comprises:
and a controller for generating a mode selection signal by which to set the signal transmitter to operate in the first mode, the second mode or the third mode.
10. The adaptive serial universal input output interface according to claim 9, wherein in said second mode said signal transmitter serially causes said currently transmitted data to be transmitted bit by bit to a signal receiver based on a frequency signal.
11. The adaptive serial universal input output interface according to claim 9, wherein in the second mode, the first data buffer and the comparator are disabled from performing operations.
12. The adaptive serial universal input/output interface according to claim 9, wherein in the third mode, the encoder obtains at least one start bit of a plurality of metamorphosis according to the data difference information, generates the at least one index value according to the at least one start bit, and generates a plurality of update data corresponding to the at least one index value according to the currently transmitted data.
13. The adaptive serial universal input output interface according to claim 9, wherein the data transfer action of the controller calculating the at least one index value requires a first time and comparing the first time with a critical time to generate the mode select signal.
14. The adaptive serial universal input-output interface according to claim 13, wherein the data transfer action of the currently transferred data in the second mode requires a second time, the critical time being set in accordance with the second time.
15. The adaptive serial general purpose input/output interface according to claim 9, wherein the controller sets a plurality of time weight values according to bits of the transmission data, calculates a sum of the time weight values corresponding to at least one variation bit according to the data difference information, and generates the mode selection signal according to comparing the sum with a threshold time value.
16. The adaptive serial universal input output interface of claim 1 wherein said signal transmitter serially causes said transmission data to be transmitted bit by bit based on a frequency signal in accordance with a refresh time period, said signal transmitter further serially causes said transmission data to be transmitted bit by bit based on said frequency signal in accordance with a demand command.
17. The adaptive serial universal input output interface according to claim 16, wherein said signal transmitter counts said refresh time period by a counting action and resets said counting action in accordance with said demand command or mode select signal.
18. The adaptive serial universal input output interface according to claim 1, wherein said signal transmitter further comprises:
the second data buffer is coupled to the front end of the first data buffer, receives source data and provides the current transmission data according to the temporarily stored source data.
19. A signal receiver, comprising:
a decoder coupled to the signal transmitter for receiving the transmission signal based on the indication signal, and decoding the transmission signal to obtain at least one position of at least one variation bit, adjusting at least one bit of a previously received data according to the at least one position to generate the currently received data,
the indication signal is used for indicating the last bit of the corresponding index value by a first logic value and indicating at least one non-last bit of the corresponding index value by a second logic value, wherein the first logic value is different from the second logic value, and the bit number of the indication signal is not less than 3.
20. The signal receiver of claim 19, wherein the transmission signal comprises at least one index value, the controller toggles for the at least one bit in the previously received data according to the at least one position to generate the currently received data.
21. The signal receiver of claim 19, wherein the transmission signal comprises at least one index value and at least one update data corresponding to the at least one index value, the controller altering the at least one bit in previously received data according to the at least one location and the at least one update data to generate the currently received data.
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