CN1191529C - General asynchronous serial port controller - Google Patents
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- CN1191529C CN1191529C CN 01107426 CN01107426A CN1191529C CN 1191529 C CN1191529 C CN 1191529C CN 01107426 CN01107426 CN 01107426 CN 01107426 A CN01107426 A CN 01107426A CN 1191529 C CN1191529 C CN 1191529C
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Abstract
The present invention discloses a universal asynchronous serial port controller used in the field of a computer, which has a structure for supporting double bus access. The present invention comprises internal control logic of the universal asynchronous serial port controller, data sending logic, data receiving logic, first interface logic, second interface logic, third interface logic, fourth interface logic, fifth interface logic and a CPUDMA register. When DMA and the universal asynchronous series port controller carry out data exchange, a central processing unit and the DMA can carry out concurrent working; simultaneously, an internal state of the universal asynchronous serial port controller is queried or a control register is set, and thus, the present invention fully utilizes system resources and improves work efficiency of a system.
Description
Technical field the present invention relates to computer system, relates in particular to the field of data exchange in the computer realm.
Background technology is present, increasingly extensive along with computer utility, travelling speed to computing machine, efficient and stability etc. have also proposed more and more higher requirement, but at present more situation but is, quickening along with the central processing unit speed of computing machine, and its operational efficiency reduces relatively, this mainly is because in existing computer system, a central processing unit is connected on the system bus, central processing unit directly be connected system bus on various device communicate by letter, and system and outside carry out exchanges data core component---general asynchronous serial port controller (UART) is also only supported single system bus, and directly hang over this unique system bus, so just make the DMA in central processing unit and the system can not keep concurrent working, seriously influenced the whole efficiency of system's operation.In single system bus shown in Figure 1 system, central processing unit carries out initialization to general asynchronous serial port controller earlier, when receiving enough data from the outside, this general asynchronous serial port controller just sends out interruption to interruptable controller, this interrupts handling through the arbitration of interruptable controller, send to central processing unit then, central processing unit receives in this and has no progeny, the interrupt vector controller of inquiry interruptable controller, judge whether it is the interruption that general asynchronous serial port controller sends, central processing unit is inquired about the interrupt status register of general asynchronous serial port controller then, if acceptance interruption, with regard to initialization corresponding D MA control register, and withdraw from control to bus, by the control of DMA application system bus; Obtain the control of system bus as DMA after, just occupy system bus alone, carry out the data transmission of the data register of general asynchronous serial port controller to storer (in the sheet or outside the sheet), after the data volume that central processing unit is provided with to the DMA initialization time is finished by the DMA transmission, DMA just cancels the control to system bus, simultaneously send look-at-me to interruptable controller, this look-at-me sends to central processing unit through after the arbitration of interruptable controller; The interrupt status register of central processing unit inquiry interruptable controller, when finding is a look-at-me that DMA sends, obtain the control of system bus earlier, inquire about the interrupt status register of corresponding D MA then, when finding it is the data transmitted of DMA whole end of transmissions, with regard to the control register of reconfigurable DMA; Process of transmitting for general asynchronous serial port controller is also similar.Because existing general asynchronous serial port controller can only be supported unibus structure, so what existing systems adopted substantially all is the structure of unibus, central processing unit and DMA hang on same the system bus, in DMA transmission data, the control of system bus is occupied alone by DMA, central processing unit is wanted to inquire about relevant status register or control register is set, and all needs to obtain earlier the control of bus, just can do corresponding operation then.Equally, DMA transmits data if desired, also will obtain the control of system bus earlier, could transmit data then.Central processing unit and DMA can not work simultaneously like this, and overall system efficiency has been lost a lot in the mutual transmission of bus control right.And, all can have a strong impact on the performance of system to the repeatedly interruption of central processing unit.
Summary of the invention the purpose of this invention is to provide a kind of support dual bus visit, general asynchronous serial port controller efficiently, to solve the shortcoming that can only support a bus, inefficiency of the prior art.
To achieve these goals, the present invention has constructed a kind of general asynchronous serial port controller, comprise that general asynchronous serial port controller inner control logic, data send logic and Data Receiving logic, it is characterized in that, also comprise first interface logic, second interface logic, the 3rd interface logic, the 4th interface logic, the 5th interface logic and central processing unit direct access visit (CPUDMA) register;
Described first interface logic receives chip selection signal Ccs, read-write Cwr and the address signal Caddr of article one system bus, generate inner control logic enable signal Cen and send to described general asynchronous serial port controller inner control logic, article one system bus read-write enable signal 302 that generates sends to described the 4th interface logic, and article one system bus data register enable signal 301 of generation sends to described the 3rd interface logic and the 4th interface logic respectively;
Described the 4th interface logic is made of one group of alternative selector switch and three-state buffer, the steering logic read data bus signal CdataR that reception is sent by the general asynchronous serial port controller inner control logic, and the data register read data bus signal DrdataR that sends by the Data Receiving logic, its selecting side receives the second system bus data register enable signal 303 that sends from described first interface logic, its output terminal is connected on the data bus Cdata, and the other end of described data bus Cdata is connected to the steering logic write data port CdataW in the described general asynchronous serial port controller inner control logic;
Described second interface logic receives chip selection signal Dcs, the address signal Daddr of second system bus transmission and the read-write Dwr of second system bus, generate second system bus data register enable signal 303 and send to described the 3rd interface logic and the 5th interface logic, generate second system bus read-write enable signal 304 and send to described the 5th interface logic;
Described the 5th interface logic adopts a three-state buffer, receive second system bus data register enable signal 303 and second system bus read-write enable signal 304 that described second interface logic sends, receive data bus signal DrdataR from the Data Receiving logic, send it to the data bus Ddata in the second system bus;
It still is the DMA pattern that described the 3rd interface logic is selected to use central processor model by described CPUDMA register controlled, receive the data bus Cdata of article one system bus, the data bus Ddata of second system bus, article one, system bus data register enable signal 301, second system bus data register enable signal 303, the read-write Dwr of read-write Cwr and second system bus, write enable signal DrWen to described data transmission logic output data register write data bus DrdataW and data register, read enable signal DrRen to described Data Receiving logic transmitting data register;
Described read-write Cwr, address signal Caddr directly are connected with CdataW with corresponding port Cwr, the Caddr of described general asynchronous serial port controller inner control logic respectively with data bus Cdata.
After central processing unit is finished initialization to DMA and UART, the thing that central processing unit just can be Myself, the transmission of data is finished just passable by DMA and UART, need not constantly interrupt central processing unit, also reduce the performance of system without switching back and forth of system bus, central processing unit can with the complete concurrent operations of the transmission of UART data, improved the performance of system greatly.When the data of DMA and UART are being transmitted, central processing unit need not interrupt this data transmission at the UART that carries out, and just can inquire about the internal state of UART, even control register is set, the efficient that this has also improved data transmission has greatly improved the performance of system on the whole.
The invention will be further described below in conjunction with accompanying drawing for description of drawings;
Fig. 1 is the general asynchronous serial port controller logic diagram of an existing system bus interface;
Fig. 2 is the system architecture sketch that inside of the prior art has only a system bus;
Fig. 3 is the general asynchronous serial port controller logic diagram of the present invention's dual system bus interface of constructing;
Fig. 4 is the system architecture sketch with two system buss as embodiment of the present invention.
Embodiment Fig. 1 is the general asynchronous serial port controller that has a bus interface, this controller is divided into 3 parts: one is the steering logic of general asynchronous serial port controller inside, comprise control and status register that general asynchronous serial port controller is all, central processing unit is provided with control register in the general asynchronous serial port controller inner control logic by system bus, steering logic sends the status signal that logic and Data Receiving logic receive according to the setting of control register and from data, and control data sends the action of logic and Data Receiving logic; It mainly is under the control of inner control logic that data send logic, receives the data of sending from data bus Cdata, sends from data sending terminal TxD then; The Data Receiving logic mainly is under the control of inner control logic, receives from external data receiving end RxD and receives the data of coming, and in inside string and conversion, is put on the data register, waits for that the primary controller on the internal bus is taken away; Because general asynchronous serial port controller has only a system interface,, can't support dual-bus structure so can only be connected with a system bus.
In the system architecture sketch that has only a system bus of the prior art shown in Figure 2, system bus is responsible for the various piece of chip internal is linked together; Central processing unit links to each other with this system bus, is responsible for the work of various piece in control and the coordination chip; On system bus, also have a direct memory access (DMA) controller DMA, be responsible for the exchanges data between peripheral hardware and the storer, thereby make the exchange of data not need central processing unit is interrupted; General asynchronous serial port controller UART also is connected with system bus, in the ordinary course of things, this general asynchronous serial port controller UART has two signal line and outside swap data, article one, be serial data output terminal TxD, article one, be serial data input end RxD, central processing unit or DMA send data by general asynchronous serial port controller UART to the outside, in general asynchronous serial port controller UART, finish and go here and there conversion, send in the mode of serial from serial data output terminal TxD then, equally, the serial data of accepting from the outside, to import with serial mode from serial data input end RxD, data are finished string and conversion in general asynchronous serial port controller UART inside then, and central processing unit or DMA take data away from system bus again; Also hang with an interruptable controller on the system bus, be responsible for the look-at-me of inner each parts of receiving chip, DMA look-at-me as shown in FIG. and the look-at-me of general asynchronous serial port controller UART, through behind the priority discrimination, a look-at-me is sent to central processing unit by the look-at-me line that is connected between central processing unit and the interruptable controller; Also connected two storeies on system bus, one is chip external memory, mainly is bigger program and the data of storage one tittle; One is on-chip memory, mainly is to deposit the instruction and data that some need high speed and central processing unit to exchange; In DMA transmission data, the control of system bus is occupied alone by DMA, and central processing unit is wanted to inquire about relevant status register or control register is set, and all needs to obtain earlier the control of bus, just can do corresponding operation then.Equally, DMA transmits data if desired, also will obtain the control of system bus earlier, could transmit data then.Central processing unit and DMA can not work simultaneously like this, and overall system efficiency has been lost a lot in the mutual transmission of bus control right.And, all can have a strong impact on the performance of system to the repeatedly interruption of central processing unit.
The centre of two dotted lines shown in Figure 3 is the interface sections with general asynchronous serial port controller of two system bus interfaces, is the signal wire of two system bus interfaces at last dotted line with top, and following dotted line is the internal logic of general asynchronous serial port controller with the lower part.Realizing supporting that the interface section is the key component of total in the process of dual bus interface, the internal logic part of general asynchronous serial port controller is little with existing universal architecture difference.Article one, the signal wire of system bus has: the chip selection signal Ccs of article one system bus, and when article one system bus was chosen general asynchronous serial port controller, this signal was effective; Article one, the address signal Caddr of system bus, this is a bus signals, when chip selection signal was effective, this signal provided the offset address of register for general asynchronous serial port controller inside; Article one, the read-write Cwr of system bus, this signal are that explanation is read inner operation registers or write (high level is a write operation, and low level is read operation); Article one, the data-signal Cdata of system bus, this signal is a two-way data bus, when the register to general asynchronous serial port controller inside carries out write operation, this bus provides the data that write, when from the general asynchronous serial port controller read data time, the data that the async-generic asynchronous serial port controller is read central processing unit are put on the data bus, and then, central processing unit is taken away from bus.The signal wire of second system bus has: the chip selection signal Dcs of second system bus, choose general asynchronous serial port controller when the second system bus, and this signal is effective; The address signal Daddr of second system bus, this is a bus signals, when chip selection signal is effective, this signal provides the offset address of register for general asynchronous serial port controller inside, because the second system bus can only carry out read-write operation to the data register of general asynchronous serial port controller, so the register of other beyond this address bus is chosen data register can not form actual operation to inside; The read-write Dwr of second system bus, this signal are that explanation is read or write (high level is a write operation, and low level is read operation) inner operation registers; The data-signal Ddata of second system bus, this signal is a two-way data bus, when the register to general asynchronous serial port controller inside carries out write operation, this bus provides the data that write, when from the general asynchronous serial port controller read data time, the async-generic asynchronous serial port controller is put into the data that direct memory access (DMA) controller DMA reads on the data bus, is taken away from bus by DMA then.
The internal logic of general asynchronous serial port controller comprises that general asynchronous serial port controller inner control logic, data send logic and Data Receiving logic, the function of this part mainly is to introduce data and control signal that interface logic is changed inner, finish the also string conversion of data, send to the outside by serial data output terminal (TxD) then.The data of outside serial input are come in from serial data receiving end (RxD) sampling, after going here and there then and changing, wait for reading of main equipment (central processing unit or DMA), wherein, general asynchronous serial port controller inner control logic major function is to preserve the major control signal of central processing unit to general asynchronous serial port controller, send the corresponding status signal of logic and Data Receiving logic then by reading of data, generate some inner control signals and control the running of general asynchronous serial port controller, most of status information of the inside of in store general asynchronous serial port controller of while, inquiry in order to central processing unit, the input signal of general asynchronous serial port controller internal control register has: steering logic enable signal Cen, this signal are that first interface logic produces; Steering logic read-write Cwr, this signal are exactly the read-write Cwr of article one system bus; Steering logic address bus Caddr, this bus signals provides the offset address of internal control and status register, and this signal is connected on the address bus Caddr of article one system bus; Steering logic write data bus CdataW, this signal are that direct data bus Cdata from article one system bus fetches, and are used for to inner control register value of writing; Output signal has steering logic read data bus CdataR, and this signal is received in the 4th interface logic, is used for the value that central processing unit reads the general asynchronous serial port controller internal register; Data send logic control signal, and the general asynchronous serial port controller inner control logic sends the work of logic by this group signal control data; The Data Receiving logic control signal, the general asynchronous serial port controller inner control logic is by the work of this group signal control data receive logic; The function that data send logic mainly is under the control of inner control logic, preservation writes the outside data that mail to of general asynchronous serial port controller from system data bus, the also string conversion of data is finished in control, passes through serial data output port TxD according to the requirement of frame format, sends to the outside; Input signal has: data register write data enable signal DrWen, this signal are generated by the 3rd interface logic; Data register write data bus DrdataW, this signal are produced by the 3rd interface logic, are inner write data buss; Data send logic control signal, and this signal is to be produced by the universal asynchronous serial inner control logic; Output signal has serial data output port TxD, and general asynchronous serial port controller sends to outside serial data and sends to outside from this port.The major function of Data Receiving logic is under the control of inner control logic, pass through serial data input port RxD sampling external series data according to the requirement of certain frame format, after the string and conversion of data finished in control, be kept in the inner impact damper, wait for that central processing unit or DMA come to read the data that these sample from the outside by data register read data bus DrdataR, the signal of input has: data register is read enable signal DrRen, and this signal comes from the 3rd steering logic; The Data Receiving logic control signal, this signal comes from the universal asynchronous serial inner control logic; Input serial data signal RxD, this signal are the serial data input ends of outside input general asynchronous serial port controller; Output signal is data register read data bus DrdataR.
Because in general asynchronous serial port controller, the read-write of data register has two sources, be central processing unit and DMA, and control and status register have only a source, be exactly central processing unit, so in general asynchronous serial port controller, need the read-write of the read-write inlet of data register and state of a control register inlet is separately controlled.In order to adapt to this needs, the interface section of the general asynchronous serial port controller that the present invention constructed comprises five parts, i.e. first interface logic, second interface logic, the 3rd interface logic, the 4th interface logic and the 5th interface logic: the effect of first interface logic is by chip selection signal Ccs and address signal Caddr from the input of article one system bus, generate inner control logic enable signal Cen, article one system bus data register enable signal 301, article one system bus read-write enable signal 302; These several signals are to produce like this: when the sheet choosing effectively, and address signal is not the address of data register, Cen is effective for the inner control logic enable signal, other situations are invalid; When sheet choosing effectively, and address signal is the address of data register, article one system bus data register enable signal 301 is effective, other situations are invalid; When sheet choosing effectively and be that bus is to read when effective, article one system bus read-write enable signal 302 is effective.The internal logic of the 4th interface logic is one group of alternative selector switch and three-state buffer, two selection signals of its input are respectively steering logic read data bus CdataR and data register read data bus DrdataR, the selecting side is article one system bus data register enable signal 301 that comes from first interface logic, when this Enable Pin when being effective, the data register output bus is strobed into the output terminal of selector switch; When individual Enable Pin when being invalid, the steering logic data-out bus is strobed into the output terminal of selector switch, this output terminal is received the data input pin of three-state buffer, read enable signal when effective when what come from first interface logic, open three-state buffer, be connected on the data bus Cdata, connect otherwise disconnect.The function of second interface logic is similar with first interface logic, and the effect of second interface logic is by chip selection signal Dcs, address signal Daddr, second system bus data register enable signal 303, second system bus read-write enable signal 304 from the input of second system bus; When sheet choosing effectively, and address signal is the address of data register, second system bus data register enable signal 303 is effective, other situations are invalid; When sheet choosing effectively and be that bus is to read when effective, second system bus read-write enable signal 304 is effective, other situations are invalid.The inside of the 5th interface logic is a three-state buffer, and when the second system bus data register enable signal 303 that comes from second interface logic and second system bus read-write enable signal 304 all effectively the time, three-state buffer is open-minded; When this condition was false, three-state buffer disconnected.The input signal of the 3rd interface logic has: the model selection position that the CPUDMA register sends, the data bus Cdata of article one system bus, the data bus Ddata of second system bus, article one system bus data register enable signal 301, second system bus data register enable signal 303, article one system bus read-write Cwr, second system bus read-write Dwr; The signal of output has data register write data bus DrdataW, data register to write enable signal DrWen and data register is read enable signal DrRen.The effect of CPUDMA register is that memory module is selected the position, with the visit of selecting data register is to be finished or DMA finishes by central processing unit, because the read and write of the data device of universal asynchronous register all can change internal state, and be irrecoverable, so prevent the write access unauthorized to the data register, this task is finished in this model selection position: be 0 after resetting, expression is the central processing unit visit, under this set, if DMA visits data register, can not produce actual operation; When this position was set to 1, expression was the DMA access mode, had only DMA to visit data register and just can produce actual effect, if central processing unit visits data register, will can not produce actual operation.But under this set, whether just at the visit data register, central processing unit can visit control register and status register by article one system bus regardless of DMA.When being set to central processor model, the data bus Cdata of article one system bus is connected on the data register write data bus DrdataW, when being set to dma mode, the data bus Ddata of second system bus is connected on the data register write data bus DrdataW.When the read-write Dwr of the read-write Cwr of article one system bus and second system bus is a write operation during at high level, when when low level, being read operation, model selection position in described CPUDMA register is selected under the situation of cpu mode, and the system bus data register enable signal (301) of article one system bus and article one system bus read-write Cwr carry out AND-operation and be connected to data register afterwards and write on the enable signal DrWen; Article one, the inversion signal of the system bus data register enable signal (301) of system bus and article one system bus read-write Cwr carries out being connected to data register after the AND-operation and reads on the enable signal DrRen.Model selection position in described CPUDMA register is selected under the situation of dma mode, and the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carry out AND-operation and be connected to data register afterwards and write on the enable signal DrWen; The inversion signal of the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carries out being connected to data register after the AND-operation and reads on the enable signal DrRen.When the read-write Dwr of the read-write Cwr of article one system bus and second system bus is read operation during at high level, when being write operation when low level, model selection position in described CPUDMA register is selected under the situation of cpu mode, and the inversion signal of the system bus data register enable signal (301) of article one system bus and article one system bus read-write Cwr carries out AND-operation and is connected to data register afterwards and writes on the enable signal DrWen; Article one, the system bus data register enable signal (301) of system bus and article one system bus read-write Cwr carry out being connected to data register after the AND-operation and read on the enable signal DrRen.Model selection position in described CPUDMA register is selected under the situation of dma mode, and the inversion signal of the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carries out AND-operation and is connected to data register afterwards and writes on the enable signal DrWen; The bus data register enable signal (303) of second system bus and second system bus read-write Dwr carry out being connected to data register after the AND-operation and read on the enable signal DrRen.
The course of work is such: the model selection position that is provided with in the CPUDMA register is a central processor model: when central processing unit visits the state of a control register of general asynchronous serial port controller, Cen is effective for the steering logic enable signal, and central processing unit can carry out read and write access to the state of a control register of inside.At this moment article one system bus data register enable signal 301 is invalid, and reading enable signal DrRen and writing enable signal DrWen of data register all can not be effective, even DMA visits data register.So just protected the content of data register can be by the DMA unauthorized access.If the address of central processing unit transmission at this moment is a data register, steering logic enable signal Cen is just invalid, can be to the state of a control register access, at this moment read enable signal DrRen and write enable signal DrWen and can connect the corresponding signal of article one system bus, finish article one system bus to the data operation registers, and can not manage the signal that the second system bus comes; Model selection position in setting the CPUDMA register is direct memory access (DMA) (DMA) pattern: when the address that DMA sends is the state of a control register of general asynchronous serial port controller, because no matter the part of the decoding in second interface logic is the address beyond the data register, so even the address that DMA sends is the address of state of a control register, can not produce actual operation yet, can not influence the state of general asynchronous serial port controller inside.When DMA send be the signal of data register the time, the corresponding enable signal of second interface logic is effective, the corresponding signal of the 5th interface logic is effective, the switch of the 3rd interface logic switches to the direction that connects the second system bus, make the 3rd interface logic data register write data enable signal DrWen, data register write data bus DrdataW and read enable signal DrRen and all produce by the second system bus, and then finish visit to inner data register.If at this moment the central processing unit address of sending is the address of data register, because the switch of the 3rd interface logic all turns to the second system bus here, even, can the data register of inside not exerted an influence so at this moment the central processing unit address of sending is the address of data register yet.When DMA is to the data register access, if central processing unit access control status register, because the control signal data signal is from first interface logic, second interface logic produces, so can not have influence on second interface logic, the 3rd interface logic, the 5th interface logic.This moment is to the data operation registers, so central processing unit can be to the state of a control register access of inside, thereby has realized the concurrency of operation.
Two system buss shown in Figure 4: article one system bus and second system bus, be responsible for each parts of chip internal are linked together; Article one, the main equipment on the system bus has only 1, is exactly central processing unit, and central processing unit is by each parts in article one system bus initialization system; Main equipment on the second system bus is DMA, and it controls the transmission of the data stream of second system bus.Article one, connected a central processing unit on the system bus, central processing unit is controlled the work of coordinating each parts in the chip by article one system bus, and the state of the status register of each parts is provided with control register in the inquiry system; Also has a direct memory access (DMA) parts DMA in the system, be responsible for the data between peripheral hardware and the storer are directly exchanged, exchange without each data all will be interrupted central processing unit, DMA is connecting two system buss, article one, system bus is to be used for central processing unit to come initialization DMA and the state of inquiring about DMA, behind the good DMA of central processing unit initialization, DMA just can finish the exchanges data of storer and general asynchronous serial port controller by the second system bus; Also has a general asynchronous serial port controller in the system, generally speaking, general asynchronous serial port controller has two signal line and chip exterior swap data, article one, be serial data output terminal TxD, article one, be serial data input end RxD, central processing unit or DMA send to the data of chip exterior by general asynchronous serial port controller, in general asynchronous serial port controller, finish and go here and there conversion, sending from the TxD serial of serial data output terminal then, the same serial data of accepting from the outside, to hold the serial input from RxD, data are finished string and conversion in general asynchronous serial port controller inside then, central processing unit or DMA take away from bus again, in the structure that two system buss are arranged, central processing unit can send the data that will send to the outside to the general asynchronous serial port controller data register by article one system bus, also can receive the data that the outside receives general asynchronous serial port controller in central processing unit or the storer by article one system bus.DMA can write the data that will send to the outside to the general asynchronous serial port controller data register by the second system bus, also can receive the Data Receiving of general asynchronous serial port controller to the outside in storer by the second system bus; On the chip internal system bus, also have an interruptable controller to be responsible for accepting the look-at-me of each parts of chip internal, as scheme the look-at-me of DMA, the look-at-me of general asynchronous serial port controller, through behind the priority discrimination, a look-at-me is sent to central processing unit by the look-at-me line that is connected between central processing unit and the interruptable controller; Also connected two storeies on system bus, these two storeies all are connected with two system buss, and one is chip external memory, mainly are bigger program and the data of storage one tittle; One is on-chip memory, mainly is to deposit the instruction and data that some need high speed and central processing unit to exchange; The function of two interfaces of the dual bus interface of general asynchronous serial port controller is distinguishing; An interface is used to central processing unit, central processing unit both can be provided with the internal register of general asynchronous serial port controller by this bus, the state of inquiry internal register, can also write the data that outwards send in the data register of general asynchronous serial port controller by this bus, general asynchronous serial port controller is received the data of coming receive central processing unit inside from the outside, or write in the storer by this bus interface.Another interface is to the DMA special use, the internal register of general asynchronous serial port controller can not be set by this interface and corresponding system bus, can not inquire about the state of internal register, can only by this bus the data that outwards send from memory write to the general asynchronous serial port controller data register, general asynchronous serial port controller is received the data of coming receive the storer from the outside by this bus interface.
The transmission course of whole data with general asynchronous serial port controller of dual bus interface is such: central processing unit is by behind the good DMA of article one system bus initialization, with regard to initializing universal asynchronous serial port controller UART, it is set to central processor model or DMA pattern, there is a bit pattern to select the position in the CPUDMA register of general asynchronous serial port controller UART inside, when being set to central processing unit, the transmission of general asynchronous serial port controller is interrupted and receives interrupting all can sending to interruptable controller, central processing unit is learnt interrupt source by the interrupt status register of inquiry interruptable controller and general asynchronous serial port controller then, finishes corresponding data by article one system bus then and sends and receiving function.When being set to dma mode, the transmission of general asynchronous serial port controller is interrupted and receives interrupting just can not sent to interruptable controller, but directly sends to the corresponding controling end of DMA.When general asynchronous serial port controller sends interruption or receive the condition establishment of interrupting, just send out corresponding transmission interruptive port from interruption to DMA or reception interruptive port, after DMA received corresponding look-at-me, DMA just sent or receives data by the second system bus from general asynchronous serial port controller.When DMA sends or receives data, the work that central processing unit can walk abreast.Like this in the time of DMA and general asynchronous serial port controller swap data, central processing unit can be inquired about the status register of general asynchronous serial port controller simultaneously, or write control register, do not carry out again and need not wait DMA to finish the right to use that obtains system bus after the data transmission.
Claims (12)
1, a kind of general asynchronous serial port controller, comprise that general asynchronous serial port controller inner control logic, data send logic and Data Receiving logic, it is characterized in that, also comprise first interface logic, second interface logic, the 3rd interface logic, the 4th interface logic, the 5th interface logic and the direct access register of central processing unit stores device;
Described first interface logic receives chip selection signal Ccs, read-write Cwr and the address signal Caddr of article one system bus, the inner control logic enable signal Cen that generates sends to described general asynchronous serial port controller inner control logic, article one system bus read-write enable signal (302) that generates sends to described the 4th interface logic, and article one system bus data register enable signal (301) of generation sends to described the 3rd interface logic and the 4th interface logic respectively;
Described the 4th interface logic receives the steering logic read data bus signal CdataR that is sent by the general asynchronous serial port controller inner control logic, and the data register read data bus signal DrdataR that sends by the Data Receiving logic, its selecting side receives the second system bus data register enable signal (303) that sends from described first interface logic, and its output terminal is connected on the data bus Cdata;
Described second interface logic receives chip selection signal Dcs, the address signal Daddr of second system bus of second system bus transmission and the read-write Dwr of second system bus, the second system bus data register enable signal (303) that generates sends to described the 3rd interface logic and the 5th interface logic, and the second system bus read-write enable signal (304) of generation sends to described the 5th interface logic;
Described the 5th interface logic receives second system bus data register enable signal (303) and the second system bus read-write enable signal (304) that described second interface logic sends, receive data bus signal DrdataR from the Data Receiving logic, send it to the data bus Ddata in the second system bus;
It still is the DMA pattern that described the 3rd interface logic is selected to use central processor model by the direct access register control of described central processing unit stores device, receive the data bus Cdata of article one system bus, the data bus Ddata of second system bus, article one, system bus data register enable signal (301), second system bus data register enable signal (303), article one, the read-write Dwr of the read-write Cwr of system bus and second system bus, write enable signal DrWen to described data transmission logic output data register write data bus DrdataW and data register, read enable signal DrRen to described Data Receiving logic transmitting data register;
Described read-write Cwr, address signal Caddr directly are connected with CdataW with corresponding port Cwr, the Caddr of described general asynchronous serial port controller inner control logic respectively with data bus Cdata.
2, general asynchronous serial port controller according to claim 1 is characterized in that, described the 4th interface logic is made of one group of alternative selector switch and three-state buffer.
3, general asynchronous serial port controller according to claim 1 is characterized in that, described the 5th interface logic adopts a three-state buffer.
4, general asynchronous serial port controller according to claim 3 is characterized in that, described three-state buffer when second system bus data register enable signal (303) and second system bus read-write enable signal (304) all open-minded effectively the time.
5, general asynchronous serial port controller according to claim 1 is characterized in that, has only a bit pattern to select the position in the direct access register of described central processing unit stores device, and controlling described the 3rd interface logic selection central processor model still is the DMA pattern.
6, general asynchronous serial port controller according to claim 5, it is characterized in that, controlling described the 3rd interface logic in the direct access register of described central processing unit stores device selects under the situation of DMA pattern, central processing unit can visit control register and status register by article one system bus when DMA visit data register.
9, general asynchronous serial port controller according to claim 1 is characterized in that, the read-write Cwr of article one system bus and the read-write Dwr of second system bus are write operation when high level, are read operation when low level.
10, general asynchronous serial port controller according to claim 9, it is characterized in that, when cpu mode was selected in the model selection position in the described central processing unit direct access access register, the system bus data register enable signal (301) of article one system bus and article one system bus read-write Cwr carried out AND-operation and are connected to data register afterwards and write on the enable signal DrWen; Article one, the inversion signal of the system bus data register enable signal (301) of system bus and article one system bus read-write Cwr carries out being connected to data register after the AND-operation and reads on the enable signal DrRen.
11, general asynchronous serial port controller according to claim 9, it is characterized in that, when dma mode was selected in the model selection position in the direct access register of described central processing unit stores device, the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carried out AND-operation and are connected to data register afterwards and write on the enable signal DrWen; The inversion signal of the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carries out being connected to data register after the AND-operation and reads on the enable signal DrRen.
12, general asynchronous serial port controller according to claim 1 is characterized in that, the read-write Cwr of article one system bus and the read-write Dwr of second system bus are read operation when high level, are write operation when low level.
13, general asynchronous serial port controller according to claim 12, it is characterized in that, when cpu mode was selected in the model selection position in the direct access register of described central processing unit stores device, the inversion signal of the system bus data register enable signal (301) of article one system bus and article one system bus read-write Cwr carried out AND-operation and is connected to data register afterwards and writes on the enable signal DrWen; Article one, the system bus data register enable signal (301) of system bus and article one system bus read-write Cwr carry out being connected to data register after the AND-operation and read on the enable signal DrRen.
14, general asynchronous serial port controller according to claim 12, it is characterized in that, when dma mode was selected in the model selection position in the direct access register of described central processing unit stores device, the inversion signal of the bus data register enable signal (303) of second system bus and second system bus read-write Dwr carried out AND-operation and is connected to data register afterwards and writes on the enable signal DrWen; The bus data register enable signal (303) of second system bus and second system bus read-write Dwr carry out being connected to data register after the AND-operation and read on the enable signal DrRen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01107426 CN1191529C (en) | 2001-01-09 | 2001-01-09 | General asynchronous serial port controller |
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| CN 01107426 CN1191529C (en) | 2001-01-09 | 2001-01-09 | General asynchronous serial port controller |
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| CN1191529C true CN1191529C (en) | 2005-03-02 |
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| CN 01107426 Expired - Fee Related CN1191529C (en) | 2001-01-09 | 2001-01-09 | General asynchronous serial port controller |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1323529C (en) * | 2003-04-28 | 2007-06-27 | 华为技术有限公司 | A method of inner data transmission for digital signal processor |
| CN101763300B (en) * | 2008-12-25 | 2012-03-07 | 佛山市顺德区顺达电脑厂有限公司 | Method for generating SATA (Serial Advanced Technology Attachment) port test signal |
| CN101989244B (en) * | 2009-08-05 | 2013-01-23 | 华为技术有限公司 | Signal conversion device and method as well as communication equipment |
| CN105760335B (en) * | 2016-02-19 | 2018-08-31 | 北京空间飞行器总体设计部 | A kind of spacecraft general-purpose interface controller |
| CN105955764A (en) * | 2016-04-22 | 2016-09-21 | 佛山市南海区欧谱曼迪科技有限责任公司 | Improvement method for STM32 single-chip microcomputer IAP serial program burning |
| CN109933553B (en) * | 2019-02-28 | 2020-09-29 | 厦门码灵半导体技术有限公司 | Control system and design method thereof, group of control systems and electronic device |
| CN114281722B (en) * | 2021-12-29 | 2024-04-05 | 合肥市芯海电子科技有限公司 | Embedded control circuit with double bus interfaces, chip and electronic equipment |
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