CN105095122A

CN105095122A - Method for controlling memory chip, chip controller, and memory controller

Info

Publication number: CN105095122A
Application number: CN201410154996.1A
Authority: CN
Inventors: 肖世海; 杨伟; 赵俊峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-04-17
Filing date: 2014-04-17
Publication date: 2015-11-25
Anticipated expiration: 2034-04-17
Also published as: WO2015158264A1; CN105095122B

Abstract

Embodiments of the invention provide a method for controlling a memory chip, a chip controller, and a memory controller. The chip controller comprises a register module used to store independent chip selection information and a control module used to receive a first chip selection signal output by a memory controller. According to the first chip selection signal and the independent chip selection information stored by the register module, a plurality of independent chip selection signals are generated, wherein the plurality of independent chip selection signals are generated are corresponding to a plurality of memory chips in a one-to-one manner. The first chip selection signal is used to indicate to select the plurality of memory chips. The independent chip selection information is used to indicate to independently select at least a memory chip in the plurality of memory chips. The plurality of independent chip selection signals are respectively output to the plurality of memory chips, so that at least a memory chip in the plurality of memory chips executes operation corresponding to a control command signal according to the control command signal output by the memory controller. . The method for controlling a memory chip, the chip controller, and the memory controller can effectively reduce occupation on transmission bandwidth of a DRAM system.

Description

Control the method for memory chip, chip controller and Memory Controller Hub

Technical field

Embodiments of the invention relate to computer realm, particularly relate to a kind of method, chip controller and the Memory Controller Hub that control memory chip.

Background technology

Computer Architecture has memory system, and the most frequently used storage medium of memory system is dynamic RAM (DynamicRandomAccessMemory, DRAM).The internal memory of computing machine often adopts dual inline memory module (DualInlineMemoryModules, DIMM) form, DIMM(RegisteredDIMM, the RDIMM that can deposit) and low load DIMM(Load-ReducedDIMM, LRDIMM) be two kinds of conventional DIMM forms.RDIMM and LRDIMM from Memory Controller Hub receiver address signal, chip selection signal and clock enable signal, and outputs to each dram chip on DIMM again after registration module is deposited.

The principle of work of common RDIMM is: the dram chip of the narrow bit wide of multi-disc forms the DIMM of wide bit wide.RDIMM has circuit or the chip that is deposited function on DIMM bar, this circuit or chip deposit chip selection signal, the signal such as clock enable signal and address signal that Memory Controller Hub sends to DRAM, and output to each dram chip after again driving.Each dram chip of a RDIMM internal memory synchronously operates.

The DRAM system that a kind of and common RDIMM is similar is had in prior art.A DIMM register is had between the Memory Controller Hub of this DRAM system and dram chip, this register is used for scratch-pad memory controller and sends to the chip selection signal of DIMM, clock enable signal and address signal, and sends to dram chip after again driving these signals.Also have a demoder in this DRAM system, be decoded as sheet choosing for each dram chip and clock enable signal for the chip selection signal for a RANK in whole DIMM that sent by Memory Controller Hub and clock enable signal.The single sheet that DRAM system sends this DRAM order corresponding in the previous cycle of current DRAM order selects information, and chip selection signal and single sheet select information to become multiple independently chip selection signal after decoding, multiple dram chips corresponding in control DIMM respectively.

But Memory Controller Hub each DRAM order needs to send single sheet in the previous cycle of this DRAM order and selects information, seriously occupies the transmission bandwidth of DRAM system.

Summary of the invention

The embodiment provides a kind of method, chip controller and the Memory Controller Hub that control memory chip, effectively can reduce taking the transmission bandwidth of DRAM system.

First aspect, provides a kind of chip controller, comprising: registration module, selects information for depositing single sheet; Control module, for: receive the first chip selection signal that Memory Controller Hub exports; Information is selected to generate multiple independent chip selection signal according to the single sheet that the first chip selection signal and output registration module are deposited, wherein multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, and single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip; Multiple independent chip selection signal is exported, so that the control command signal that at least one memory chip in multiple memory chip exports according to Memory Controller Hub performs the operation corresponding with control command signal respectively to multiple memory chip.

In conjunction with first aspect, in the first possible implementation of first aspect, registration module also for: to select before information generates multiple independent chip selection signal according to the single sheet that the first chip selection signal and registration module are deposited in control module, receive the first address signal that Memory Controller Hub exports, first address signal carries single sheet and selects information and single sheet to select the address information of information, and deposits single sheet according to the first address signal and select information.

In conjunction with the first possible implementation of first aspect, in the implementation that the second of first aspect is possible, first address signal also carrying sheets selects policy information, sheet selects policy information to be deposited with in registration module and selects information corresponding with single sheet, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, control module is also for receiving the control command signal that Memory Controller Hub exports, control module is used for when sheet selects policy information to indicate single sheet to select information pointer effective to control command signal, information is selected to generate multiple independent chip selection signal according to the first chip selection signal and single sheet.

In conjunction with the implementation that the first or the second of first aspect are possible, in the third possible implementation of first aspect, control module is also for selecting policy information to indicate single sheet to select information pointer to control command invalidating signal during at sheet, information is selected to generate multiple independent chip selection signal according to the first chip selection signal and predetermined sheet, multiple memory chips that multiple single sheet that predetermined sheet selects information instruction to generate select signal behavior corresponding.

In conjunction with the first of first aspect to the possible implementation of any one in the third, in the 4th kind of possible implementation of first aspect, the second single sheet that registration module also exports for receiving Memory Controller Hub selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions registration module to deposit single sheet according to the first address signal and selected information.

In conjunction with the first of first aspect and first aspect to any one the possible implementation in the 4th kind, in the 5th kind of possible implementation of first aspect, the first single sheet that control module also exports for receiving Memory Controller Hub selects indicator signal, and wherein the first single sheet selects indicator signal and first to select combined signal to indicate control module to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and registration module.

In conjunction with the first of first aspect and first aspect to any one the possible implementation in the 5th kind, in the 6th kind of possible implementation of first aspect, control module is also for receiving the first clock enable signal that Memory Controller Hub exports, independent clock enable information according to depositing in the first clock enable signal and registration module generates multiple independent clock enable signal, and export multiple independent clock enable signal to multiple memory chip, wherein, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip.

In conjunction with the 6th kind of possible implementation of first aspect, in the 7th kind of possible implementation of first aspect, registration module is also for before chip controller is according to the multiple independent clock enable signal of independent clock enable information generation of depositing in the first clock enable signal and chip controller, receive the second address signal that Memory Controller Hub exports, and deposit independent clock enable information according to the second address signal, wherein, address signal carries the address information of independent clock enable information and independent clock enable information, second address signal carries the address information of independent clock enable information and independent clock enable information.

In conjunction with the 7th kind of possible implementation of first aspect, in the 8th kind of possible implementation of first aspect, second address signal also carries the enable policy information of clock, the enable policy information of clock to be deposited with in chip controller and corresponding with independent clock enable information, whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal, control module is also for receiving the control command signal that Memory Controller Hub exports, control module is used for when the enable policy information of clock indicates independent clock enable information effective, multiple independent clock enable signal is generated according to the first clock enable signal and independent clock enable information.

In conjunction with the 8th kind of possible implementation of first aspect, in the 9th kind of possible implementation of first aspect, control module is also for when the enable policy information of clock indicates independent clock enable information for control command invalidating signal, generate multiple independent clock enable signal according to the first clock enable signal and predetermined clock enable information, the multiple independent clock enable signal that predetermined clock enable information instruction generates selects corresponding multiple memory chips.

In conjunction with the 6th kind of first aspect to any one the possible implementation in the 9th kind, in the tenth kind of possible implementation of first aspect, registration module is also for receiving the second independent clock enable indication and second clock enable signal that Memory Controller Hub exports, and wherein the second independent clock enable indication and second clock enable signal joint instructions control module deposit independent clock enable information according to the second address signal.

In conjunction with the 6th kind of first aspect to any one the possible implementation in the tenth kind, in the 11 kind of possible implementation of first aspect, control module is also for receiving the first clock enable indication that Memory Controller Hub exports, and wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and registration module.

Second aspect, provides a kind of internal memory, comprising: multiple memory chip and the chip controller as any one in claim 1 to 12.

The third aspect provides a kind of Memory Controller Hub, comprising: generation module, and for generating the first chip selection signal, the first single sheet selects indicator signal and control command signal, output module, for exporting the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, single sheet selects information for generating multiple independent chip selection signal, multiple independent chip selection signal and multiple memory chip one_to_one corresponding, during first chip selection signal is used in reference to show select multiple memory chip, single sheet is selected information to be used to indicate and is selected separately the few memory chip of multiple memory chip, wherein, output module is also for exporting control command signal to multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in multiple memory chip exports according to chip controls performs the operation corresponding with control command signal.

In conjunction with the third aspect, in the first possible implementation of the third aspect, output module is also for exporting the first address signal to chip controller, and address signal carries single sheet and selects information and single sheet to select the address information of information.

In conjunction with the first possible implementation of the third aspect, in the implementation that the second of the third aspect is possible, address signal also carrying sheets selects policy information, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, wherein, output module is also for exporting control command signal to chip controller.

In conjunction with the implementation that the first or the second of the third aspect are possible, in the third possible implementation of the third aspect, output module also selects indicator signal and the second chip selection signal for exporting the second single sheet to chip controller, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to address information and selected information.

In conjunction with the first of the third aspect and the third aspect to the possible implementation of any one in the third, in the 4th kind of possible implementation of the third aspect, output module is also for exporting the first clock enable signal and the first independent clock enable indication to chip controller, wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, independent clock enable information is for generating multiple independent clock enable signal, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip.

In conjunction with the 4th kind of possible implementation of the third aspect, in the 5th kind of possible implementation of the third aspect, output module is also for exporting the second address signal to chip controller, and the second address signal carries the address information of independent clock enable information and independent clock enable information.

In conjunction with the 5th kind of possible implementation of the third aspect, in the 6th kind of possible implementation of the third aspect, address signal also carries the enable policy information of clock, and whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal.

In conjunction with the 4th kind of the third aspect to any one the possible implementation in the 6th kind, in the 7th kind of possible implementation of the third aspect, output module is also for exporting the second independent clock enable indication and second clock enable signal to chip controller, and wherein the second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal

Fourth aspect, provides a kind of method controlling internal memory, comprising: chip controller receives the first chip selection signal that Memory Controller Hub exports; Chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, wherein multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, and single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip; Chip controller exports multiple independent chip selection signal respectively to multiple memory chip, so that the control command signal that at least one memory chip in multiple memory chip exports according to Memory Controller Hub performs the operation corresponding with control command signal.

In conjunction with fourth aspect, in the first possible implementation of fourth aspect, before chip controller selects the multiple independent chip selection signal of information generation according to the single sheet of depositing in the first chip selection signal and chip controller, method also comprises: chip controller receives the first address signal that Memory Controller Hub exports, and the first address signal carries single sheet and selects information and single sheet to select the address information of information; Chip controller is deposited single sheet according to the first address signal and is selected information.

In conjunction with the first possible implementation of fourth aspect, in the implementation that the second of fourth aspect is possible, first address signal also carrying sheets selects policy information, sheet selects policy information to be deposited with in chip controller and selects information corresponding with single sheet, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, wherein, the method also comprises: chip controller receives the control command signal that Memory Controller Hub exports, wherein, chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, comprise: as chankings selects policy information to indicate single sheet to select information pointer effective to control command signal, then chip controller selects information to generate multiple independent chip selection signal according to the first chip selection signal and single sheet.

In conjunction with the implementation that the first or the second of fourth aspect and fourth aspect are possible, in the third possible implementation of fourth aspect, the method also comprises: as chankings selects policy information to indicate single sheet to select information pointer to control command invalidating signal, then chip controller selects information to generate multiple independent chip selection signal according to the first chip selection signal and predetermined sheet, multiple memory chips that multiple single sheet that predetermined sheet selects information instruction to generate select signal behavior corresponding.

In conjunction with the first or the third possible implementation of fourth aspect and fourth aspect, in the 4th kind of possible implementation of fourth aspect, the method also comprises: the second single sheet that chip controller receives Memory Controller Hub output selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to the first address signal and selected information.

In conjunction with the first or the 4th kind of possible implementation of fourth aspect and fourth aspect, in the 5th kind of possible implementation of fourth aspect, the method also comprises: the first single sheet that chip controller receives Memory Controller Hub output selects indicator signal, and wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller.

In conjunction with the first or the 5th kind of possible implementation of fourth aspect and fourth aspect, in the 6th kind of possible implementation of fourth aspect, the method also comprises: chip controller receives the first clock enable signal that Memory Controller Hub exports; Chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, and multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip; Chip controller exports multiple independent clock enable signal respectively to multiple memory chip.

In conjunction with the 6th kind of possible implementation of fourth aspect, in the 7th kind of possible implementation of fourth aspect, before chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, also comprise: chip controller receives the second address signal that Memory Controller Hub exports, address signal carries the address information of independent clock enable information and independent clock enable information, and the second address signal carries the address information of independent clock enable information and independent clock enable information; Chip controller deposits independent clock enable information according to the second address signal.

In conjunction with the 7th kind of possible implementation of fourth aspect, in the 8th kind of possible implementation of fourth aspect, second address signal also carries the enable policy information of clock, the enable policy information of clock to be deposited with in chip controller and corresponding with independent clock enable information, whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal, wherein, the method also comprises: chip controller receives the control command signal that Memory Controller Hub exports, wherein chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, comprise:

If the enable policy information of clock indicates independent clock enable information effective, then chip controller generates multiple independent clock enable signal according to the first clock enable signal and independent clock enable information.

In conjunction with the 8th kind of possible implementation of fourth aspect, in the 9th kind of possible implementation of fourth aspect, the method also comprises: if the enable policy information of clock indicates independent clock enable information for control command invalidating signal, then chip controller generates multiple independent clock enable signal according to the first clock enable signal and predetermined clock enable information, and the multiple independent clock enable signal of generation selects corresponding multiple memory chips.

In conjunction with the 6th kind of fourth aspect to any one the possible implementation in the 9th kind, in the tenth kind of possible implementation of fourth aspect, the method also comprises: chip controller receives the second independent clock enable indication and second clock enable signal that Memory Controller Hub exports, and wherein the second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal.

In conjunction with the 6th kind of fourth aspect to any one the possible implementation in the tenth kind, in the 11 kind of possible implementation of fourth aspect, the method also comprises: chip controller receives the first clock enable indication that Memory Controller Hub exports, and wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller.

5th aspect, provide a kind of method controlling memory chip, the method comprises: Memory Controller Hub exports the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, single sheet selects information for generating multiple independent chip selection signal, multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip, Memory Controller Hub exports control command signal to multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in multiple memory chip exports according to chip controls performs the operation corresponding with control command signal.

In conjunction with the 5th aspect, in the first the possible implementation in the 5th, the method also comprises: Memory Controller Hub exports the first address signal to chip controller, and address signal carries single sheet and selects information and single sheet to select the address information of information.

In conjunction with the first possible implementation of the 5th aspect, in the implementation that the second in the 5th is possible, address signal also carrying sheets selects policy information, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, wherein, the method also comprises: Memory Controller Hub exports control command signal to chip controller.

In conjunction with the first implementation possible with the second of the 5th aspect, in the third possible implementation in the 5th, the method also comprises: Memory Controller Hub exports the second single sheet to chip controller and selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to address information and selected information.

In conjunction with the first any one possible implementation to the third of the 5th aspect and the 5th aspect, in the 4th kind of possible implementation in the 5th, the method also comprises: Memory Controller Hub exports the first clock enable signal and the first independent clock enable indication to chip controller, wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, independent clock enable information is for generating multiple independent clock enable signal, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip.

In conjunction with the 4th kind of possible implementation of the 5th aspect, in the 5th kind of possible implementation in the 5th, the method also comprises: Memory Controller Hub exports the second address signal to chip controller, and the second address signal carries the address information of independent clock enable information and independent clock enable information.

In conjunction with the 5th kind of possible implementation of the 5th aspect, in the 6th kind of possible implementation in the 5th, address signal also carries the enable policy information of clock, and whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal.

In conjunction with the 4th kind of the 5th aspect to any one the possible implementation in the 6th kind, in the 7th kind of possible implementation in the 5th, the method also comprises: Memory Controller Hub exports the second independent clock enable indication and second clock enable signal to chip controller, and wherein the second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal.

Therefore, technical scheme of the present invention selects information by depositing single sheet in chip controller, select information to generate multiple independent chip selection signal according to the chip selection signal received from Memory Controller Hub and the single sheet of depositing, and export described multiple independent chip selection signal respectively to described multiple memory chip.Select information owing to having deposited single sheet in chip controller, therefore send single sheet without the need to Memory Controller Hub for each order and select information, thus decrease taking transmission bandwidth.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described to the accompanying drawing used required in the embodiment of the present invention below, apparently, accompanying drawing described is below only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the schematic diagram of memory system according to an embodiment of the invention.

Fig. 2 is the schematic diagram of chip controller according to an embodiment of the invention.

Fig. 3 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.

Fig. 4 is the indicative flowchart of the method for control memory chip according to the embodiment of the present invention.

Fig. 5 A is the schematic diagram of the signal stream of memory system according to an embodiment of the invention.

Fig. 5 B is the schematic diagram of the signal stream of chip controller according to an embodiment of the invention.

Fig. 6 is the indicative flowchart of the control method of chip controller according to an embodiment of the invention.

Fig. 7 is the indicative flowchart of the method for control memory chip according to another embodiment of the present invention.

Fig. 8 is the indicative flowchart of the method for control memory chip according to still another embodiment of the invention.

Fig. 9 is the schematic diagram of chip controller according to an embodiment of the invention.

Figure 10 is the schematic diagram of internal memory according to an embodiment of the invention.

Figure 11 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Fig. 1 is the schematic diagram of the memory system 100 according to the embodiment of the present invention.Memory system 100 comprises Memory Controller Hub 110 and internal memory 120.

Memory Controller Hub 110 is for controlling the exchanges data between internal memory 120 and central processing unit (CentralProcessingUnit, CPU).Internal memory 120 comprises chip controller 121 and multiple memory chip 122.Chip controller 121 between Memory Controller Hub 110 and memory chip 122, for controlling the operation of Memory Controller Hub 110 pairs of memory chips 122.Communicated by communication bus between Memory Controller Hub 110 with internal memory 120.Should be understood that chip controller 121 can also be positioned at outside internal memory, in other words, chip controller 121 can be separated with memory chip 122.Memory Controller Hub 110 can be separated with central processing unit (CPU), also can be incorporated in CPU.

Will also be understood that, the technical scheme of embodiments of the invention can be applied to multiple different memory organization form, such as internal memory 120 can adopt the form of dual inline memory module (DIMM), also other forms can be adopted, such as, also can be that chip controller and processor are on one piece of veneer.Or chip controller is as other forms of subcard or daughter board.

Chip controller 121 is connected with memory chip 122, such as, control command signal and address signal can be made to be input to chip from the side of DIMM, and independent chip selection signal and/or independent clock enable signal can be made to be input to chip from the opposite side of DIMM.However, it should be understood that embodiments of the invention are not limited to this mode.

Interface between chip controller 121 and Memory Controller Hub 110 can transmit address (ADDRESS) signal in Double Data Rate synchronous random access memory (DDR) transmission standard, control command (CMD) signal, sheet choosing (CS) signal and clock enable (CKE) signal etc., in addition, interface between chip controller 121 and Memory Controller Hub 110 can also transmit indicator signal, such as, this indicator signal may be used for registration module and determines that depositing single sheet selects information and independent clock enable information, this indicator signal can also be used for control module and determine to process chip selection signal and clock enable signal.

Memory Controller Hub 110 is connected with central processing unit (CPU) and controls by central processing unit.

Fig. 2 is the schematic diagram of the chip controller 200 according to the embodiment of the present invention.Chip controller 200 is examples of the chip controller 121 of Fig. 1.Chip controller 200 comprises: registration module 210 and control module 220.

Control module 220 for: receive Memory Controller Hub export the first chip selection signal; Information is selected to generate multiple independent chip selection signal according to the single sheet that the first chip selection signal and registration module 210 are deposited, wherein multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, and single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip; Multiple independent chip selection signal is exported, so that the control command signal that at least one memory chip in multiple memory chip exports according to Memory Controller Hub performs the operation corresponding with control command signal respectively to multiple memory chip.

Therefore, technical scheme of the present invention selects information by depositing single sheet in chip controller, select information to generate multiple independent chip selection signal according to chip selection signal and the single sheet of depositing, and export described multiple independent chip selection signal respectively to described multiple memory chip.Select information owing to having deposited single sheet in chip controller, therefore send single sheet without the need to Memory Controller Hub for each order and select information, thus decrease taking transmission bandwidth.

Alternatively, as another embodiment, chip controller 200 can also comprise another registration module, and the signal of wherein control module 220 output gives another registration module.This registration module is used for buffer memory and drive singal again.At signal quality when good and sequential allowance abundance, this registration module can be omitted.

The input signal of chip controller 200 can be CMD, ADDRESS, CS, CKE signal and the indicator signal of Memory Controller Hub output, and output signal can be the independent chip selection signal of each chip corresponding and independent clock enable signal.Each independent chip selection signal performs specific operational order for controlling chip corresponding to this independent chip selection signal.Each independent clock enable signal is in sleep pattern for the chip controlling this independent clock enable signal corresponding.

Should be understood that chip controller can receive the first chip selection signal of Memory Controller Hub output by communication bus.Specifically, first selects signal designation to select all memory chips in memory bar to operate, and such as, write operation or read operation, embodiments of the invention are not limited to this, and such as, operation can also comprise the operations such as activation, precharge or refreshing.In other words, each memory chip receives the first chip selection signal to perform the operation of control command signal designation.Independent chip selection signal and memory chip one_to_one corresponding, single sheet selects signal designation to choose the memory chip of its correspondence to carry out the operation of control command signal designation.

When should also be understood that the memory chip executable operations that single sheet selects signal behavior corresponding with it, can set when independent chip selection signal is high level or low level time effective, embodiments of the invention are not construed as limiting this.

According to embodiments of the invention, registration module also for: to select before information generates multiple independent chip selection signal according to the single sheet that the first chip selection signal and registration module are deposited in control module, receive the first address signal that Memory Controller Hub exports, the first address signal carries single sheet and selects information and single sheet to select the address information of information; Deposit single sheet according to the first address signal and select information.

Should be understood that address signal instruction registration module is deposited single sheet and selected information.Such as, can be registration module deposit single sheet according to the control command signal of instruction registration operations and address signal selects information.Also can be that registration module is deposited single sheet according to address signal and selected information.Should also be understood that and only can send once in the complete operation process of each memory chip, also can send repeatedly.Such as, send before first control command signal of Memory Controller Hub only in the process of the once complete write of data, reading or refresh operation and carry the signal that single sheet selects information, control module is called for the control command signal that memory chip is later the single sheet that registration module deposits in this operation and is selected information.

Information is selected owing to having deposited single sheet, make chip controller can obtain this single sheet when needed and select information, thus chip controller does not need to select information for each control command Signal reception single sheet, saves bandwidth, improves the dirigibility of control chip.

According to embodiments of the invention, first address signal also carrying sheets selects policy information, sheet selects policy information to be deposited with in registration module and selects information corresponding with single sheet, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, control module is also for receiving the control command signal that Memory Controller Hub exports, wherein, control module is used for, when sheet selects policy information to indicate single sheet to select information pointer effective to control command signal, selecting information to generate multiple independent chip selection signal according to the first chip selection signal and single sheet.As chankings selects policy information to indicate single sheet to select information pointer to control command invalidating signal, then control module selects information to generate multiple independent chip selection signal according to the first chip selection signal and predetermined sheet, and predetermined sheet selects information to indicate the multiple independent chip selection signal generated to choose corresponding multiple memory chips.

Specifically, the sheet that information setting can be selected corresponding for single sheet selects policy information.In other words, this sheet selects policy information and single sheet to select information and predetermined control command signal all to there are mapping relations.In this case, control module is when calling the information of depositing in registration module, and Selection and call single sheet does not select information, and the sheet only calling correspondence selects policy information.

Such as, policy information instruction single sheet selects information pointer effective to refresh command, then chip controller is when receiving refresh command, selects information to export independent chip selection signal according to single sheet.Should be understood that control command signal can also be any one in such as write operation command signal, read operation command signal or activation (Activate, ACT) command signal.

Again such as, policy information indicates independent chip selection signal invalid for read command signal, then chip controller selects information to generate according to predetermined sheet and exports multiple independent chip selection signal.Such as, if policy information instruction single sheet selects information pointer invalid to read command, then chip controller is when receiving read command, can not export independent chip selection signal, but exports the first chip selection signal.Should be understood that control command signal can also be any one in act command signal, refresh command signal, write operation signal.Predetermined sheet selects information can be set to acquiescence, specifically, chip controller can be indicated to choose all memory chips.

Owing to have employed policy information, and define different strategies for different control commands, the control command for the independent chip selection signal of unnecessary output is made only to export a chip selection signal, and multiple independent chip selection signal can not be exported, thus decrease the transmission of unnecessary information, improve the utilization factor of bandwidth.

According to embodiments of the invention, the second single sheet that registration module also exports for receiving Memory Controller Hub selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions registration module to deposit single sheet according to the first address signal and selected information.

Should be understood that the first chip selection signal and the second chip selection signal carry identical sheet and select and order.Second chip selection signal instruction is deposited single sheet and is selected information, and first selects signal designation to select information to export independent chip selection signal according to deposited single sheet.Second single sheet is selected indicator signal and the second chip selection signal to be used to indicate chip controller and is deposited single sheet according to the first address signal and select information, such as, chip controller can the second single sheet select indicator signal and the second chip selection signal simultaneously effectively time, deposit the single sheet of carrying in the first address signal and select information.Specifically, when the second single sheet selects indicator signal to be high level, can be defined as effectively, and when the second chip selection signal is low level, the second chip selection signal be defined as effectively.Should be understood that and also when the second single sheet selects indicator signal to be low level, can be defined as effectively, and when the second chip selection signal is high level, the second chip selection signal is defined as effectively.

Due to chip controller can the second single sheet select indicator signal and the second chip selection signal to judge whether depositing single sheet selects information, make when not needing to deposit single sheet and selecting information, chip controller does not carry out the operation of depositing, just forward the signal received, thus enhance the dirigibility that Memory Controller Hub controls chip controller, improve the utilization factor of bandwidth simultaneously.

According to embodiments of the invention, the first single sheet that control module also exports for receiving Memory Controller Hub selects indicator signal, and wherein the first single sheet selects indicator signal and first to select combined signal to indicate control module to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and registration module.

Should be understood that the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller.Select indicator signal similar with the second chip selection signal to the second single sheet, such as, chip controller can the first single sheet select indicator signal and the first chip selection signal simultaneously effectively time, process single sheet selects information, and selects information to generate independent chip selection signal according to single sheet.Specifically, select indicator signal similar to the second single sheet, be defined as when the first single sheet can be selected indicator signal at high level or in low level effectively.Similar to the second chip selection signal, can by the first chip selection signal at high level or in low level time be defined as effectively.

Because chip controller can select indicator signal and the first chip selection signal to judge whether to generate independent chip selection signal according to the first single sheet, chip controller is not operated accordingly when not needing to export independent chip selection signal, thus enhance the dirigibility that Memory Controller Hub controls chip controller, further enhancing the dirigibility of Memory Controller Hub to internal memory chip controls.

According to embodiments of the invention, control module is also for receiving the first clock enable indication that Memory Controller Hub exports, first clock enable signal, first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, registration module is also for receiving the second independent clock enable indication that Memory Controller Hub exports, second clock enable signal and the second address signal, second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal, second address signal carries independent clock enable information, the address information of independent clock enable information.

Should be understood that clock enable signal is similar with chip selection signal, clock enable signal instruction selects multiple memory chip to perform the operation of control command signal designation.Independent chip selection signal is similar to independent clock enable signal, such as, can set independent clock enable signal be high level or low level time as effectively.

Should be understood that address signal instruction registration module deposits independent clock enable information.Such as, can be that registration module deposits independent clock enable information according to the control command signal of instruction registration operations and address signal.Also can be that registration module deposits independent clock enable information according to address signal.

Should also be understood that the signal carrying independent clock enable information only can send once in the complete operation process of each memory chip, also can send repeatedly.Such as, send the signal carrying independent clock enable information before first control command signal of Memory Controller Hub only in the process of the once complete write of data, reading or refresh operation, control module calls for the control command signal that memory chip is later the independent clock enable information that registration module deposits in this operation.

Specifically, can for the enable policy information of clock of independent clock enable information setting correspondence.In other words, all there are mapping relations in the enable policy information of this clock and independent clock enable information and predetermined control command signal.In this case, control module when calling the information of depositing in registration module, the not independent clock enable information of Selection and call, and only call the corresponding enable policy information of clock.

Such as, policy information indicates independent clock enable information effective for act command, then chip controller is when act command, exports independent clock enable signal according to independent clock enable information.Should be understood that control command signal can also be any one in such as write operation command signal, read operation command signal or refresh command signal.

Should be understood that the first clock enable signal and second clock enable signal carry identical clock enable command.Independent clock enable information is deposited in the instruction of second clock enable signal, and the first clock enable signal instruction exports independent clock enable signal according to deposited independent clock enable information.Second independent clock enable indication and second clock enable signal are used to indicate chip controller and deposit independent clock enable information according to the first address signal, such as, chip controller can the second independent clock enable indication and second clock enable signal simultaneously effectively time, deposit independent clock enable information.Specifically, when the second independent clock enable indication is high level, can be defined as effectively, and when second clock enable signal is low level, second clock enable signal be defined as effectively.Should be understood that and also when the second independent clock enable indication is low level, can be defined as effectively, and when second clock enable signal is high level, second clock enable signal be defined as effectively.

Should be understood that the first independent clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller.Also second clock enable signal is similar to the second independent clock enable indication, such as, can chip controller can the first independent clock enable indication and the first clock enable signal simultaneously effectively time, process independent clock enable information, and generate independent clock enable signal according to independent clock enable information.Specifically, similar to the second independent clock enable indication, can by the first independent clock enable indication at high level or in low level time be defined as effectively.Similar to second clock enable signal, can by the first clock enable signal at high level or in low level time be defined as effectively.

Owing to exporting independent clock enable signal for each memory chip, making memory chip when not needing clock signal, not accepting the order of clock signal.Owing to generating independent clock enable signal, thus make chip controller can control chip separately, such as, make specific chip be in sleep pattern, thus reduce the power consumption of chip.

Fig. 3 is the schematic diagram of Memory Controller Hub according to another embodiment of the present invention.This Memory Controller Hub 300 comprises: generation module 310, and for generating the first chip selection signal, the first single sheet selects indicator signal and control command signal, output module 320, for exporting the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, single sheet selects information for generating multiple independent chip selection signal, multiple independent chip selection signal and multiple memory chip one_to_one corresponding, during first chip selection signal is used in reference to show select multiple memory chip, single sheet is selected information to be used to indicate and is selected separately the few memory chip of multiple memory chip, output module is also for exporting control command signal to multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in multiple memory chip exports according to chip controls performs the operation corresponding with control command signal.

According to embodiments of the invention, output module is also for exporting the first address signal to chip controller, and address signal carries single sheet and selects information and single sheet to select the address information of information.

According to embodiments of the invention, address signal also carrying sheets selects policy information, and whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, and wherein, output module is also for exporting control command signal to chip controller.

According to embodiments of the invention, output module also selects indicator signal and the second chip selection signal for exporting the second single sheet to chip controller, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to address information and selected information.

Fig. 4 is the indicative flowchart of the method for the control memory chip of one embodiment of the present of invention.Fig. 5 A is the schematic diagram of the signal stream of memory system according to an embodiment of the invention.Fig. 5 B is the schematic diagram of the signal stream of chip controller according to an embodiment of the invention.

Describe the method described by Fig. 4 below in conjunction with Fig. 5 A and Fig. 5 B, wherein Fig. 5 A shows the method for transmitting signals between Memory Controller Hub, chip controller and memory chip.Fig. 5 B particularly illustrates control module in chip controller for the operation performed by multiple signal.

In this embodiment, for convenience of description, first single sheet selects indicator signal, the second single sheet selects indicator signal, the first independent clock enable indication and the second independent clock enable indication are referred to as indicator signal, first address signal and the second address signal are referred to as address signal, first chip selection signal and the second chip selection signal are referred to as chip selection signal, and the first clock enable signal and second clock enable signal are referred to as clock enable signal.In addition, the present embodiment adopts the DIMM memory bar that dram chip is formed.

410, registration module receives the bus line command signal that Memory Controller Hub exports.

Bus line command signal comprises address signal, control command signal, chip selection signal, clock enable signal and indicator signal.

420, registration module select indicator signal to determine according to the second chip selection signal and the second single sheet depositing single sheet selects information, registration module is determined to deposit independent clock enable information according to second clock enable signal and the second independent clock enable indication.

Such as, time when the second chip selection signal and the second single sheet select indicator signal while effectively, represent that registration module determines that depositing single sheet selects information.When second clock enable signal and the second independent clock enable indication are simultaneously effective, represent that registration module is determined to deposit independent clock enable information.Such as, effective when the second chip selection signal can be made to be predefined for high level, when making the second single sheet select indicator signal and the second independent clock enable indication to be predefined for low level effectively, and effective when making second clock enable signal be predefined for high level.

430, registration module deposits independent chip selection information and independent clock enable information.

Address signal carries single sheet and selects information, separately clock enable information and single sheet to select the address information of the address information of information and independent clock enable information.Single sheet selects information and independent clock enable information to be written in registration module by the address signal in bus and control command signal by Memory Controller Hub.Registration module is divided into again sheet to select registration module and the enable registration module of clock, be respectively used to deposit single sheet and select information and independent clock enable information, such as, table 1 shows the single sheet that registration module deposits and selects information and independent clock enable information to have particular address a0 and a1 respectively.

Table 1

The address of the parameter of depositing	The parameter type deposited
		a0	Single sheet selects information

a1	Independent clock enable information

440, registration module is deposited and is selected the sheet of information to select policy information for single sheet, this sheet select policy information to be used to indicate application strategy that single sheet selects information.Registration module is deposited also for the enable policy information of clock of independent clock enable information, and the enable policy information of this clock is used to indicate the application strategy of independent clock enable information.

Such as, whether this sheet selects policy information pointer to select information effective to act command signal single sheet.Such as, whether this clock strategy information indicating finger is effective to act command signal independent clock enable information.

Such as, sheet can be selected policy information to be defined as policy information for act command, namely when control module receives the signal of act command, determine whether to select information to export independent chip selection signal according to single sheet according to this policy information.Select information to export independent chip selection signal if this policy information still indicates according to single sheet, then control module selects information to export independent chip selection signal according to single sheet.If policy information instruction exports chip selection signal according to predetermined default information, then control module exports chip selection signal according to predetermined default information, such as, default information is set to all independent chip selection signals of instruction and all exports effectively by control module, and ignores single sheet and select information.In other words, similar to chip selection signal, make all independent chip selection signals all indicate corresponding memory chip to carry out execution act command.Other control command as the operational order such as reading order or refresh command and act command similar, do not repeat them here.

Equally, enable for clock policy information can be defined as the policy information for act command, namely when control module receives the signal of act command, determine whether to select information to export independent chip selection signal according to single sheet according to this policy information.Should be understood that in the present embodiment, similar operations is adopted to chip selection signal and clock enable signal, such as, the policy information of independent chip selection signal and independent clock enable signal is defined as same control command, but, also can be defined as the policy information for different control command.

450, control module receives control command signal, chip selection signal, clock enable signal and indicator signal in bus line command signal.

460, control module is determined to process this chip selection signal according to chip selection signal and indicator signal, and determines to process clock enable signal according to clock enable signal and indicator signal.

Control module is used for the information of depositing according to registration module, generates and exports the independent chip selection signal of each dram chip in DIMM memory bar and independent clock enable signal.

As shown in Figure 5, control module 220 comprises sheet and selects control module 221 and clock to make energy control module 222.Registration module 210 comprises sheet and selects registration module 211 and the enable registration module 212 of clock.Registration module 210 comprises sheet and selects registration module 211 and the enable registration module of clock 212 to be respectively used to deposit sheet to select relevant information and the enable relevant information of clock.This sheet selects control module 221 to generate and exports the independent chip selection signal of each dram chip corresponding, and this clock makes energy control module 222 generate and exports the independent clock enable signal of each dram chip corresponding.

470, control module determines to there is policy information.

There is policy information in registration module, therefore control module strategically information judge, should be understood that if there is no policy information, then select information to judge according to single sheet.

480, control module is determined to adopt the policy information for control command signal according to the control command signal received.

Such as, because this act command exists corresponding policy information, and the instruction of this policy information selects information and independent enable information output signal according to single sheet, therefore control module is not select information and predetermined clock enable information to export according to predetermined sheet, but selects information and independent clock enable information to export independent chip selection signal and independent clock enable signal according to single sheet.

490, control module exports independent chip selection signal and independent clock enable signal to memory chip.

Each memory chip receives corresponding independent chip selection signal and independent clock enable signal.Such as, the single sheet of corresponding memory chip selects this chip of signal designation to be in not selected state when write operation order, then, after memory chip receives this signal, do not carry out write operation.

Should be understood that registration module also can not deposit independent clock enable information, correspondingly, control module also can not process clock enable signal, and namely unfavorable clock enable signal generates independent clock enable signal.

Fig. 6 is the process flow diagram of the control method of chip controller according to an embodiment of the invention.In the present embodiment, succinct and convenient in order to describe, only for chip selection signal.Control module to clock enable signal with to the judgement of chip selection signal and the similar of operation, do not repeat them here.Should also be understood that the present embodiment adopts the dram chip of DIMM form, but embodiments of the invention are not limited to this.

610, receive the signal of bus from Memory Controller Hub, comprise address signal, indicator signal, chip selection signal and control command signal.

620, judge whether to process chip selection signal according to chip selection signal and indicator signal.

Specifically, chip selection signal and indicator signal all effectively time, represent that chip controller processes this chip selection signal.In other words, this chip selection signal is the order of the dram chip in the DIMM that controls for this chip controller.Time effective when chip selection signal is different with indicator signal, represent that this chip controller does not do any process to chip selection signal.If the result judged is yes, then perform 640, if the result judged is no, then perform 630.

630, chip selection signal is outputted to memory chip by chip controller, and does not generate and do not export independent chip selection signal, and namely chip selection signal is non-selected state separately.

640, chip controller selects process chip selection signal, and further, by registration module, control module judges whether this control command has corresponding policy information.If the result judged is yes, namely there is predetermined policy information, then perform 660, if the result judged is no, namely there is not predetermined policy information, then perform 650.

650, control module is selected information to generate according to single sheet and is exported independent chip selection signal.

660, control module judges to select information export or select information to export according to predetermined sheet according to single sheet according to policy information.Such as, predetermined sheet selects information can be default information.

670, if policy information instruction selects information to export according to predetermined sheet, such as, according to default information, then control module generates according to default information and exports corresponding signal.Specifically, default information can be set to all independent chip selection signals of instruction and all indicate effectively, and ignore single sheet and select information.In other words, because multiple single sheet selects information all to indicate effectively, the situation that multiple memory chip receives multiple independent chip selection signal is similar to the situation receiving chip selection signal, and all independent chip selection signals all indicate corresponding memory chip to operate, such as, carry out activating or the operation such as refreshing.If policy information instruction exports not in accordance with acquiescence, then control module performs 650, and namely control module is selected information to generate according to single sheet and exported independent chip selection signal.

Fig. 7 is the indicative flowchart of the method for control memory chip according to an embodiment of the invention.The method of Fig. 7 is performed by chip controller, comprises following content.

710, chip controller receives the first chip selection signal that Memory Controller Hub exports.

720, chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, wherein multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, and single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip.

730, chip controller exports multiple independent chip selection signal respectively to multiple memory chip, so that the control command signal that at least one memory chip in multiple memory chip exports according to Memory Controller Hub performs the operation corresponding with control command signal.

Therefore, technical scheme of the present invention selects information by depositing single sheet in chip controller, select information to generate multiple independent chip selection signal according to the chip selection signal received from Memory Controller Hub and the single sheet of depositing, and export multiple independent chip selection signal respectively to multiple memory chip.Select information owing to having deposited single sheet in chip controller, therefore send single sheet without the need to Memory Controller Hub for each order and select information, thus decrease taking transmission bandwidth.

Alternatively, as another embodiment, before chip controller selects the multiple independent chip selection signal of information generation according to the single sheet of depositing in the first chip selection signal and chip controller, the method of Fig. 7 also comprises: chip controller receives the first address signal that Memory Controller Hub exports, and the first address signal carries single sheet and selects information and single sheet to select the address information of information; Chip controller is deposited single sheet according to the first address signal and is selected information.

According to embodiments of the invention, first address signal also carrying sheets selects policy information, sheet selects policy information to be deposited with in chip controller and selects information corresponding with single sheet, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, wherein, method also comprises: chip controller receives the control command signal that Memory Controller Hub exports, wherein, chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, comprise: as chankings selects policy information to indicate single sheet to select information pointer effective to control command signal, then chip controller selects information to generate multiple independent chip selection signal according to the first chip selection signal and single sheet.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: as chankings selects policy information to indicate single sheet to select information pointer to control command invalidating signal, then chip controller selects information to generate multiple independent chip selection signal according to the first chip selection signal and predetermined sheet, multiple memory chips that multiple single sheet that predetermined sheet selects information instruction to generate select signal behavior corresponding.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: the second single sheet that chip controller receives Memory Controller Hub output selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to the first address signal and selected information.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: the first single sheet that chip controller receives Memory Controller Hub output selects indicator signal, and wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller.

Alternatively, as another embodiment, the method for Fig. 7 also comprises: chip controller receives the first clock enable signal that Memory Controller Hub exports; Chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, and multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip; Chip controller exports multiple independent clock enable signal respectively to multiple memory chip.

Alternatively, as another embodiment, before chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, the method of Fig. 7 also comprises: chip controller receives the second address signal that Memory Controller Hub exports, address signal carries the address information of independent clock enable information and independent clock enable information, and the second address signal carries the address information of independent clock enable information and independent clock enable information; Chip controller deposits independent clock enable information according to the second address signal.

According to embodiments of the invention, second address signal also carries the enable policy information of clock, the enable policy information of clock to be deposited with in chip controller and corresponding with independent clock enable information, whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal, wherein, method also comprises: chip controller receives the control command signal that Memory Controller Hub exports, wherein chip controller generates multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, comprise: if the enable policy information of clock indicates independent clock enable information effective, then chip controller generates multiple independent clock enable signal according to the first clock enable signal and independent clock enable information.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: if the enable policy information of clock indicates independent clock enable information for control command invalidating signal, then chip controller generates multiple independent clock enable signal according to the first clock enable signal and predetermined clock enable information, and the multiple independent clock enable signal of generation selects corresponding multiple memory chips.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: chip controller receives the second independent clock enable indication and second clock enable signal that Memory Controller Hub exports, and wherein the second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal.

Alternatively, as another embodiment, the method of Fig. 7 also comprises: chip controller receives the first clock enable indication that Memory Controller Hub exports, and wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller.

Fig. 8 is the indicative flowchart of the method for control memory chip according to another embodiment of the present invention.The method of Fig. 8 is performed by Memory Controller Hub, comprises following content.

810, Memory Controller Hub exports the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, single sheet selects information for generating multiple independent chip selection signal, multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip.

820, Memory Controller Hub exports control command signal to multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in multiple memory chip exports according to chip controls performs the operation corresponding with control command signal.

Alternatively, as another embodiment, the method for Fig. 8 also comprises: Memory Controller Hub exports the first address signal to chip controller, and address signal carries single sheet and selects information and single sheet to select the address information of information.

According to embodiments of the invention, address signal also carrying sheets selects policy information, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, and wherein, method also comprises: Memory Controller Hub exports control command signal to chip controller.

Alternatively, as another embodiment, the method of Fig. 8 also comprises: Memory Controller Hub exports the second single sheet to chip controller and selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to address information and selected information.

Alternatively, as another embodiment, the method of Fig. 8 also comprises: Memory Controller Hub exports the first clock enable signal and the first independent clock enable indication to chip controller, wherein the first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, independent clock enable information is for generating multiple independent clock enable signal, multiple independent clock enable signal and multiple memory chip one_to_one corresponding, first clock enable signal is for controlling the clock signal of multiple memory chip, multiple independent clock enable signal is respectively used to the clock signal controlling separately at least one chip in multiple memory chip.

Alternatively, as another embodiment, the method for Fig. 8 also comprises: Memory Controller Hub exports the second address signal to chip controller, and the second address signal carries the address information of independent clock enable information and independent clock enable information.

According to embodiments of the invention, address signal also carries the enable policy information of clock, and whether the enable policy information of clock is used to indicate independent clock enable information effective for control command signal.

Alternatively, as another embodiment, the method of Fig. 8 also comprises: Memory Controller Hub exports the second independent clock enable indication and second clock enable signal to chip controller, and wherein the second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal.

Fig. 9 is the schematic diagram of chip controller according to an embodiment of the invention.Chip controller 900 comprises: register 910 and controller 920, and register 910 is connected with controller 920, and wherein register 910 selects information for depositing single sheet; Controller 920 for: receive Memory Controller Hub export the first chip selection signal; Information is selected to generate multiple independent chip selection signal according to the single sheet that the first chip selection signal and output register are deposited, wherein multiple independent chip selection signal and multiple memory chip one_to_one corresponding, first chip selection signal is used to indicate selects multiple memory chip, and single sheet selects information to be used to indicate at least one memory chip selected separately in multiple memory chip; Multiple independent chip selection signal is exported, so that the control command signal that at least one memory chip in multiple memory chip exports according to Memory Controller Hub performs the operation corresponding with control command signal respectively to multiple memory chip.

According to embodiments of the invention, register also for: to select before information generates multiple independent chip selection signal according to the single sheet that the first chip selection signal and register are deposited at controller, receive the first address signal that Memory Controller Hub exports, the first address signal carries single sheet and selects information and single sheet to select the address information of information; Deposit single sheet according to the first address signal and select information.

According to embodiments of the invention, first address signal also carrying sheets selects policy information, sheet selects policy information to be deposited with in chip controller and selects information corresponding with single sheet, whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, controller is also for receiving the control command signal that Memory Controller Hub exports, information is selected to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, comprise: as chankings selects policy information to indicate single sheet to select information pointer effective to control command signal, then information is selected to generate multiple independent chip selection signal according to the first chip selection signal and single sheet, as chankings selects policy information to indicate single sheet to select information pointer to control command invalidating signal, then information is selected to generate multiple independent chip selection signal according to the first chip selection signal and predetermined sheet, multiple memory chips that multiple single sheet that predetermined sheet selects information instruction to generate select signal behavior corresponding.

According to embodiments of the invention, the second single sheet that register also exports for receiving Memory Controller Hub selects indicator signal and the second chip selection signal, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to the first address signal and selected information.

According to embodiments of the invention, the first single sheet that controller also exports for receiving Memory Controller Hub selects indicator signal, and wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller.

According to embodiments of the invention, controller is also for receiving the first clock enable indication that Memory Controller Hub exports, first clock enable signal, first clock enable indication and the first clock enable signal joint instructions chip controller generate multiple independent clock enable signal according to the independent clock enable information of depositing in the first clock enable signal and chip controller, register is also for receiving the second independent clock enable indication that Memory Controller Hub exports, second clock enable signal and the second address signal, second independent clock enable indication and second clock enable signal joint instructions chip controller deposit independent clock enable information according to the second address signal, second address signal carries independent clock enable information, the address information of independent clock enable information.

Figure 10 is the schematic diagram of internal memory according to an embodiment of the invention.Internal memory 1000 comprises: multiple memory chip 1010 and the chip controller 900 as Fig. 9.

Figure 11 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.Memory Controller Hub 1100, comprising: processor 1110 and transmitter 1120, and wherein processor 1110 is connected with transmitter 1120, processor 1110 for generating the first chip selection signal, the first single sheet selects indicator signal and control command signal, transmitter 1120, for exporting the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein the first single sheet selects indicator signal and first to select combined signal to indicate chip controller to select information to generate multiple independent chip selection signal according to the single sheet of depositing in the first chip selection signal and chip controller, single sheet selects information for generating multiple independent chip selection signal, multiple independent chip selection signal and multiple memory chip one_to_one corresponding, during first chip selection signal is used in reference to show select multiple memory chip, single sheet is selected information to be used to indicate and is selected separately the few memory chip of multiple memory chip, wherein, transmitter 1120 is also for exporting control command signal to multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in multiple memory chip exports according to chip controls performs the operation corresponding with control command signal.

According to embodiments of the invention, transmitter is also for exporting the first address signal to chip controller, and address signal carries single sheet and selects information and single sheet to select the address information of information.

According to embodiments of the invention, address signal also carrying sheets selects policy information, and whether sheet selects policy information to be used to indicate single sheet to select information pointer effective to control command signal, and wherein, transmitter is also for exporting control command signal to chip controller.

According to embodiments of the invention, transmitter also selects indicator signal and the second chip selection signal for exporting the second single sheet to chip controller, and wherein the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to deposit single sheet according to address information and selected information.

According to embodiments of the invention, transmitter also selects indicator signal and the second chip selection signal for exporting the second single sheet to chip controller, and the second single sheet is selected indicator signal and the second chip selection signal joint instructions chip controller to post according to address information and stated single sheet and select information.

Term "and/or" herein, being only a kind of incidence relation describing affiliated partner, can there are three kinds of relations in expression, and such as, A and/or B, can represent: individualism A, exists A and B simultaneously, these three kinds of situations of individualism B.In addition, character "/" herein, general expression forward-backward correlation is to the relation liking a kind of "or".

Those of ordinary skill in the art can recognize, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.

Those skilled in the art can be well understood to, and for convenience of description and succinctly, the specific works process of the system of foregoing description, device and unit, with reference to the corresponding process in preceding method embodiment, can not repeat them here.

In several embodiments that the application provides, should be understood that disclosed system, apparatus and method can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.In addition, shown or discussed coupling each other or direct-coupling or communication connection can be indirect coupling by some interfaces, device or unit or communication connection, also can be electric, machinery or other form connect.

The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of embodiment of the present invention scheme.

In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, and also can be that the independent physics of unit exists, also can be that two or more unit are in a unit integrated.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form of SFU software functional unit also can be adopted to realize.

Through the above description of the embodiments, those skilled in the art can be well understood to the present invention can use hardware implementing, or firmware realizes, or their array mode realizes.When implemented in software, above-mentioned functions can be stored in computer-readable medium or as the one or more instruction on computer-readable medium or code and transmit.Computer-readable medium comprises computer-readable storage medium and communication media, and wherein communication media comprises any medium being convenient to transmit computer program from a place to another place.Storage medium can be any usable medium that computing machine can access.Be not limited to as example: computer-readable medium can comprise RAM, ROM, EEPROM, CD-ROM or other optical disc storage, magnetic disk storage medium or other magnetic storage apparatus or can be used in carrying or storing the expectation with instruction or data structure form program code and can by any other medium of computer access.In addition.Any connection can be suitable become computer-readable medium.Such as, if software be use concentric cable, optical fiber cable, twisted-pair feeder, Digital Subscriber Line (DSL) or such as infrared ray, radio and microwave and so on wireless technology from website, server or other remote source, so the wireless technology of concentric cable, optical fiber cable, twisted-pair feeder, DSL or such as infrared ray, wireless and microwave and so on be included in affiliated medium fixing in.As used in the present invention, dish (Disk) and dish (disc) comprise compression laser disc (CD), laser dish, laser disc, Digital Versatile Disc (DVD), floppy disk and Blu-ray Disc, the usual magnetic of its mid-game copy data, what dish then carried out optics with laser copies data.Combination above also should be included within the protection domain of computer-readable medium.

In a word, the foregoing is only the preferred embodiment of technical solution of the present invention, be not intended to limit protection scope of the present invention.All within principle of the present invention, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a chip controller, is characterized in that, comprising:

Registration module, selects information for depositing single sheet;

Control module, for: receive the first chip selection signal that Memory Controller Hub exports; Information is selected to generate multiple independent chip selection signal according to the single sheet that described first chip selection signal and described registration module are deposited, wherein said multiple independent chip selection signal and multiple memory chip one_to_one corresponding, described first chip selection signal is used to indicate selects described multiple memory chip, and described single sheet selects information to be used to indicate at least one memory chip selected separately in described multiple memory chip; Described multiple independent chip selection signal is exported, so that the control command signal that at least one memory chip in described multiple memory chip exports according to described Memory Controller Hub performs the operation corresponding with described control command signal respectively to multiple memory chip.

2. method according to claim 1, is characterized in that, described registration module also for: to select before information generates multiple independent chip selection signal according to the single sheet that described first chip selection signal and described registration module are deposited in described control module,

Receive the first address signal that described Memory Controller Hub exports, described first address signal carries described single sheet and selects information and described single sheet to select the address information of information;

Deposit described single sheet according to described first address signal and select information.

3. method according to claim 2, it is characterized in that, described first address signal also carrying sheets selects policy information, described is selected policy information to be deposited with in described chip controller and selects information corresponding with described single sheet, whether described selected policy information to be used to indicate described single sheet to select information pointer effective to described control command signal, described control module is also for receiving the described control command signal that described Memory Controller Hub exports

The described single sheet according to depositing in described first chip selection signal and described chip controller selects information to generate multiple independent chip selection signal, comprising:

If described is selected policy information to indicate described single sheet to select information pointer effective to described control command signal, then information is selected to generate described multiple independent chip selection signal according to described first chip selection signal and described single sheet;

If described is selected policy information to indicate described single sheet to select information pointer to described control command invalidating signal, then information is selected to generate multiple independent chip selection signal according to described first chip selection signal and predetermined sheet, described multiple memory chip that described multiple single sheet that described predetermined sheet selects information instruction to generate selects signal behavior corresponding.

4. according to the method in claim 2 or 3, it is characterized in that, the second single sheet that described registration module also exports for receiving described Memory Controller Hub selects indicator signal and the second chip selection signal, and wherein said second single sheet is selected chip controller described in indicator signal and described second chip selection signal joint instructions to deposit described single sheet according to described first address signal and selected information.

5. the method according to any one in claim 1-4, it is characterized in that, the first single sheet that described control module also exports for receiving described Memory Controller Hub selects indicator signal, and wherein said first single sheet selects indicator signal and described first to select combined signal to indicate described chip controller to select information to generate described multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller.

6. the method according to any one in claim 1-5, is characterized in that,

Described control module is also for receiving the first clock enable indication, the first clock enable signal that described Memory Controller Hub exports, chip controller described in described first clock enable indication and described first clock enable signal joint instructions generates described multiple independent clock enable signal according to the independent clock enable information of depositing in described first clock enable signal and described chip controller

Described registration module is also for receiving the second independent clock enable indication, second clock enable signal and the second address signal that described Memory Controller Hub exports, described in described second independent clock enable indication and described second clock enable signal joint instructions, chip controller deposits described independent clock enable information according to described second address signal, and described second address signal carries the address information of independent clock enable information, described independent clock enable information.

7. an internal memory, is characterized in that, comprising: multiple memory chip and the chip controller as described in any one in claim 1 to 6.

8. a Memory Controller Hub, is characterized in that, comprising:

Generation module, for generating the first chip selection signal, the first single sheet selects indicator signal and control command signal, wherein said first single sheet selects indicator signal and described first to select combined signal to indicate described chip controller to select information to generate described multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller

Output module, for exporting the first chip selection signal to chip controller and the first single sheet selects indicator signal, described single sheet selects information for generating multiple independent chip selection signal, described multiple independent chip selection signal and multiple memory chip one_to_one corresponding, described first chip selection signal is used to indicate selects described multiple memory chip, described single sheet selects information to be used to indicate at least one memory chip selected separately in described multiple memory chip

Described output module is also for exporting control command signal to described multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in described multiple memory chip exports according to described chip controls performs the operation corresponding with described control command signal.

9. method according to claim 8, is characterized in that, described output module is also for exporting the first address signal to described chip controller, and described address signal carries described single sheet and selects information and described single sheet to select the address information of information.

10. method according to claim 9, is characterized in that, described address signal also carrying sheets selects policy information, and whether described selected policy information to be used to indicate described single sheet to select information pointer effective to described control command signal,

Described output module is also for exporting described control command signal to described chip controller.

11. methods according to any one in claim 9-10, is characterized in that,

Described output module also selects indicator signal and the second chip selection signal for exporting the second single sheet to described chip controller, and wherein said second single sheet is selected chip controller described in indicator signal and described second chip selection signal joint instructions to deposit described single sheet according to described address information and selected information.

12. 1 kinds of methods controlling internal memory, is characterized in that, comprising:

Chip controller receives the first chip selection signal that Memory Controller Hub exports;

Described chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller, wherein said multiple independent chip selection signal and multiple memory chip one_to_one corresponding, described first chip selection signal is used to indicate selects described multiple memory chip, and described single sheet selects information to be used to indicate at least one memory chip selected separately in described multiple memory chip;

Described chip controller exports described multiple independent chip selection signal respectively to described multiple memory chip, so that the control command signal that at least one memory chip in described multiple memory chip exports according to described Memory Controller Hub performs the operation corresponding with described control command signal.

13. method according to claim 12, is characterized in that, before described chip controller selects the multiple independent chip selection signal of information generation according to the single sheet of depositing in described first chip selection signal and described chip controller, described method also comprises:

Described chip controller receives the first address signal that described Memory Controller Hub exports, and described first address signal carries described single sheet and selects information and described single sheet to select the address information of information;

Described chip controller is deposited described single sheet according to described first address signal and is selected information.

14. methods according to claim 13, it is characterized in that, described first address signal also carrying sheets selects policy information, described is selected policy information to be deposited with in described chip controller and selects information corresponding with described single sheet, whether described selected policy information to be used to indicate described single sheet to select information pointer effective to described control command signal

Wherein, described method also comprises:

Described chip controller receives the described control command signal that described Memory Controller Hub exports,

Wherein, described chip controller selects information to generate multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller, comprising:

If described is selected policy information to indicate described single sheet to select information pointer effective to described control command signal, then described chip controller selects information to generate described multiple independent chip selection signal according to described first chip selection signal and described single sheet;

If described is selected policy information to indicate described single sheet to select information pointer to described control command invalidating signal, then described chip controller selects information to generate multiple independent chip selection signal according to described first chip selection signal and predetermined sheet, described multiple memory chip that described multiple single sheet that described predetermined sheet selects information instruction to generate selects signal behavior corresponding.

15. methods according to claim 13 or 14, is characterized in that, also comprise:

The second single sheet that described chip controller receives the output of described Memory Controller Hub selects indicator signal and the second chip selection signal, and wherein said second single sheet is selected chip controller described in indicator signal and described second chip selection signal joint instructions to deposit described single sheet according to described first address signal and selected information.

16. methods according to any one in claim 12-15, is characterized in that, also comprise:

The first single sheet that described chip controller receives the output of described Memory Controller Hub selects indicator signal, and wherein said first single sheet selects indicator signal and described first to select combined signal to indicate described chip controller to select information to generate described multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller.

17. methods according to any one in claim 12-16, is characterized in that, also comprise:

Described chip controller receives the first clock enable indication that described Memory Controller Hub exports, first clock enable signal, second independent clock enable indication, second clock enable signal and the second address signal, chip controller described in wherein said first clock enable indication and described first clock enable signal joint instructions generates described multiple independent clock enable signal according to the independent clock enable information of depositing in described first clock enable signal and described chip controller, described in described second independent clock enable indication and described second clock enable signal joint instructions, chip controller deposits described independent clock enable information according to described second address signal, described second address signal carries independent clock enable information, the address information of described independent clock enable information.

18. 1 kinds of methods controlling memory chip, is characterized in that, comprising:

Memory Controller Hub exports the first chip selection signal to chip controller and the first single sheet selects indicator signal, wherein said first single sheet selects indicator signal and described first to select combined signal to indicate described chip controller to select information to generate described multiple independent chip selection signal according to the single sheet of depositing in described first chip selection signal and described chip controller, described single sheet selects information for generating multiple independent chip selection signal, described multiple independent chip selection signal and multiple memory chip one_to_one corresponding, described first chip selection signal is used to indicate selects described multiple memory chip, described single sheet selects information to be used to indicate at least one memory chip selected separately in described multiple memory chip,

Described Memory Controller Hub exports control command signal to described multiple memory chip, so that the multiple independent chip selection signal that at least one memory chip in described multiple memory chip exports according to described chip controls performs the operation corresponding with described control command signal.

19. methods according to claim 18, is characterized in that, also comprise:

Described Memory Controller Hub exports the first address signal to described chip controller, and described address signal carries described single sheet and selects information and described single sheet to select the address information of information.

20. methods according to claim 19, is characterized in that, described address signal also carrying sheets selects policy information, and whether described selected policy information to be used to indicate described single sheet to select information pointer effective to described control command signal,

Described method also comprises: described Memory Controller Hub exports described control command signal to described chip controller.

21. methods according to any one in claim 19-20, is characterized in that, also comprise:

Described Memory Controller Hub exports the second single sheet to described chip controller and selects indicator signal and the second chip selection signal, and wherein said second single sheet is selected chip controller described in indicator signal and described second chip selection signal joint instructions to deposit described single sheet according to described address information and selected information.