CN105095122A - Method for controlling memory chip, chip controller, and memory controller - Google Patents

Abstract

Embodiments of the present invention provide a method for controlling a memory chip, a chip controller and a memory controller. The chip controller includes: a register module for registering individual chip select information; a control module for: receiving the first chip select signal output by the memory controller; according to the first chip select signal and the individual chip select information registered by the register module Generate multiple individual chip selection signals, wherein multiple individual chip selection signals correspond to multiple memory chips one by one, the first chip selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the selection of multiple memory chips At least one memory chip in the chip; output a plurality of individual chip selection signals to the plurality of memory chips, so that at least one memory chip in the plurality of memory chips performs an operation corresponding to the control command signal according to the control command signal output by the memory controller . The embodiments of the present invention can effectively reduce the occupation of the transmission bandwidth of the DRAM system.

Description

Method for controlling memory chip, chip controller and memory controller

technical field

The embodiments of the present invention relate to the computer field, and in particular to a method for controlling a memory chip, a chip controller and a memory controller.

Background technique

The computer architecture has a memory system, and the most commonly used storage medium of the memory system is Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM). Computer memory is often in the form of Dual Inline Memory Modules (DIMMs). Registered DIMMs (RDIMMs) and Load-Reduced DIMMs (LRDIMMs) are two commonly used forms of DIMMs. RDIMM and LRDIMM receive address signal, chip select signal and clock enable signal from the memory controller, and output to each DRAM chip on the DIMM after being registered by the register module.

The working principle of a common RDIMM is as follows: a plurality of narrow-bit-width DRAM chips form a wide-bit-width DIMM. RDIMM has a circuit or chip with a registration function on the DIMM strip. This circuit or chip registers the chip select signal, clock enable signal, address signal and other signals sent by the memory controller to the DRAM, and outputs them to each DRAM chip after being re-driven. . Each DRAM chip of an RDIMM memory operates synchronously.

There is a DRAM system similar to ordinary RDIMM in the prior art. There is a DIMM register between the memory controller of the DRAM system and the DRAM chip, which is used to temporarily store the chip select signal, clock enable signal and address signal sent by the memory controller to the DIMM, and re-drive these signals and send them to DRAM chips. There is also a decoder in the DRAM system, which is used to decode the chip select signal and clock enable signal for a RANK in the entire DIMM sent by the memory controller into chip select and clock enable signals for each DRAM chip. The DRAM system sends the individual chip selection information corresponding to the DRAM command in the previous cycle of the current DRAM command. After decoding, the chip selection signal and the individual chip selection information become multiple independent chip selection signals, which respectively control the corresponding multiple chips in the DIMM. DRAM chips.

However, each DRAM command of the memory controller needs to send a separate chip selection information in the previous cycle of the DRAM command, which seriously occupies the transmission bandwidth of the DRAM system.

Contents of the invention

Embodiments of the present invention provide a method for controlling a memory chip, a chip controller and a memory controller, which can effectively reduce the occupation of the transmission bandwidth of a DRAM system.

In the first aspect, a chip controller is provided, including: a register module for registering individual chip select information; a control module for: receiving the first chip select signal output by the memory controller; according to the first chip select signal and The individual chip selection information registered by the output register module generates multiple individual chip selection signals, wherein the multiple individual chip selection signals correspond to multiple memory chips one by one, the first chip selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection signal The information is used to indicate that at least one memory chip among the plurality of memory chips is individually selected; a plurality of individual chip selection signals are respectively output to the plurality of memory chips, so that at least one memory chip among the plurality of memory chips is output according to a control command output by the memory controller The signal performs the operation corresponding to the control command signal.

With reference to the first aspect, in the first possible implementation of the first aspect, the registration module is further configured to: generate multiple individual chip selection signals at the control module according to the first chip selection signal and the individual chip selection information registered by the registration module Before, the first address signal output by the memory controller is received, the first address signal carries the individual chip selection information and the address information of the individual chip selection information, and the individual chip selection information is registered according to the first address signal.

With reference to the first possible implementation of the first aspect, in the second possible implementation of the first aspect, the first address signal also carries chip selection strategy information, and the chip selection strategy information is registered in the register module and is connected with the separate Corresponding to the chip selection information, the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, and the control module is also used to receive the control command signal output by the memory controller. When the chip selection information is valid for the control command signal, multiple individual chip selection signals are generated according to the first chip selection signal and the individual chip selection information.

With reference to the first or second possible implementation of the first aspect, in a third possible implementation of the first aspect, the control module is further configured to indicate in the chip selection policy information that the individual chip selection information is directed to the control command signal When invalid, multiple individual chip select signals are generated according to the first chip select signal and predetermined chip select information, and the predetermined chip select information indicates that the generated multiple individual chip select signals select corresponding multiple memory chips.

With reference to any one of the first to third possible implementations of the first aspect, in a fourth possible implementation of the first aspect, the registration module is further configured to receive the second independent The chip selection indication signal and the second chip selection signal, wherein the second individual chip selection indication signal and the second chip selection signal jointly instruct the registration module to register the individual chip selection information according to the first address signal.

In combination with the first aspect and any one of the first to fourth possible implementations of the first aspect, in a fifth possible implementation of the first aspect, the control module is further configured to receive the memory controller output The first individual chip selection indication signal, wherein the first individual chip selection indication signal and the first chip selection signal jointly indicate that the control module generates a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information registered in the registration module .

With reference to the first aspect and any one of the first to fifth possible implementations of the first aspect, in a sixth possible implementation of the first aspect, the control module is further configured to receive the memory controller output the first clock enable signal, generate a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the registration module, and output the plurality of individual clock enable signals to a plurality of memory chips, Wherein, a plurality of individual clock enable signals correspond to the plurality of memory chips one by one, the first clock enable signal is used to control the clock signals of the plurality of memory chips, and the plurality of individual clock enable signals are respectively used to individually control the plurality of memory chips A clock signal for at least one of the chips.

With reference to the sixth possible implementation of the first aspect, in the seventh possible implementation of the first aspect, the registering module is further configured to register in the chip controller according to the first clock enable signal and the chip controller Before the individual clock enable information generates multiple individual clock enable signals, the second address signal output by the memory controller is received, and the individual clock enable information is registered according to the second address signal, wherein the address signal carries the individual clock enable information and The address information of the individual clock enabling information, the second address signal carries the individual clock enabling information and the address information of the individual clock enabling information.

With reference to the seventh possible implementation of the first aspect, in the eighth possible implementation of the first aspect, the second address signal also carries clock enabling policy information, and the clock enabling policy information is stored in the chip controller And corresponding to the individual clock enablement information, the clock enablement policy information is used to indicate whether the individual clock enablement information is valid for the control command signal, and the control module is also used to receive the control command signal output by the memory controller, and the control module is used to When the clock enable policy information indicates that the individual clock enable information is valid, multiple individual clock enable signals are generated according to the first clock enable signal and the individual clock enable information.

With reference to the eighth possible implementation of the first aspect, in a ninth possible implementation of the first aspect, the control module is further configured to: when the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal , generating multiple individual clock enable signals according to the first clock enable signal and predetermined clock enable information, where the predetermined clock enable information indicates that the generated multiple individual clock enable signals select corresponding multiple memory chips.

With reference to any one of the sixth to ninth possible implementation manners of the first aspect, in a tenth possible implementation manner of the first aspect, the registration module is further configured to receive the second independent The clock enable indication signal and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the control module to register the individual clock enable information according to the second address signal.

With reference to any one of the sixth to tenth possible implementation manners of the first aspect, in the eleventh possible implementation manner of the first aspect, the control module is further configured to receive the first A clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the registration module can signal.

In a second aspect, a memory is provided, comprising: a plurality of memory chips and the chip controller according to any one of claims 1-12.

The third aspect provides a memory controller, including: a generating module, used to generate a first chip select signal, a first individual chip select indication signal and a control command signal; an output module, used to output the first chip select signal to the chip controller selection signal and the first individual chip selection indication signal, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to generate multiple Single chip selection signal, single chip selection information is used to generate multiple single chip selection signals, multiple single chip selection signals correspond to multiple memory chips one by one, the first chip selection signal is used to select multiple memory chips chip, the individual chip selection information is used to indicate that multiple memory chips are individually selected and one less memory chip is selected, wherein the output module is also used to output control command signals to multiple memory chips, so that at least one memory chip in the multiple memory chips Multiple individual chip select signals that control the output perform operations corresponding to the control command signals.

With reference to the third aspect, in a first possible implementation manner of the third aspect, the output module is further configured to output a first address signal to the chip controller, where the address signal carries individual chip selection information and address information of the individual chip selection information.

With reference to the first possible implementation of the third aspect, in a second possible implementation of the third aspect, the address signal also carries chip selection strategy information, and the chip selection strategy information is used to indicate that the individual chip selection information is for the control command Whether the signal is valid, wherein the output module is also used to output the control command signal to the chip controller.

With reference to the first or second possible implementation of the third aspect, in a third possible implementation of the third aspect, the output module is further configured to output the second individual chip selection indication signal and the first chip selection indication signal to the chip controller. Two chip selection signals, wherein the second individual chip selection indication signal and the second chip selection signal jointly instruct the chip controller to register the individual chip selection information according to the address information.

In combination with the third aspect and any one of the first to third possible implementations of the third aspect, in a fourth possible implementation of the third aspect, the output module is further configured to output to the chip controller The first clock enable signal and the first independent clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to The individual clock enable information generates multiple individual clock enable signals, the individual clock enable information is used to generate multiple individual clock enable signals, the multiple individual clock enable signals correspond to multiple memory chips one by one, the first clock enable The enable signal is used to control the clock signals of multiple memory chips, and the multiple independent clock enable signals are respectively used to independently control the clock signal of at least one of the multiple memory chips.

With reference to the fourth possible implementation of the third aspect, in a fifth possible implementation of the third aspect, the output module is further configured to output a second address signal to the chip controller, and the second address signal carries a separate clock to enable Address information for enable information and individual clock enable information.

With reference to the fifth possible implementation of the third aspect, in a sixth possible implementation of the third aspect, the address signal further carries clock enable policy information, and the clock enable policy information is used to indicate individual clock enable information Whether the control command signal is valid.

In combination with any one of the fourth to sixth possible implementations of the third aspect, in the seventh possible implementation of the third aspect, the output module is further configured to output the second independent clock to the chip controller The enable indication signal and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal

In the fourth aspect, a method for controlling memory is provided, including: the chip controller receives the first chip select signal output by the memory controller; the chip controller receives the first chip select signal and the individual chip select information stored in the chip controller Generate multiple individual chip selection signals, wherein multiple individual chip selection signals correspond to multiple memory chips one by one, the first chip selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the selection of multiple memory chips At least one memory chip in the chip; the chip controller outputs a plurality of individual chip selection signals to the plurality of memory chips, so that at least one memory chip in the plurality of memory chips executes and controls the command signal according to the control command signal output by the memory controller corresponding operation.

With reference to the fourth aspect, in the first possible implementation of the fourth aspect, before the chip controller generates multiple individual chip select signals according to the first chip select signal and the individual chip select information stored in the chip controller, the method It also includes: the chip controller receives the first address signal output by the memory controller, the first address signal carries the individual chip selection information and the address information of the individual chip selection information; the chip controller registers the individual chip selection information according to the first address signal.

With reference to the first possible implementation of the fourth aspect, in the second possible implementation of the fourth aspect, the first address signal also carries chip selection strategy information, and the chip selection strategy information is stored in the chip controller and communicated with Corresponding to the individual chip selection information, the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the method further includes: the chip controller receiving the control command signal output by the memory controller, wherein the chip controller Generate multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information registered in the chip controller, including: if the chip selection strategy information indicates that the individual chip selection information is valid for the control command signal, the chip controller according to the first The chip select signal and the individual chip select information generate a plurality of individual chip select signals.

In combination with the fourth aspect and the first or second possible implementation of the fourth aspect, in the third possible implementation of the fourth aspect, the method further includes: if the chip selection policy information indicates individual chip selection information If the control command signal is invalid, the chip controller generates multiple individual chip select signals according to the first chip select signal and predetermined chip select information, and the predetermined chip select information indicates that the generated multiple individual chip select signals select corresponding multiple memory chip.

In combination with the fourth aspect and the first or third possible implementation manner of the fourth aspect, in a fourth possible implementation manner of the fourth aspect, the method further includes: the chip controller receives the first Two individual chip selection indication signals and a second chip selection signal, wherein the second individual chip selection indication signal and the second chip selection signal jointly instruct the chip controller to register individual chip selection information according to the first address signal.

In combination with the fourth aspect and the first or fourth possible implementation manner of the fourth aspect, in a fifth possible implementation manner of the fourth aspect, the method further includes: the chip controller receives the first An individual chip selection indication signal, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to generate multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information stored in the chip controller .

In combination with the fourth aspect and the first or fifth possible implementation of the fourth aspect, in a sixth possible implementation of the fourth aspect, the method further includes: the chip controller receives the first A clock enable signal; the chip controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the plurality of individual clock enable signals are integrated with the plurality of memory chips One-to-one correspondence, the first clock enable signal is used to control the clock signals of multiple memory chips, and the multiple independent clock enable signals are respectively used to individually control the clock signals of at least one chip in the multiple memory chips; Multiple memory chips output multiple individual clock enable signals.

With reference to the sixth possible implementation of the fourth aspect, in the seventh possible implementation of the fourth aspect, the chip controller according to the first clock enable signal and the individual clock enable information registered in the chip controller Before generating multiple individual clock enable signals, it also includes: the chip controller receives the second address signal output by the memory controller, the address signal carries the individual clock enable information and the address information of the individual clock enable information, and the second address signal carries The individual clock enabling information and the address information of the individual clock enabling information; the chip controller registers the individual clock enabling information according to the second address signal.

With reference to the seventh possible implementation of the fourth aspect, in the eighth possible implementation of the fourth aspect, the second address signal also carries clock enabling policy information, and the clock enabling policy information is stored in the chip controller And corresponding to the individual clock enabling information, the clock enabling policy information is used to indicate whether the individual clock enabling information is valid for the control command signal, wherein the method further includes: the chip controller receives the control command signal output by the memory controller, Wherein the chip controller generates multiple individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, including:

If the clock enable policy information indicates that the individual clock enable information is valid, the chip controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information.

With reference to the eighth possible implementation of the fourth aspect, in a ninth possible implementation of the fourth aspect, the method further includes: if the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal, Then the chip controller generates multiple individual clock enable signals according to the first clock enable signal and predetermined clock enable information, and the generated multiple individual clock enable signals select corresponding multiple memory chips.

With reference to any one of the sixth to ninth possible implementation manners of the fourth aspect, in the tenth possible implementation manner of the fourth aspect, the method further includes: the chip controller receives the output of the memory controller The second individual clock enable indication signal and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal.

With reference to any one of the sixth to tenth possible implementation manners of the fourth aspect, in the eleventh possible implementation manner of the fourth aspect, the method further includes: the chip controller receives the memory controller output The first clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate multiple a separate clock enable signal.

In a fifth aspect, a method for controlling a memory chip is provided, the method comprising: the memory controller outputs a first chip select signal and a first individual chip select indication signal to the chip controller, wherein the first individual chip select indication signal and the second The chip select signal jointly instructs the chip controller to generate multiple individual chip select signals according to the first chip select signal and the individual chip select information stored in the chip controller, and the individual chip select information is used to generate multiple individual chip select signals. The individual chip selection signal corresponds to a plurality of memory chips one by one, the first chip selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the selection of at least one memory chip among the plurality of memory chips; the memory controller Outputting the control command signal to the plurality of memory chips, so that at least one memory chip in the plurality of memory chips performs operations corresponding to the control command signal according to a plurality of individual chip selection signals output by chip control.

With reference to the fifth aspect, in a first possible implementation of the fifth aspect, the method further includes: the memory controller outputs a first address signal to the chip controller, and the address signal carries the individual chip selection information and the information of the individual chip selection information. Address information.

With reference to the first possible implementation of the fifth aspect, in the second possible implementation of the fifth aspect, the address signal also carries chip selection strategy information, and the chip selection strategy information is used to indicate that the individual chip selection information is for the control command Whether the signal is valid, wherein the method further includes: the memory controller outputs a control command signal to the chip controller.

In combination with the first and second possible implementations of the fifth aspect, in a third possible implementation of the fifth aspect, the method further includes: the memory controller outputs a second individual chip selection instruction to the chip controller signal and the second chip selection signal, wherein the second individual chip selection indication signal and the second chip selection signal jointly instruct the chip controller to register the individual chip selection information according to the address information.

In combination with the fifth aspect and any one of the first to third possible implementations of the fifth aspect, in the fourth possible implementation of the fifth aspect, the method further includes: sending the memory controller to the chip control The device outputs the first clock enable signal and the first independent clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly indicate the chip controller according to the first clock enable signal and the chip controller The registered individual clock enable information generates multiple individual clock enable signals, the individual clock enable information is used to generate multiple individual clock enable signals, and the multiple individual clock enable signals correspond to multiple memory chips one by one, the first The clock enable signal is used to control the clock signals of multiple memory chips, and the multiple independent clock enable signals are respectively used to individually control the clock signal of at least one chip of the multiple memory chips.

With reference to the fourth possible implementation of the fifth aspect, in the fifth possible implementation of the fifth aspect, the method further includes: the memory controller outputs a second address signal to the chip controller, and the second address signal carries Individual clock enable information and address information of individual clock enable information.

With reference to the fifth possible implementation of the fifth aspect, in a sixth possible implementation of the fifth aspect, the address signal further carries clock enablement strategy information, and the clock enablement strategy information is used to indicate individual clock enablement information Whether the control command signal is valid.

In combination with any one of the fourth to sixth possible implementations of the fifth aspect, in a seventh possible implementation of the fifth aspect, the method further includes: the memory controller outputs the first Two individual clock enable indication signals and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal.

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to the Multiple memory chips output the multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required in the embodiments of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1 is a schematic structural diagram of a memory system according to an embodiment of the present invention.

FIG. 2 is a schematic structure diagram of a chip controller according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.

FIG. 4 is a schematic flowchart of a method for controlling a memory chip according to an embodiment of the present invention.

FIG. 5A is a schematic diagram of a signal flow of a memory system according to an embodiment of the present invention.

FIG. 5B is a schematic diagram of signal flow of a chip controller according to an embodiment of the present invention.

FIG. 6 is a schematic flowchart of a control method of a chip controller according to an embodiment of the present invention.

FIG. 7 is a schematic flowchart of a method for controlling a memory chip according to another embodiment of the present invention.

FIG. 8 is a schematic flowchart of a method for controlling a memory chip according to yet another embodiment of the present invention.

FIG. 9 is a schematic structure diagram of a chip controller according to an embodiment of the present invention.

FIG. 10 is a schematic structural diagram of a memory according to an embodiment of the present invention.

FIG. 11 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

FIG. 1 is a schematic structural diagram of a memory system 100 according to an embodiment of the present invention. The memory system 100 includes a memory controller 110 and a memory 120 .

The memory controller 110 is used for controlling data exchange between the memory 120 and a central processing unit (Central Processing Unit, CPU). The memory 120 includes a chip controller 121 and a plurality of memory chips 122 . The chip controller 121 is located between the memory controller 110 and the memory chip 122 and is used for controlling the operation of the memory controller 110 on the memory chip 122 . The memory controller 110 communicates with the memory 120 through a communication bus. It should be understood that the chip controller 121 may also be located outside the memory, in other words, the chip controller 121 and the memory chip 122 may be separated. The memory controller 110 may be separated from the central processing unit (CPU), or may be integrated into the CPU.

It should also be understood that the technical solutions of the embodiments of the present invention can be applied to various memory organization forms, for example, the memory 120 can be in the form of a dual in-line memory module (DIMM), and can also be in other forms, for example, also It may be that the chip controller and the processor are on a single board. Or chip controllers as other forms of daughter cards or boards.

The chip controller 121 is connected with the memory chip 122, for example, control command signals and address signals can be input into the chip from one side of the DIMM, and an independent chip select signal and/or an independent clock enable signal can be input from the other side of the DIMM. side input into the chip. However, it should be understood that embodiments of the present invention are not limited in this manner.

The interface between the chip controller 121 and the memory controller 110 can transmit the address (ADDRESS) signal, the control command (CMD) signal, the chip select (CS) signal and the clock enable in the double rate synchronous random access memory (DDR) transmission standard. In addition, the interface between the chip controller 121 and the memory controller 110 can also transmit an indication signal, for example, this indication signal can be used for the registration module to determine the registration of individual chip selection information and Separate clock enable information, this indication signal can also be used by the control module to determine the processing of the chip select signal and the clock enable signal.

The memory controller 110 is connected to and controlled by a central processing unit (CPU).

FIG. 2 is a schematic structural diagram of a chip controller 200 according to an embodiment of the present invention. The chip controller 200 is an example of the chip controller 121 of FIG. 1 . The chip controller 200 includes: a register module 210 and a control module 220 .

The control module 220 is used to: receive the first chip selection signal output by the memory controller; generate a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information registered by the registration module 210, wherein the plurality of individual chip selection signals and Multiple memory chips correspond one-to-one, the first chip selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the selection of at least one memory chip among the multiple memory chips; An individual chip select signal, so that at least one memory chip among the plurality of memory chips performs an operation corresponding to the control command signal according to the control command signal output by the memory controller.

Therefore, the technical solution of the present invention registers individual chip selection information in the chip controller, generates multiple individual chip selection signals according to the chip selection signal and the registered individual chip selection information, and outputs the described Multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

Optionally, as another embodiment, the chip controller 200 may further include another registration module, wherein the signal output by the control module 220 is sent to another registration module. This register block is used to buffer and redrive signals. In the case of good signal quality and sufficient timing margin, the register module can be omitted.

The input signals of the chip controller 200 may be CMD, ADDRESS, CS, CKE signals and indication signals output by the memory controller, and the output signals may be individual chip select signals and individual clock enable signals corresponding to each chip. Each individual chip select signal is used to control the chip corresponding to the individual chip select signal to execute a specific operation command. Each individual clock enable signal is used to control the chip corresponding to the individual clock enable signal to be in sleep mode.

It should be understood that the chip controller may receive the first chip select signal output by the memory controller through the communication bus. Specifically, the first chip select signal indicates to select all the memory chips in the memory bank to perform operations, such as a write operation or a read operation. Embodiments of the present invention are not limited thereto. For example, the operations may also include activation, Operations such as pre-charging or refreshing. In other words, each memory chip receives the first chip select signal to perform the operation indicated by the control command signal. The individual chip selection signal corresponds to the memory chips one by one, and the individual chip selection signal indicates that the corresponding memory chip is selected to perform the operation indicated by the control command signal.

It should also be understood that when the individual chip select signal selects its corresponding memory chip to perform an operation, the individual chip select signal can be set to be valid when it is at a high level or at a low level, which is not limited in this embodiment of the present invention.

According to an embodiment of the present invention, the registration module is further configured to: receive the first address signal output by the memory controller before the control module generates a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information registered by the registration module , the first address signal carries the individual chip selection information and the address information of the individual chip selection information; the individual chip selection information is registered according to the first address signal.

It should be understood that the address signal instructs the registration module to register individual chip selection information. For example, the registration module may register the individual chip selection information according to the control command signal and the address signal indicating the registration operation. Alternatively, the registering module registers individual chip selection information according to the address signal. It should also be understood that it may be sent only once during each complete operation of the memory chip, or may be sent multiple times. For example, the memory controller only sends a signal carrying individual chip selection information before the first control command signal in the process of a complete write, read or refresh operation of data. The command signal invokes the individual chip select information registered by the register module.

Since the individual chip selection information is stored, the chip controller can obtain the individual chip selection information when needed, so that the chip controller does not need to receive individual chip selection information for each control command signal, which saves bandwidth and improves the efficiency of the control chip. flexibility.

According to an embodiment of the present invention, the first address signal also carries chip selection strategy information, the chip selection strategy information is registered in the registration module and corresponds to the individual chip selection information, and the chip selection strategy information is used to indicate that the individual chip selection information is for the control command Whether the signal is valid, the control module is also used for receiving the control command signal output by the memory controller, wherein the control module is used for when the chip selection policy information indicates that the individual chip selection information is valid for the control command signal, according to the first chip selection signal and the individual Chip select information generates multiple individual chip select signals. If the chip selection strategy information indicates that the individual chip selection information is invalid for the control command signal, the control module generates a plurality of individual chip selection signals according to the first chip selection signal and predetermined chip selection information, and the predetermined chip selection information indicates the plurality of individual chip selection signals generated. The chip select signal selects corresponding multiple memory chips.

Specifically, corresponding chip selection policy information may be set for individual chip selection information. In other words, there is a mapping relationship between the chip selection policy information and individual chip selection information and predetermined control command signals. In this case, when the control module calls the information registered in the registration module, it does not choose to call individual chip selection information, but only calls the corresponding chip selection strategy information.

For example, the policy information indicates that the individual chip selection information is valid for the refresh command, and the chip controller outputs the individual chip selection signal according to the individual chip selection information when the refresh command is received. It should be understood that the control command signal may also be any one of a write operation command signal, a read operation command signal, or an activate (Activate, ACT) command signal.

For another example, if the policy information indicates that the individual chip select signal is invalid for the read command signal, the chip controller generates and outputs multiple individual chip select signals according to predetermined chip select information. For example, if the policy information indicates that the individual chip select information is invalid for the read command, the chip controller will not output the individual chip select signal but the first chip select signal when receiving the read command. It should be understood that the control command signal may also be any one of an ACT command signal, a refresh command signal, and a write operation signal. The predetermined chip selection information can be set as a default, specifically, the chip controller can be instructed to select all memory chips.

Due to the use of strategy information and the definition of different strategies for different control commands, only one chip selection signal is output for control commands that do not need to output a single chip selection signal, and multiple individual chip selection signals are not output, thereby reducing The transmission of unnecessary information is avoided, and the utilization rate of bandwidth is improved.

According to an embodiment of the present invention, the registration module is also used to receive the second independent chip selection indication signal and the second chip selection signal output by the memory controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate the registration module Individual chip select information is registered according to the first address signal.

It should be understood that the first chip select signal and the second chip select signal carry the same chip select command. The second chip selection signal indicates to register individual chip selection information, and the first chip selection signal indicates to output an individual chip selection signal according to the registered individual chip selection information. The second individual chip selection indication signal and the second chip selection signal are used to instruct the chip controller to register individual chip selection information according to the first address signal. When both are valid, the individual chip selection information carried in the first address signal is registered. Specifically, when the second individual chip select indication signal is at a high level, it can be determined to be valid, and when the second chip select signal is at a low level, the second chip select signal can be determined to be valid. It should be understood that the second individual chip select indication signal may also be determined to be valid when the second individual chip select indication signal is at a low level, and the second chip select signal may be determined to be valid when the second chip select signal is at a high level.

Since the chip controller can judge whether to register the individual chip selection information by the second individual chip selection indication signal and the second chip selection signal, when the individual chip selection information does not need to be registered, the chip controller does not perform the registration operation, but only forwards and receives signal, thereby enhancing the flexibility of the memory controller to control the chip controller, and at the same time improving the utilization rate of the bandwidth.

According to an embodiment of the present invention, the control module is also used to receive the first individual chip selection indication signal output by the memory controller, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the control module to and the individual chip selection information registered in the registration module to generate a plurality of individual chip selection signals.

It should be understood that the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to generate multiple individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller. Similar to the second individual chip selection indication signal and the second chip selection signal, for example, the chip controller can process the individual chip selection information when the first individual chip selection indication signal and the first chip selection signal are valid at the same time, and Select information to generate a separate chip select signal. Specifically, similar to the second individual chip selection indication signal, the first individual chip selection indication signal may be determined to be valid when it is at a high level or at a low level. Similar to the second chip select signal, the first chip select signal can be determined to be valid when it is at a high level or at a low level.

Since the chip controller can judge whether to generate a single chip selection signal according to the first single chip selection indication signal and the first chip selection signal, the chip controller does not perform corresponding operations when it is not necessary to output a single chip selection signal, thereby enhancing memory The flexibility of the controller to control the chip controller further enhances the flexibility of the memory controller to control the memory chip.

According to an embodiment of the present invention, the control module is also used to receive the first clock enable indication signal and the first clock enable signal output by the memory controller, and the first clock enable indication signal and the first clock enable signal jointly indicate the chip The controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the registration module is also used to receive the second individual clock enable indication signal output by the memory controller, The second clock enable signal and the second address signal, the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal, and the second address signal carries the individual clock enable information Clock enable information, address information of individual clock enable information.

It should be understood that the clock enable signal is similar to the chip select signal, and the clock enable signal indicates that multiple memory chips are selected to perform the operation indicated by the control command signal. The individual chip select signal is similar to the individual clock enable signal, for example, the individual clock enable signal can be set to be valid when it is high or low.

It should be understood that the address signal instructs the registration module to register individual clock enable information. For example, the registration module may register individual clock enable information according to a control command signal and an address signal indicating a registration operation. Alternatively, the register module registers individual clock enable information according to the address signal.

It should also be understood that the signal carrying individual clock enable information may be sent only once during each complete operation of the memory chip, or may be sent multiple times. For example, the memory controller only sends a signal carrying separate clock enable information before the first control command signal in a complete write, read or refresh operation of data. The control command signal invokes individual clock enable information registered by the register module.

Specifically, corresponding clock enabling policy information may be set for individual clock enabling information. In other words, there is a mapping relationship between the clock enabling policy information and the individual clock enabling information and predetermined control command signals. In this case, when the control module calls the information registered in the registration module, it does not choose to call individual clock enabling information, but only calls corresponding clock enabling policy information.

For example, if the policy information indicates that the individual clock enabling information is valid for the ACT command, the chip controller outputs the individual clock enabling signal according to the individual clock enabling information in the case of the ACT command. It should be understood that the control command signal may also be any one of a write operation command signal, a read operation command signal or a refresh command signal.

It should be understood that the first clock enable signal and the second clock enable signal carry the same clock enable command. The second clock enable signal indicates to register individual clock enable information, and the first clock enable signal indicates to output an individual clock enable signal according to the registered individual clock enable information. The second individual clock enable indication signal and the second clock enable signal are used to instruct the chip controller to register the individual clock enable information according to the first address signal. When the two clock enable signals are valid at the same time, the independent clock enable information is registered. Specifically, when the second individual clock enable indication signal is at a high level, it may be determined to be valid, and when the second clock enable signal is at a low level, the second clock enable signal may be determined to be valid. It should be understood that the second independent clock enable indication signal may also be determined to be valid when the second independent clock enable indication signal is at a low level, and the second clock enable signal may be determined to be valid when the second clock enable signal is at a high level.

It should be understood that the first individual clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate multiple individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller . Similar to the second individual clock enable indication signal and the second clock enable signal, for example, the chip controller can process the individual clock enable indication signal and the first clock enable signal when the first individual clock enable indication signal and the first clock enable signal are valid at the same time. enable information, and generate an individual clock enable signal based on the individual clock enable information. Specifically, similar to the second individual clock enable indication signal, the first individual clock enable indication signal may be determined to be valid when it is at a high level or at a low level. Similar to the second clock enable signal, the first clock enable signal can be determined to be valid when it is at a high level or at a low level.

Since an individual clock enable signal is output for each memory chip, the memory chip does not accept the command of the clock signal when the clock signal is not needed. Since the independent clock enable signal is generated, the chip controller can independently control the chip, for example, put a specific chip in a sleep mode, thereby reducing the power consumption of the chip.

FIG. 3 is a schematic structural diagram of a memory controller according to another embodiment of the present invention. The memory controller 300 includes: a generating module 310 for generating a first chip select signal, a first separate chip select indication signal and a control command signal; an output module 320 for outputting the first chip select signal and the second chip select signal to the chip controller An individual chip selection indication signal, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to generate multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information stored in the chip controller , the individual chip selection information is used to generate multiple individual chip selection signals, and the multiple individual chip selection signals correspond to multiple memory chips one by one. The selection information is used to indicate that multiple memory chips are individually selected and one less memory chip is selected; the output module is also used to output control command signals to multiple memory chips, so that at least one memory chip in the multiple memory chips outputs multiple individual memory chips according to the chip control. The chip select signal performs the operation corresponding to the control command signal.

Therefore, the technical solution of the present invention registers individual chip selection information in the chip controller, generates multiple individual chip selection signals according to the chip selection signal and the registered individual chip selection information, and outputs the described Multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

According to an embodiment of the present invention, the output module is further configured to output the first address signal to the chip controller, and the address signal carries the individual chip selection information and the address information of the individual chip selection information.

According to an embodiment of the present invention, the address signal also carries chip selection policy information, and the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the output module is also used to output the control command signal to the chip controller.

According to an embodiment of the present invention, the output module is also used to output a second individual chip selection indication signal and a second chip selection signal to the chip controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate the chip controller Register individual chip selection information based on address information.

FIG. 4 is a schematic flowchart of a method for controlling a memory chip according to an embodiment of the present invention. FIG. 5A is a schematic diagram of a signal flow of a memory system according to an embodiment of the present invention. FIG. 5B is a schematic diagram of signal flow of a chip controller according to an embodiment of the present invention.

The method described in FIG. 4 will be described below in conjunction with FIG. 5A and FIG. 5B , wherein FIG. 5A shows a signal transmission method among the memory controller, the chip controller, and the memory chip. FIG. 5B specifically shows the operations performed by the control module in the chip controller for multiple signals.

In this embodiment, for convenience of description, the first individual chip selection indication signal, the second individual chip selection indication signal, the first individual clock enable indication signal and the second individual clock enable indication signal are collectively referred to as indication signals, and the first The address signal and the second address signal are collectively referred to as address signals, the first chip select signal and the second chip select signal are collectively referred to as chip select signals, and the first clock enable signal and the second clock enable signal are collectively referred to as clock enable signals. In addition, this embodiment adopts a DIMM memory bar formed by DRAM chips.

410. The registration module receives the bus command signal output by the memory controller.

The bus command signals include address signals, control command signals, chip select signals, clock enable signals and indication signals.

420. The register module determines to register individual chip select information according to the second chip select signal and the second individual chip select indication signal, and the register module determines to register individual clock enable information according to the second clock enable signal and the second individual clock enable indication signal .

For example, when the second chip select signal and the second individual chip select indication signal are valid at the same time, it means that the registration module determines to register the individual chip select information. When the second clock enable signal and the second independent clock enable indication signal are valid at the same time, it indicates that the registration module determines to register the individual clock enable information. For example, it is possible to make the second chip select signal valid when it is predetermined to be high, make the second individual chip select indication signal and the second individual clock enable indication signal active when it is predetermined to be low, and make the second clock enable signal predetermined to be Valid when high level.

430. The register module registers individual chip selection information and individual clock enable information.

The address signal carries individual chip select information, individual clock enable information, and address information of the individual chip select information and address information of the individual clock enable information. The memory controller writes the individual chip selection information and the individual clock enabling information into the register module through the address signal and the control command signal in the bus. The register module is further divided into a chip select register module and a clock enable register module, which are respectively used to register individual chip select information and individual clock enable information. For example, Table 1 shows the individual chip select information and individual clock information registered by the register module. The enable information has specific addresses a0 and a1, respectively.

Table 1

The address of the registered parameter Registered parameter type a0 Individual Chip Select Information

a1 Individual clock enable information

440. The registration module registers chip selection policy information for the individual chip selection information, where the chip selection policy information is used to indicate an application policy of the individual chip selection information. The registration module also registers clock enable policy information for the individual clock enable information, where the clock enable policy information is used to indicate an application policy of the individual clock enable information.

For example, the chip selection policy information indicates whether individual chip selection information is valid for the ACT command signal. For example, the clock policy information indicates whether individual clock enable information is valid for the ACT command signal.

For example, the chip selection policy information can be defined as policy information for the ACT command, that is, when the control module receives the signal of the ACT command, it determines whether to output the individual chip selection signal according to the individual chip selection information according to the policy information. If the policy information still indicates to output the individual chip selection signal according to the individual chip selection information, the control module outputs the individual chip selection signal according to the individual chip selection information. If the policy information indicates that the chip select signal is output according to the predetermined default information, the control module outputs the chip select signal according to the predetermined default information, for example, the control module sets the default information to indicate that all individual chip select signals are output valid, and ignore the Select information. In other words, similar to the chip select signal, all individual chip select signals instruct the corresponding memory chip to execute the ACT command. Operation commands such as other control commands such as a read command or a refresh command are similar to the ACT command and will not be repeated here.

Similarly, the clock enabling policy information can be defined as policy information for the ACT command, that is, when the control module receives the signal of the ACT command, it determines whether to output the individual chip selection signal according to the individual chip selection information according to the policy information. It should be understood that, in this embodiment, similar operations are adopted for the chip select signal and the clock enable signal, for example, the definition of policy information for the individual chip select signal and the individual clock enable signal is for the same control command, however, it may also be Define it as policy information for different control commands.

450. The control module receives a control command signal, a chip select signal, a clock enable signal, and an indication signal in the bus command signal.

460. The control module determines to process the chip select signal according to the chip select signal and the indication signal, and determines to process the clock enable signal according to the clock enable signal and the indication signal.

The control module is used for generating and outputting an individual chip select signal and an individual clock enable signal of each DRAM chip in the DIMM according to the information registered by the register module.

As shown in FIG. 5 , the control module 220 includes a chip select control module 221 and a clock enable control module 222 . The register module 210 includes a chip select register module 211 and a clock enable register module 212 . The register module 210 includes a chip select register module 211 and a clock enable register module 212 for registering chip select related information and clock enable related information respectively. The chip select control module 221 generates and outputs an individual chip select signal corresponding to each DRAM chip, and the clock enable control module 222 generates and outputs an individual clock enable signal corresponding to each DRAM chip.

470. The control module determines that policy information exists.

There is policy information in the registration module, so the control module judges according to the policy information. It should be understood that if there is no policy information, it judges according to the individual chip selection information.

480. The control module determines to adopt policy information for the control command signal according to the received control command signal.

For example, because the ACT command has corresponding policy information, and the policy information indicates that the signal is output according to the individual chip selection information and the individual enabling information, the control module is not outputting according to the predetermined chip selection information and the predetermined clock enabling information, but Outputting an individual chip select signal and an individual clock enable signal according to the individual chip select information and the individual clock enable information.

490. The control module outputs an individual chip selection signal and an individual clock enable signal to the memory chip.

Each memory chip receives a corresponding individual chip select signal and an individual clock enable signal. For example, an individual chip select signal corresponding to a memory chip indicates that the chip is in an unselected state in the case of a write operation command, and the memory chip does not perform a write operation after receiving the signal.

It should be understood that the register module may not register the individual clock enable information, and correspondingly, the control module may not process the clock enable signal, that is, the clock enable signal is not used to generate the individual clock enable signal.

FIG. 6 is a flowchart of a control method of a chip controller according to an embodiment of the present invention. In this embodiment, for simplicity and convenience of description, only the chip select signal is taken as an example. The judgment and operation of the clock enable signal and the chip select signal by the control module are similar, and will not be repeated here. It should also be understood that the present embodiment uses DRAM chips in the form of DIMMs, but the embodiments of the present invention are not limited thereto.

610. Receive bus signals from the memory controller, including address signals, indication signals, chip select signals, and control command signals.

620. Determine whether to process the chip select signal according to the chip select signal and the indication signal.

Specifically, when both the chip selection signal and the indication signal are valid, it means that the chip controller processes the chip selection signal. In other words, the chip select signal is a command for the DRAM chips in the DIMM controlled by the chip controller. When the chip selection signal and the indication signal are not valid at the same time, it means that the chip controller does not perform any processing on the chip selection signal. If the result of the judgment is yes, go to 640 ; if the result of the judgment is no, go to 630 .

630. The chip controller outputs the chip select signal to the memory chip without generating and outputting the individual chip select signal, that is, the individual chip select signal is in a non-selected state.

640. The chip controller selects and processes the chip select signal. Further, the control module judges whether the control command has corresponding policy information through the register module. If the judgment result is yes, that is, there is predetermined policy information, go to 660 ; if the judgment result is no, that is, there is no predetermined policy information, go to 650 .

650. The control module generates and outputs an individual chip selection signal according to the individual chip selection information.

660. The control module judges according to the policy information to output according to individual chip selection information or to output according to predetermined chip selection information. For example, predetermined chip selection information may be default information.

670. If the policy information indicates to output according to predetermined chip selection information, for example, according to default information, the control module generates and outputs a corresponding signal according to the default information. Specifically, the default information may be set to indicate that all individual chip selection signals are valid, and the individual chip selection information is ignored. In other words, since multiple individual chip selection information indicates that they are valid, the situation that multiple memory chips receive multiple individual chip selection signals is similar to the situation of receiving chip selection signals, and all individual chip selection signals indicate that the corresponding memory chip Perform operations such as activation or refresh. If the policy information indicates not to output by default, the control module executes 650, that is, the control module generates and outputs an individual chip selection signal according to the individual chip selection information.

FIG. 7 is a schematic flowchart of a method for controlling a memory chip according to an embodiment of the present invention. The method in FIG. 7 is executed by the chip controller, and includes the following contents.

710. The chip controller receives the first chip select signal output by the memory controller.

720. The chip controller generates multiple individual chip select signals according to the first chip select signal and the individual chip select information stored in the chip controller, wherein the multiple individual chip select signals correspond to multiple memory chips one by one, and the first chip select signal The signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the individual selection of at least one memory chip among the multiple memory chips.

730. The chip controller outputs multiple individual chip select signals to multiple memory chips, so that at least one memory chip among the multiple memory chips performs an operation corresponding to the control command signal according to the control command signal output by the memory controller.

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to multiple The memory chip outputs multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

Optionally, as another embodiment, before the chip controller generates multiple individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, the method in FIG. 7 further includes: the chip controller The first address signal output by the memory controller is received, the first address signal carries the individual chip selection information and the address information of the individual chip selection information; the chip controller registers the individual chip selection information according to the first address signal.

According to an embodiment of the present invention, the first address signal also carries chip selection strategy information, the chip selection strategy information is stored in the chip controller and corresponds to the individual chip selection information, and the chip selection strategy information is used to indicate that the individual chip selection information is for controlling Whether the command signal is valid, wherein the method further includes: the chip controller receives the control command signal output by the memory controller, wherein the chip controller generates multiple independent chip selection information according to the first chip selection signal and the chip selection information stored in the chip controller The chip selection signal includes: if the chip selection strategy information indicates that the individual chip selection information is valid for the control command signal, the chip controller generates multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information.

Optionally, as another embodiment, the method in FIG. 7 further includes: if the chip selection policy information indicates that individual chip selection information is invalid for the control command signal, the chip controller generates Multiple individual chip selection signals, the predetermined chip selection information indicating that the generated multiple individual chip selection signals select corresponding multiple memory chips.

Optionally, as another embodiment, the method in FIG. 7 further includes: the chip controller receives the second individual chip selection indication signal and the second chip selection signal output by the memory controller, wherein the second individual chip selection indication signal and the first The two chip selection signals jointly instruct the chip controller to register individual chip selection information according to the first address signal.

Optionally, as another embodiment, the method in FIG. 7 further includes: the chip controller receives the first individual chip select indication signal output by the memory controller, wherein the first individual chip select indication signal and the first chip select signal jointly indicate The chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller.

Optionally, as another embodiment, the method in FIG. 7 further includes: the chip controller receiving the first clock enable signal output by the memory controller; the chip controller according to the first clock enable signal and the The individual clock enable information generates multiple individual clock enable signals, the multiple individual clock enable signals correspond to the multiple memory chips one by one, the first clock enable signal is used to control the clock signals of the multiple memory chips, and the multiple individual clock enable signals The clock enabling signals are respectively used to separately control the clock signal of at least one chip in the plurality of memory chips; the chip controller outputs a plurality of independent clock enabling signals to the plurality of memory chips respectively.

Optionally, as another embodiment, before the chip controller generates multiple individual clock enable signals according to the first clock enable signal and individual clock enable information registered in the chip controller, the method in FIG. 7 further includes: The chip controller receives the second address signal output by the memory controller, the address signal carries the individual clock enable information and the address information of the individual clock enable information, and the second address signal carries the individual clock enable information and the address of the individual clock enable information information; the chip controller registers independent clock enable information according to the second address signal.

According to an embodiment of the present invention, the second address signal also carries clock enabling policy information, which is stored in the chip controller and corresponds to individual clock enabling information, and the clock enabling policy information is used to indicate the individual clock Whether the enable information is valid for the control command signal, wherein the method further includes: the chip controller receives the control command signal output by the memory controller, wherein the chip controller enables the first clock enable signal and the individual clock registered in the chip controller Generate a plurality of individual clock enable signals through the enable information, including: if the clock enable policy information indicates that the individual clock enable information is valid, the chip controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information can signal.

Optionally, as another embodiment, the method in FIG. 7 further includes: if the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal, the chip controller according to the first clock enable signal and the predetermined clock The enabling information generates multiple independent clock enabling signals, and the generated multiple independent clock enabling signals select corresponding multiple memory chips.

Optionally, as another embodiment, the method in FIG. 7 further includes: the chip controller receives the second independent clock enable indication signal and the second clock enable signal output by the memory controller, wherein the second independent clock enable indication The signal and the second clock enable signal jointly instruct the chip controller to register individual clock enable information according to the second address signal.

Optionally, as another embodiment, the method in FIG. 7 further includes: the chip controller receives the first clock enable indication signal output by the memory controller, wherein the first clock enable indication signal and the first clock enable signal are combined Instructing the chip controller to generate multiple individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller.

FIG. 8 is a schematic flowchart of a method for controlling a memory chip according to another embodiment of the present invention. The method in FIG. 8 is executed by the memory controller, and includes the following contents.

810. The memory controller outputs the first chip select signal and the first individual chip select indication signal to the chip controller, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to The individual chip selection information registered in the chip controller generates multiple individual chip selection signals, and the individual chip selection information is used to generate multiple individual chip selection signals, and the multiple individual chip selection signals correspond to multiple memory chips one by one. The selection signal is used to indicate the selection of multiple memory chips, and the individual chip selection information is used to indicate the selection of at least one memory chip among the multiple memory chips.

820. The memory controller outputs a control command signal to multiple memory chips, so that at least one memory chip among the multiple memory chips performs an operation corresponding to the control command signal according to multiple individual chip select signals output by chip control.

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to multiple The memory chip outputs multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

Optionally, as another embodiment, the method in FIG. 8 further includes: the memory controller outputs a first address signal to the chip controller, where the address signal carries individual chip selection information and address information of the individual chip selection information.

According to an embodiment of the present invention, the address signal also carries chip selection strategy information, and the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the method further includes: the memory controller outputs the control command to the chip controller Signal.

Optionally, as another embodiment, the method in FIG. 8 further includes: the memory controller outputs a second individual chip selection indication signal and a second chip selection signal to the chip controller, wherein the second individual chip selection indication signal and the second The chip select signal jointly instructs the chip controller to register individual chip select information according to the address information.

Optionally, as another embodiment, the method in FIG. 8 further includes: the memory controller outputs a first clock enable signal and a first independent clock enable indication signal to the chip controller, wherein the first clock enable indication signal and The first clock enable signal jointly instructs the chip controller to generate multiple individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the individual clock enable information is used to generate multiple individual clock enable signals. A clock enable signal, multiple individual clock enable signals correspond to multiple memory chips one by one, the first clock enable signal is used to control the clock signals of multiple memory chips, and multiple individual clock enable signals are used for separate control A clock signal for at least one of the plurality of memory chips.

Optionally, as another embodiment, the method in FIG. 8 further includes: the memory controller outputs a second address signal to the chip controller, and the second address signal carries individual clock enable information and address information of the individual clock enable information.

According to an embodiment of the present invention, the address signal also carries clock enabling policy information, and the clock enabling policy information is used to indicate whether the individual clock enabling information is valid for the control command signal.

Optionally, as another embodiment, the method in FIG. 8 further includes: the memory controller outputs a second independent clock enable indication signal and a second clock enable indication signal to the chip controller, wherein the second independent clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register independent clock enable information according to the second address signal.

FIG. 9 is a schematic structure diagram of a chip controller according to an embodiment of the present invention. The chip controller 900 includes: a register 910 and a controller 920, the register 910 is connected to the controller 920, wherein the register 910 is used to store individual chip selection information; the controller 920 is used to: receive the first chip selection signal output by the memory controller ; Generate a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information stored in the output register, wherein the plurality of individual chip selection signals correspond to a plurality of memory chips one by one, and the first chip selection signal is used to indicate that multiple memory chips are selected. memory chips, the individual chip selection information is used to indicate that at least one memory chip among the plurality of memory chips is individually selected; multiple individual chip selection signals are respectively output to the plurality of memory chips, so that at least one memory chip among the plurality of memory chips is selected according to The control command signal output by the memory controller executes the operation corresponding to the control command signal.

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to multiple The memory chip outputs multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

According to an embodiment of the present invention, the register is also used to receive the first address signal output by the memory controller before the controller generates multiple individual chip select signals according to the first chip select signal and the individual chip select information stored in the register. An address signal carries the individual chip selection information and the address information of the individual chip selection information; the individual chip selection information is registered according to the first address signal.

According to an embodiment of the present invention, the first address signal also carries chip selection strategy information, the chip selection strategy information is stored in the chip controller and corresponds to the individual chip selection information, and the chip selection strategy information is used to indicate that the individual chip selection information is for controlling Whether the command signal is valid, the controller is also used to receive the control command signal output by the memory controller, and generate multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information stored in the chip controller, including: if the chip selection If the policy information indicates that the individual chip selection information is valid for the control command signal, multiple individual chip selection signals are generated according to the first chip selection signal and the individual chip selection information; if the chip selection strategy information indicates that the individual chip selection information is invalid for the control command signal, then Multiple individual chip select signals are generated according to the first chip select signal and predetermined chip select information, and the predetermined chip select information indicates that the generated multiple individual chip select signals select corresponding multiple memory chips.

According to an embodiment of the present invention, the register is also used to receive the second individual chip selection indication signal and the second chip selection signal output by the memory controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate the chip controller Individual chip select information is registered according to the first address signal.

According to an embodiment of the present invention, the controller is further configured to receive the first individual chip selection indication signal output by the memory controller, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to select Signals and individual chip select information registered in the chip controller generate a plurality of individual chip select signals.

According to an embodiment of the present invention, the controller is further configured to receive the first clock enable indication signal and the first clock enable signal output by the memory controller, and the first clock enable indication signal and the first clock enable signal jointly indicate the chip The controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the register is also used to receive the second individual clock enable indication signal output by the memory controller, the first The second clock enable signal and the second address signal, the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal, and the second address signal carries the individual clock Enable information, address information of individual clock enable information.

Fig. 10 is a schematic structural diagram of a memory according to an embodiment of the present invention. The memory 1000 includes: a plurality of memory chips 1010 and a chip controller 900 as shown in FIG. 9 .

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to multiple The memory chip outputs multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

FIG. 11 is a schematic structural diagram of a memory controller according to an embodiment of the present invention. The memory controller 1100 includes: a processor 1110 and a transmitter 1120, wherein the processor 1110 and the transmitter 1120 are connected, and the processor 1110 is used to generate a first chip select signal, a first individual chip select indication signal and a control command signal; The transmitter 1120 is configured to output the first chip selection signal and the first individual chip selection indication signal to the chip controller, wherein the first individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to and the individual chip selection information registered in the chip controller to generate multiple individual chip selection signals, the individual chip selection information is used to generate multiple individual chip selection signals, and the multiple individual chip selection signals correspond to multiple memory chips one by one, the first The chip selection signal is used to indicate to select multiple memory chips, and the individual chip selection information is used to indicate that multiple memory chips are individually selected and one less memory chip is selected, wherein the transmitter 1120 is also used to output control commands to multiple memory chips signal, so that at least one memory chip among the plurality of memory chips executes an operation corresponding to the control command signal according to a plurality of individual chip select signals output by the chip control.

Therefore, the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and sends them to multiple The memory chip outputs multiple individual chip select signals. Since separate chip selection information is stored in the chip controller, there is no need for the memory controller to send separate chip selection information for each command, thereby reducing the occupation of transmission bandwidth.

According to an embodiment of the present invention, the transmitter is further configured to output a first address signal to the chip controller, where the address signal carries individual chip selection information and address information of the individual chip selection information.

According to an embodiment of the present invention, the address signal also carries chip selection strategy information, and the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the transmitter is also used to output the control command signal to the chip controller.

According to an embodiment of the present invention, the transmitter is also used to output a second individual chip selection indication signal and a second chip selection signal to the chip controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate the chip controller Register individual chip selection information based on address information.

According to an embodiment of the present invention, the transmitter is also used to output a second individual chip selection indication signal and a second chip selection signal to the chip controller, and the second individual chip selection indication signal and the second chip selection signal jointly instruct the chip controller to The address information sends individual chip selection information.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the relationship between hardware and software Interchangeability. In the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

Through the above description of the implementation manners, those skilled in the art can clearly understand that the present invention can be implemented by hardware, firmware, or a combination thereof. When implemented in software, the functions described above may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example but not limitation: computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or may be used to carry or store information in the form of instructions or data structures desired program code and any other medium that can be accessed by a computer. also. Any connection can suitably be a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixation of the respective media. As used herein, disk and disc include compact disc (CD), laser disc, compact disc, digital versatile disc (DVD), floppy disc, and Blu-ray disc, where a disc usually reproduces data magnetically, and a disc Lasers are used to optically reproduce the data. Combinations of the above should also be included within the scope of computer-readable media.

In a word, the above descriptions are only preferred embodiments of the technical solutions of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims (21)

1. A chip controller, characterized in that, comprising: The register module is used to register individual chip selection information; The control module is configured to: receive the first chip select signal output by the memory controller; generate multiple individual chip select signals according to the first chip select signal and the individual chip select information registered by the registration module, wherein the multiple The individual chip selection signal is in one-to-one correspondence with a plurality of memory chips, the first chip selection signal is used to indicate selection of the plurality of memory chips, and the individual chip selection information is used to indicate the individual selection of one of the plurality of memory chips at least one memory chip; respectively outputting the plurality of individual chip select signals to a plurality of memory chips, so that at least one memory chip in the plurality of memory chips executes the control command signal output by the memory controller according to the control The operation corresponding to the command signal. 2. The method according to claim 1, wherein the registration module is further configured to: generate multiple Individual chip select signals before the receiving a first address signal output by the memory controller, the first address signal carrying the individual chip selection information and address information of the individual chip selection information; The individual chip select information is registered according to the first address signal. 3. The method according to claim 2, wherein the first address signal also carries chip selection strategy information, and the chip selection strategy information is stored in the chip controller and is associated with the individual chip selection information Correspondingly, the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, and the control module is also used to receive the control command signal output by the memory controller, The generating a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller includes: If the chip selection policy information indicates that the individual chip selection information is valid for the control command signal, generating the plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information; If the chip selection strategy information indicates that the individual chip selection information is invalid for the control command signal, generate a plurality of individual chip selection signals according to the first chip selection signal and predetermined chip selection information, and the predetermined chip selection signal The selection information indicates that the multiple generated individual chip select signals select the corresponding multiple memory chips. 4. The method according to claim 2 or 3, wherein the register module is further configured to receive a second independent chip selection indication signal and a second chip selection signal output by the memory controller, wherein the first The two individual chip selection indication signals and the second chip selection signal jointly instruct the chip controller to register the individual chip selection information according to the first address signal. 5. The method according to any one of claims 1-4, wherein the control module is further configured to receive a first individual chip selection indication signal output by the memory controller, wherein the first The individual chip selection indication signal and the first chip selection signal jointly instruct the chip controller to generate the multiple individual chip selection signals according to the first chip selection signal and the individual chip selection information stored in the chip controller . 6. The method according to any one of claims 1-5, characterized in that, The control module is also used to receive the first clock enable indication signal and the first clock enable signal output by the memory controller, the first clock enable indication signal and the first clock enable signal jointly indicate generating, by the chip controller, the multiple individual clock enable signals according to the first clock enable signal and individual clock enable information registered in the chip controller, The registration module is further configured to receive a second independent clock enable indication signal, a second clock enable signal and a second address signal output by the memory controller, the second independent clock enable indication signal and the first independent clock enable indication signal The two clock enable signals jointly instruct the chip controller to register the individual clock enable information according to the second address signal, and the second address signal carries the individual clock enable information and the address of the individual clock enable information information. 7. A memory, characterized by comprising: a plurality of memory chips and the chip controller according to any one of claims 1-6. 8. A memory controller, characterized in that, comprising: A generating module, configured to generate a first chip select signal, a first individual chip select indication signal, and a control command signal, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller according to The first chip select signal and the individual chip select information registered in the chip controller generate the multiple individual chip select signals, The output module is used to output the first chip selection signal and the first individual chip selection indication signal to the chip controller, and the individual chip selection information is used to generate a plurality of individual chip selection signals, and the plurality of individual chip selection signals are related to the plurality of individual chip selection signals. The memory chips correspond one to one, the first chip selection signal is used to indicate the selection of the plurality of memory chips, and the individual chip selection information is used to indicate the selection of at least one memory chip in the plurality of memory chips, The output module is also used to output control command signals to the plurality of memory chips, so that at least one of the memory chips in the plurality of memory chips executes a plurality of individual chip selection signals outputted according to the chip control and the control command signal. The operation corresponding to the command signal. 9. The method according to claim 8, wherein the output module is further configured to output a first address signal to the chip controller, the address signal carrying the individual chip selection information and the individual chip Select the address information of the information. 10. The method according to claim 9, wherein the address signal further carries chip selection strategy information, and the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, The output module is also used to output the control command signal to the chip controller. 11. The method according to any one of claims 9-10, wherein, The output module is further configured to output a second individual chip selection indication signal and a second chip selection signal to the chip controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate the The chip controller registers the individual chip selection information according to the address information. 12. A method for controlling memory, comprising: The chip controller receives the first chip select signal output by the memory controller; The chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, wherein the plurality of individual chip select signals are connected to the plurality of memory chips one by one Correspondingly, the first chip select signal is used to indicate to select the plurality of memory chips, and the individual chip select information is used to indicate to individually select at least one memory chip among the plurality of memory chips; The chip controller outputs the plurality of individual chip select signals to the plurality of memory chips respectively, so that at least one memory chip in the plurality of memory chips executes the matching with the plurality of memory chips according to the control command signal output by the memory controller. Operations corresponding to the above control command signals. 13. The method according to claim 12, wherein, before the chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller , the method also includes: The chip controller receives a first address signal output by the memory controller, where the first address signal carries the individual chip selection information and address information of the individual chip selection information; The chip controller registers the individual chip select information according to the first address signal. 14. The method according to claim 13, wherein the first address signal also carries chip selection strategy information, and the chip selection strategy information is stored in the chip controller and is associated with the individual chip selection information Correspondingly, the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, Wherein, the method also includes: The chip controller receives the control command signal output by the memory controller, Wherein, the chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, including: If the chip selection policy information indicates that the individual chip selection information is valid for the control command signal, the chip controller generates the plurality of individual chips according to the first chip selection signal and the individual chip selection information selection signal; If the chip selection policy information indicates that the individual chip selection information is invalid for the control command signal, the chip controller generates a plurality of individual chip selection signals according to the first chip selection signal and predetermined chip selection information, The predetermined chip selection information indicates that the plurality of generated individual chip selection signals select the corresponding plurality of memory chips. 15. The method according to claim 13 or 14, further comprising: The chip controller receives the second individual chip selection indication signal and the second chip selection signal output by the memory controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate that the chip The controller registers the individual chip selection information according to the first address signal. 16. The method according to any one of claims 12-15, further comprising: The chip controller receives the first individual chip select indication signal output by the memory controller, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to The chip select signal and the individual chip select information registered in the chip controller generate the plurality of individual chip select signals. 17. The method according to any one of claims 12-16, further comprising: The chip controller receives the first clock enable indication signal, the first clock enable signal, the second individual clock enable indication signal, the second clock enable signal and the second address signal output by the memory controller, wherein The first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate the the plurality of individual clock enable signals, the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal , the second address signal carries individual clock enablement information and address information of the individual clock enablement information. 18. A method for controlling a memory chip, comprising: The memory controller outputs a first chip select signal and a first individual chip select indication signal to the chip controller, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to The first chip select signal and the individual chip select information registered in the chip controller generate the multiple individual chip select signals, the individual chip select information is used to generate multiple individual chip select signals, and the multiple individual chip select signals The selection signal corresponds to a plurality of memory chips one by one, the first chip selection signal is used to indicate the selection of the plurality of memory chips, and the individual chip selection information is used to indicate the selection of at least one of the plurality of memory chips memory chips; The memory controller outputs a control command signal to the plurality of memory chips, so that at least one memory chip in the plurality of memory chips executes the control command signal according to a plurality of individual chip select signals output by the chip control. corresponding operation. 19. The method of claim 18, further comprising: The memory controller outputs a first address signal to the chip controller, and the address signal carries the individual chip selection information and address information of the individual chip selection information. 20. The method according to claim 19, wherein the address signal further carries chip selection strategy information, and the chip selection strategy information is used to indicate whether the individual chip selection information is valid for the control command signal, The method further includes: the memory controller outputting the control command signal to the chip controller. 21. The method according to any one of claims 19-20, further comprising: The memory controller outputs a second individual chip selection indication signal and a second chip selection signal to the chip controller, wherein the second individual chip selection indication signal and the second chip selection signal jointly indicate that the chip control The device registers the individual chip selection information according to the address information.