CN105095122B

CN105095122B - Control method, chip controller and the Memory Controller Hub of memory chip

Info

Publication number: CN105095122B
Application number: CN201410154996.1A
Authority: CN
Inventors: 肖世海; 杨伟; 赵俊峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-04-17
Filing date: 2014-04-17
Publication date: 2018-03-27
Anticipated expiration: 2034-04-17
Also published as: WO2015158264A1; CN105095122A

Abstract

Embodiments of the invention provide a kind of method, chip controller and Memory Controller Hub for controlling memory chip.The chip controller includes：Registration module, information is selected for depositing independent piece；Control module, it is used for：Receive the first chip selection signal of Memory Controller Hub output；Information is selected to generate multiple independent chip selection signals according to the independent piece that the first chip selection signal and registration module are deposited, plurality of individually chip selection signal corresponds with multiple memory chips, first chip selection signal is used to indicate the multiple memory chips of selection, and independent piece selects information to be used to indicate individually to select at least one memory chip in multiple memory chips；Multiple independent chip selection signals are exported to multiple memory chips respectively, so that the control command signal that at least one memory chip in multiple memory chips exports according to Memory Controller Hub performs operation corresponding with control command signal.Embodiments of the invention can efficiently reduce the occupancy to the transmission bandwidth of DRAM system.

Description

Control method, chip controller and the Memory Controller Hub of memory chip

Technical field

Embodiments of the invention are related to computer realm, more particularly to a kind of method, chip controls for controlling memory chip Device and Memory Controller Hub.

Background technology

Computer Architecture has memory system, and the most frequently used storage medium of memory system is dynamic random access memory Device（Dynamic Random Access Memory, DRAM）.The internal memory of computer is frequently with dual inline memory module （Dual Inline Memory Modules, DIMM）Form, the DIMM that can be deposited（Registered DIMM, RDIMM）With Low-load DIMM（Load-Reduced DIMM, LRDIMM）It is two kinds of conventional DIMM forms.RDIMM and LRDIMM is from internal memory Controller receives address signal, chip selection signal and clock enable signal, and is output to DIMM again after registration module is deposited On each dram chip.

Common RDIMM operation principle is：The dram chip of the narrow bit wide of multi-disc forms the DIMM of wide bit wide.RDIMM exists There is the circuit or chip of a deposit function, the circuit or chip deposit Memory Controller Hub are sent to DRAM on DIMM bars The signal such as chip selection signal, clock enable signal and address signal, and carry out being output to each dram chip after driving again. Each dram chip of one RDIMM internal memory is synchronously operated.

There is a kind of DRAM system similar with common RDIMM in the prior art.The Memory Controller Hub of the DRAM system and Have a DIMM register between dram chip, the register be used for scratch-pad memory controller be sent to DIMM chip selection signal, Clock enable signal and address signal, and it is sent to dram chip after driving these signals again.Also have in the DRAM system One decoder, for the chip selection signal and the enabled letter of clock for a RANK in whole DIMM for sending Memory Controller Hub Number it is decoded as the piece choosing of each dram chip and clock enable signal.Previous week of the DRAM system in current DRAM orders Phase sends independent piece corresponding to the DRAM orders and selects information, and chip selection signal and independent piece select information to be changed into multiple only after decoding Vertical chip selection signal, corresponding multiple dram chips in DIMM are controlled respectively.

However, each DRAM orders of Memory Controller Hub are required for sending independent piece choosing in the previous cycle of the DRAM orders Information, seriously occupy the transmission bandwidth of DRAM system.

The content of the invention

The embodiment provides a kind of method, chip controller and Memory Controller Hub for controlling memory chip, energy Enough efficiently reduce the occupancy to the transmission bandwidth of DRAM system.

First aspect, there is provided a kind of chip controller, including：Registration module, information is selected for depositing independent piece；Control Module, it is used for：Receive the first chip selection signal of Memory Controller Hub output；According to the first chip selection signal and output registration module deposit Independent piece select information to generate multiple independent chip selection signals, a pair of plurality of individually chip selection signal and multiple memory chips 1 Should, the first chip selection signal is used to indicate to select multiple memory chips, and independent piece selects information to be used to indicate individually to select multiple internal memories At least one memory chip in chip；Multiple independent chip selection signals are exported to multiple memory chips respectively, so as to multiple internal memories The control command signal that at least one memory chip in chip exports according to Memory Controller Hub performs and control command signal pair The operation answered.

With reference in a first aspect, in the first possible implementation of first aspect, registration module is additionally operable to：Controlling Before the independent piece that module is deposited according to the first chip selection signal and registration module selects the multiple individually chip selection signals of information generation, receive First address signal of Memory Controller Hub output, the first address signal carry independent piece and select information and independent piece to select the address of information Information, and independent piece is deposited according to the first address signal and selects information.

With reference to the first possible implementation of first aspect, in second of possible implementation of first aspect In, the first address signal also carrying sheets selects policy information, and piece selects policy information to be deposited with registration module and selected with independent piece Information is corresponding, and piece selects policy information to be used to indicate that independent piece selects information whether effective for control command signal, control module It is additionally operable to receive the control command signal of Memory Controller Hub output, control module is used to select policy information to indicate independent piece choosing in piece Information for control command signal it is effective when, according to the first chip selection signal and independent piece select information generation it is multiple individually pieces choosing letter Number.

With reference to the first or second of possible implementation of first aspect, in the third possible reality of first aspect In existing mode, control module is additionally operable to when piece selects policy information to indicate that independent piece selects information to be directed to control command invalidating signal, Information is selected to generate multiple independent chip selection signals according to the first chip selection signal and predetermined piece, predetermined piece selects information instruction generation Multiple memory chips corresponding to multiple individually chip selection signal selections.

With reference to first aspect the first to the third any of possible implementation, the 4th of first aspect the In kind possible implementation, the second independent piece that registration module is additionally operable to receive Memory Controller Hub output selects indication signal and the Two chip selection signals, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions registration module according to the first address Signal deposits independent piece and selects information.

With reference to the first of first aspect and first aspect to any of the 4th kind possible implementation, In 5th kind of possible implementation of one side, control module is additionally operable to receive the first independent piece choosing of Memory Controller Hub output Indication signal, wherein the first independent piece selects indication signal and the first chip selection signal joint instructions control module to be believed according to first choosing Number and registration module in the independent piece deposited select information to generate multiple independent chip selection signals.

With reference to the first of first aspect and first aspect to any of the 5th kind possible implementation, In 6th kind of possible implementation of one side, the first clock that control module is additionally operable to receive Memory Controller Hub output enables Signal, enabling the multiple individually clocks of information generation according to the independent clock deposited in the first clock enable signal and registration module makes Can signal, and to the multiple individually clock enable signals of multiple memory chips output, wherein, multiple individually clock enable signals with Multiple memory chips correspond, and the first clock enable signal is used for the clock signal for controlling multiple memory chips, multiple independent Clock enable signal is respectively used to individually control the clock signal of at least one chip in multiple memory chips.

With reference to the 6th kind of possible implementation of first aspect, in the 7th kind of possible implementation of first aspect In, registration module is additionally operable in chip controller according to the independent clock deposited in the first clock enable signal and chip controller Before the enabled multiple individually clock enable signals of information generation, the second address signal of Memory Controller Hub output, and root are received Deposit independent clock according to the second address signal and enable information, wherein, address signal carry independent clock enable information and it is independent when Clock enables the address information of information, and the second address signal carries the address that independent clock enables information and independent clock enables information Information.

With reference to the 7th kind of possible implementation of first aspect, in the 8th kind of possible implementation of first aspect In, the second address signal also carry clock enable policy information, clock enable policy information be deposited with chip controller and Corresponding with the enabled information of independent clock, clock enables policy information and is used to indicate that independent clock enables information and is directed to control command Whether signal effective, control module be additionally operable to receive Memory Controller Hub output control command signal, control module be used for when When the enabled policy information of clock indicates that the enabled information of independent clock is effective, according to the first clock enable signal and the enabled letter of independent clock The multiple individually clock enable signals of breath generation.

With reference to the 8th kind of possible implementation of first aspect, in the 9th kind of possible implementation of first aspect In, control module, which is additionally operable to enable policy information in clock, indicates that independent clock enables information and is directed to control command invalidating signal When, the multiple individually clock enable signals of information generation are enabled according to the first clock enable signal and predetermined clock, when predetermined Clock enables multiple memory chips corresponding to multiple individually clock enable signal selections of information instruction generation.

With reference to any of the 6th kind to the 9th kind possible implementation of first aspect, the tenth of first aspect the In the possible implementation of kind, the second independent clock that registration module is additionally operable to receive Memory Controller Hub output enables indication signal With second clock enable signal, wherein the second independent clock enable indication signal and second clock enable signal joint instructions control Module deposits independent clock according to the second address signal and enables information.

With reference to any of the 6th kind to the tenth kind possible implementation of first aspect, the tenth of first aspect the In a kind of possible implementation, the first clock that control module is additionally operable to receive Memory Controller Hub output enables indication signal, Wherein the first clock enables indication signal and the first clock enable signal joint instructions chip controller enables according to the first clock The independent clock deposited in signal and registration module enables the multiple individually clock enable signals of information generation.

Second aspect, there is provided a kind of internal memory, including：Multiple memory chips and such as any one of claim 1 to 12 Chip controller.

The third aspect provides a kind of Memory Controller Hub, including：Generation module, for generating the first chip selection signal, first Independent piece selects indication signal and control command signal；Output module, for exporting the first chip selection signal and the to chip controller One independent piece selects indication signal, wherein the first independent piece selects indication signal and the first chip selection signal joint instructions chip controller root Information is selected to generate multiple independent chip selection signals, independent piece choosing letter according to the independent piece deposited in the first chip selection signal and chip controller Cease for generating multiple independent chip selection signals, multiple individually chip selection signals correspond with multiple memory chips, first choosing letter Number be used in referring to the multiple memory chips of selection are shown, independent piece selects information to be used to indicate individually to select multiple memory chips few one Individual memory chip, wherein, output module is additionally operable to multiple memory chip output control command signals, so as to multiple memory chips In at least one memory chip according to chip controls export it is multiple individually chip selection signals perform it is corresponding with control command signal Operation.

With reference to the third aspect, in the first possible implementation of the third aspect, output module is additionally operable to chip Controller exports the first address signal, and address signal carries independent piece and selects information and independent piece to select the address information of information.

With reference to the first possible implementation of the third aspect, in second of possible implementation of the third aspect In, address signal also carrying sheets selects policy information, and piece selects policy information to be used to indicate that independent piece selects information for control command to believe Number whether effectively, wherein, output module is additionally operable to chip controller output control command signal.

With reference to the first or second of possible implementation of the third aspect, in the third possible reality of the third aspect In existing mode, output module is additionally operable to select indication signal and the second chip selection signal to chip controller the second independent piece of output, its In the second independent piece select indication signal and the second chip selection signal joint instructions chip controller to deposit independent piece according to address information Select information.

With reference to the first of the third aspect and the third aspect to the third any of possible implementation, In 4th kind of possible implementation of three aspects, output module is additionally operable to export the first clock enable signal to chip controller Indication signal is enabled with the first independent clock, wherein the first clock enables indication signal and the first clock enable signal joint instructions Chip controller enables information according to the independent clock deposited in the first clock enable signal and chip controller and generates multiple lists Only clock enable signal, independent clock enable information and are used to generate multiple individually clock enable signals, and multiple individually clocks enable Signal corresponds with multiple memory chips, and the first clock enable signal is used for the clock signal for controlling multiple memory chips, more Individual individually clock enable signal is respectively used to individually control the clock signal of at least one chip in multiple memory chips.

With reference to the 4th kind of possible implementation of the third aspect, in the 5th kind of possible implementation of the third aspect In, output module is additionally operable to export the second address signal to chip controller, and the second address signal carries the enabled letter of independent clock Breath and independent clock enable the address information of information.

With reference to the 5th kind of possible implementation of the third aspect, in the 6th kind of possible implementation of the third aspect In, address signal also carries clock and enables policy information, and clock enables policy information and is used to indicate that independent clock enables information pin It is whether effective to control command signal.

With reference to any of the 4th kind to the 6th kind possible implementation of the third aspect, the 7th of the third aspect the In kind possible implementation, output module, which is additionally operable to export the second independent clock to chip controller, enables indication signal and the Two clock enable signals, wherein the second independent clock enables indication signal and second clock enable signal joint instructions chip controls Device deposits independent clock according to the second address signal and enables information

Fourth aspect, there is provided a kind of method for controlling internal memory, including：Chip controller receives Memory Controller Hub output First chip selection signal；Chip controller selects information generation more according to the independent piece deposited in the first chip selection signal and chip controller Individual independent chip selection signal, plurality of individually chip selection signal correspond with multiple memory chips, and the first chip selection signal is used to refer to Show the multiple memory chips of selection, independent piece selects information to be used to indicate individually to select at least one internal memory core in multiple memory chips Piece；Chip controller exports multiple independent chip selection signals to multiple memory chips respectively, so as in multiple memory chips at least The control command signal that one memory chip exports according to Memory Controller Hub performs operation corresponding with control command signal.

With reference to fourth aspect, in the first possible implementation of fourth aspect, in chip controller according to first Before the independent piece deposited in chip selection signal and chip controller selects the multiple individually chip selection signals of information generation, method also includes： Chip controller receives the first address signal of Memory Controller Hub output, and the first address signal carries independent piece and selects information and individually Piece selects the address information of information；Chip controller deposits independent piece according to the first address signal and selects information.

With reference to the first possible implementation of fourth aspect, in second of possible implementation of fourth aspect In, the first address signal also carrying sheets selects policy information, piece select policy information be deposited with chip controller and with independent piece Select information corresponding, piece selects policy information to be used to indicate that independent piece selects information whether effective for control command signal, wherein, should Method also includes：Chip controller receives the control command signal of Memory Controller Hub output, wherein, chip controller is according to first The independent piece deposited in chip selection signal and chip controller selects information to generate multiple independent chip selection signals, including：As chankings selects plan Slightly information indicates that independent piece selects information effective for control command signal, then chip controller is according to the first chip selection signal and individually Piece selects information to generate multiple independent chip selection signals.

With reference to the first or second of possible implementation of fourth aspect and fourth aspect, the of fourth aspect In three kinds of possible implementations, this method also includes：As chankings selects policy information to indicate that independent piece selects information to be ordered for control Making invalidating signal, then chip controller selects information to generate multiple independent chip selection signals according to the first chip selection signal and predetermined piece, Predetermined piece selects multiple memory chips corresponding to multiple individually chip selection signal selections of information instruction generation.

With reference to the first or the third possible implementation of fourth aspect and fourth aspect, the of fourth aspect In four kinds of possible implementations, this method also includes：Chip controller receives the second independent piece choosing of Memory Controller Hub output Indication signal and the second chip selection signal, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions chip controls Device deposits independent piece according to the first address signal and selects information.

With reference to the first or the 4th kind of possible implementation of fourth aspect and fourth aspect, the of fourth aspect In five kinds of possible implementations, this method also includes：Chip controller receives the first independent piece choosing of Memory Controller Hub output Indication signal, wherein the first independent piece selects indication signal and the first chip selection signal joint instructions chip controller according to first choosing The independent piece deposited in signal and chip controller selects information to generate multiple independent chip selection signals.

With reference to the first or the 5th kind of possible implementation of fourth aspect and fourth aspect, the of fourth aspect In six kinds of possible implementations, this method also includes：The first clock that chip controller receives Memory Controller Hub output enables Signal；Chip controller is more according to the enabled information generation of the independent clock deposited in the first clock enable signal and chip controller Individual individually clock enable signal, multiple individually clock enable signals correspond with multiple memory chips, the enabled letter of the first clock Number it is used to control the clock signals of multiple memory chips, multiple individually clock enable signals are respectively used to individually control multiple internal memories The clock signal of at least one chip in chip；Chip controller makes to the multiple individually clocks of multiple memory chips output respectively Can signal.

With reference to the 6th kind of possible implementation of fourth aspect, in the 7th kind of possible implementation of fourth aspect In, it is more according to the enabled information generation of the independent clock deposited in the first clock enable signal and chip controller in chip controller Before individual individually clock enable signal, in addition to：Chip controller receives the second address signal of Memory Controller Hub output, address Signal carries the address information that independent clock enables information and independent clock enables information, and the second address signal carries independent clock Enabled information and independent clock enable the address information of information；Chip controller deposits independent clock according to the second address signal to be made Can information.

With reference to the 7th kind of possible implementation of fourth aspect, in the 8th kind of possible implementation of fourth aspect In, the second address signal also carry clock enable policy information, clock enable policy information be deposited with chip controller and Corresponding with the enabled information of independent clock, clock enables policy information and is used to indicate that independent clock enables information and is directed to control command Whether signal is effective, wherein, this method also includes：Chip controller receives the control command signal of Memory Controller Hub output, its Chips controller is multiple according to the enabled information generation of the independent clock deposited in the first clock enable signal and chip controller Independent clock enable signal, including：

If clock enables policy information and indicates that the enabled information of independent clock is effective, chip controller is according to the first clock Enable signal and independent clock enable the multiple individually clock enable signals of information generation.

With reference to the 8th kind of possible implementation of fourth aspect, in the 9th kind of possible implementation of fourth aspect In, this method also includes：If clock enables policy information and indicates that independent clock enables information and is directed to control command invalidating signal, Then chip controller enables the multiple individually clock enable signals of information generation according to the first clock enable signal and predetermined clock, Multiple memory chips corresponding to multiple individually clock enable signal selections of generation.

With reference to any of the 6th kind to the 9th kind possible implementation of fourth aspect, the tenth of fourth aspect the In the possible implementation of kind, this method also includes：The second independent clock that chip controller receives Memory Controller Hub output makes Energy indication signal and second clock enable signal, wherein the second independent clock enables indication signal and second clock enable signal connection Close instruction chip controller and the enabled information of independent clock is deposited according to the second address signal.

With reference to any of the 6th kind to the tenth kind possible implementation of fourth aspect, the tenth of fourth aspect the In a kind of possible implementation, this method also includes：The first clock that chip controller receives Memory Controller Hub output enables Indication signal, wherein the first clock enables indication signal and the first clock enable signal joint instructions chip controller according to first The independent clock deposited in clock enable signal and chip controller enables the multiple individually clock enable signals of information generation.

5th aspect, there is provided a kind of method for controlling memory chip, this method include：Memory Controller Hub is to chip controls Device exports the first chip selection signal and the first independent piece selects indication signal, wherein the first independent piece selects indication signal and first choosing letter Number joint instructions chip controller selects information generation multiple according to the independent piece deposited in the first chip selection signal and chip controller Independent chip selection signal, independent piece select information to be used to generate multiple independent chip selection signals, multiple individually chip selection signals and multiple internal memories Chip corresponds, and the first chip selection signal is used to indicate to select multiple memory chips, and independent piece selects information to be used to indicate individually to select Select at least one memory chip in multiple memory chips；Memory Controller Hub to multiple memory chip output control command signals, So as at least one memory chip in multiple memory chips according to chip controls export it is multiple individually chip selection signals perform with Operated corresponding to control command signal.

With reference to the 5th aspect, in the first possible implementation of the 5th aspect, this method also includes：Memory control Device exports the first address signal to chip controller, and address signal carries independent piece and selects information and independent piece to select the address of information to believe Breath.

With reference to the first possible implementation of the 5th aspect, in second of possible implementation of the 5th aspect In, address signal also carrying sheets selects policy information, and piece selects policy information to be used to indicate that independent piece selects information for control command to believe Number whether effectively, wherein, this method also includes：Memory Controller Hub is to chip controller output control command signal.

With reference to the first and second of possible implementation of the 5th aspect, in the third possible reality of the 5th aspect In existing mode, this method also includes：Memory Controller Hub exports the second independent piece to chip controller and selects indication signal and second Signal is selected, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions chip controller to be posted according to address information The only piece of deposit receipt selects information.

With reference to the first of the 5th aspect and the 5th aspect to the third any possible implementation, the 5th In 4th kind of possible implementation of aspect, this method also includes：Memory Controller Hub exports the first clock to chip controller Enable signal and the first independent clock enable indication signal, wherein the first clock enables indication signal and the first clock enable signal Joint instructions chip controller enables information life according to the independent clock deposited in the first clock enable signal and chip controller Into multiple individually clock enable signals, independent clock enables information and is used to generate multiple individually clock enable signals, multiple independent Clock enable signal corresponds with multiple memory chips, and the first clock enable signal is used for the clock for controlling multiple memory chips Signal, multiple individually clock enable signals are respectively used to individually control the clock letter of at least one chip in multiple memory chips Number.

With reference to the 4th kind of possible implementation of the 5th aspect, in the 5th kind of possible implementation of the 5th aspect In, this method also includes：Memory Controller Hub exports the second address signal to chip controller, when the second address signal carries independent Clock enables information and independent clock enables the address information of information.

With reference to the 5th kind of possible implementation of the 5th aspect, in the 6th kind of possible implementation of the 5th aspect In, address signal also carries clock and enables policy information, and clock enables policy information and is used to indicate that independent clock enables information pin It is whether effective to control command signal.

With reference to any of the 4th kind to the 6th kind possible implementation of the 5th aspect, the 7th of the 5th aspect the In the possible implementation of kind, this method also includes：Memory Controller Hub exports the enabled finger of the second independent clock to chip controller Show signal and second clock enable signal, refer to wherein the enabled indication signal of the second independent clock and second clock enable signal are combined Show that chip controller deposits independent clock according to the second address signal and enables information.

Therefore, technical scheme selects information by depositing independent piece in chip controller, according to from internal memory control The chip selection signal and the independent piece of deposit that device processed receives select information to generate multiple independent chip selection signals, and respectively to described more Individual memory chip exports the multiple independent chip selection signal.Information, therefore nothing are selected due to having deposited independent piece in chip controller Need Memory Controller Hub to send independent piece for each order and select information, so as to reduce the occupancy to transmission bandwidth.

Brief description of the drawings

In order to illustrate the technical solution of the embodiments of the present invention more clearly, it will make below to required in the embodiment of the present invention Accompanying drawing is briefly described, it should be apparent that, drawings described below is only some embodiments of the present invention, for For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings Accompanying drawing.

Fig. 1 is the schematic diagram of memory system according to an embodiment of the invention.

Fig. 2 is the schematic diagram of chip controller according to an embodiment of the invention.

Fig. 3 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.

Fig. 4 is the indicative flowchart of the method for control memory chip according to embodiments of the present invention.

Fig. 5 A are the schematic diagrames of the signal stream of memory system according to an embodiment of the invention.

Fig. 5 B are the schematic diagrames of the signal stream of chip controller according to an embodiment of the invention.

Fig. 6 is the indicative flowchart of the control method of chip controller according to an embodiment of the invention.

Fig. 7 is the indicative flowchart of the method for control memory chip according to another embodiment of the present invention.

Fig. 8 is the indicative flowchart of the method for control memory chip according to still another embodiment of the invention.

Fig. 9 is the schematic diagram of chip controller according to an embodiment of the invention.

Figure 10 is the schematic diagram of internal memory according to an embodiment of the invention.

Figure 11 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is part of the embodiment of the present invention, rather than whole embodiments.Based on this hair Embodiment in bright, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made Example, belongs to the scope of protection of the invention.

Fig. 1 is the schematic diagram of memory system 100 according to embodiments of the present invention.Memory system 100 includes internal memory Controller 110 and internal memory 120.

Memory Controller Hub 110 is used to control internal memory 120 and central processing unit（Central Processing Unit, CPU） Between data exchange.Internal memory 120 includes chip controller 121 and multiple memory chips 122.Chip controller 121 is positioned at interior Between memory controller 110 and memory chip 122, for controlling operation of the Memory Controller Hub 110 to memory chip 122.Internal memory control Communicated between device 110 processed and internal memory 120 by communication bus.It should be understood that chip controller 121 may be located on internal memory it Outside, in other words, chip controller 121 can separate with memory chip 122.Memory Controller Hub 110 and central processing unit （CPU）It can be separation, can also be incorporated into CPU.

It should also be understood that the technical scheme of embodiments of the invention can apply to a variety of different memory organization forms, example As internal memory 120 can also use other forms, for example, also may be used using the form of dual inline memory module (DIMM) To be chip controller and processor on one piece of veneer.Or subcard or daughter board of the chip controller as other forms.

Chip controller 121 is connected with memory chip 122, for example, can make control command signal and address signal from DIMM side is input in chip, can make the opposite side of independent chip selection signal and/or independent clock enable signal from DIMM It is input in chip.However, it should be understood that embodiments of the invention are not limited to this mode.

Interface between chip controller 121 and Memory Controller Hub 110 can transmit Double Data Rate synchronous random access memory （DDR）Address in transmission standard（ADDRESS）Signal, control command (CMD) signal, piece choosing (CS) signal and clock enable (CKE) signal etc., in addition, the interface between chip controller 121 and Memory Controller Hub 110 can also transmit instruction letter Number, for example, this indication signal, which can be used for registration module, determines that depositing independent piece selects information and independent clock to enable information, this Kind indication signal can be also used for control module and determine to handle chip selection signal and clock enable signal.

Memory Controller Hub 110 and central processing unit（CPU）It is connected and is controlled by central processing unit.

Fig. 2 is the schematic diagram of chip controller 200 according to embodiments of the present invention.Chip controller 200 is Fig. 1 Chip controller 121 example.Chip controller 200 includes：Registration module 210 and control module 220.

Control module 220 is used for：Receive the first chip selection signal of Memory Controller Hub output；According to the first chip selection signal and post The independent piece that storing module 210 is deposited selects information to generate multiple independent chip selection signals, plurality of individually chip selection signal with it is multiple interior Chip one-to-one corresponding is deposited, the first chip selection signal is used to indicate to select multiple memory chips, and independent piece selects information to be used to indicate individually Select at least one memory chip in multiple memory chips；Multiple independent chip selection signals are exported to multiple memory chips respectively, So that the control command signal that at least one memory chip in multiple memory chips exports according to Memory Controller Hub performs and controls Operated corresponding to command signal processed.

Therefore, technical scheme selects information by depositing independent piece in chip controller, according to chip selection signal Information is selected to generate multiple independent chip selection signals with the independent piece of deposit, and it is described more to the output of the multiple memory chip respectively Individual independent chip selection signal.Information is selected due to having deposited independent piece in chip controller, therefore without Memory Controller Hub for each Order all sends independent piece and selects information, so as to reduce the occupancy to transmission bandwidth.

Alternatively, as another embodiment, chip controller 200 can also include another registration module, wherein controlling mould The signal that block 220 exports gives another registration module.The registration module is used to cache and drive signal again.It is good in signal quality In the case of sequential allowance abundance, it is convenient to omit the registration module.

The input signal of chip controller 200 can be Memory Controller Hub output CMD, ADDRESS, CS, CKE signal and Indication signal, output signal can be the independent chip selection signal of corresponding each chip and independent clock enable signal.It is each independent Chip selection signal is used to control chip corresponding to the independent chip selection signal to perform specific operational order.Each enabled letter of individually clock Number be used for control chip corresponding to the independent clock enable signal to be in sleep pattern.

It should be understood that chip controller can receive the first chip selection signal that Memory Controller Hub exports by communication bus.Tool For body, all memory chips in the first chip selection signal instruction selection memory bar are to be operated, for example, write operation or reading Extract operation, embodiments of the invention are not limited to this, for example, operation can also include the operations such as activation, precharge or refreshing.Change Sentence is talked about, and each memory chip receives the first chip selection signal to perform the operation of control command signal designation.Independent piece choosing letter Number corresponded with memory chip, the instruction of independent chip selection signal chooses its corresponding memory chip to be controlled command signal instruction Operation.

It should also be understood that when individually chip selection signal selects corresponding memory chip execution operation, independent piece can be set Effective when to select signal be high level or during low level, embodiments of the invention are not construed as limiting to this.

According to an embodiment of the invention, registration module is additionally operable to：In control module according to the first chip selection signal and deposit mould Before the independent piece of block deposit selects the multiple individually chip selection signals of information generation, the first address letter of Memory Controller Hub output is received Number, the first address signal carries independent piece and selects information and independent piece to select the address information of information；Deposited according to the first address signal Independent piece selects information.

It should be understood that address signal instruction registration module deposits independent piece and selects information.For example, it may be registration module is according to finger The control command signal and address signal for showing registration operations select information to deposit independent piece.It can also be registration module base area Location signal deposits independent piece and selects information.It should also be understood that can only be sent once during the complete operation of each memory chip, It can also send repeatedly.Such as Memory Controller Hub only writes, during reading or refresh operation in the once complete of data Sent before first control command signal and carry the signal that independent piece selects information, control module is directed to internal memory core in this operation The later control command signal of piece calls the independent piece of registration module deposit to select information.

Information is selected due to having deposited independent piece so that chip controller can obtain the independent piece when needed and select information, Information is selected so as to which chip controller need not be directed to the independent piece of each control command signal reception, bandwidth is saved, improves control The flexibility of coremaking piece.

According to an embodiment of the invention, the first address signal also carrying sheets selects policy information, and piece selects policy information to be deposited with Select information corresponding in registration module and with independent piece, piece selects policy information to be used to indicate that independent piece selects information to order for control Make signal whether effective, control module is additionally operable to receive the control command signal of Memory Controller Hub output, wherein, control module is used In when piece selects policy information to indicate that independent piece selects information effective for control command signal, according to the first chip selection signal and individually Piece selects information to generate multiple independent chip selection signals.As chankings selects policy information to indicate that independent piece selects information to be directed to control command signal Invalid, then control module selects information to generate multiple independent chip selection signals, predetermined piece according to the first chip selection signal and predetermined piece Multiple individually chip selection signals of information instruction generation are selected to choose corresponding multiple memory chips.

Specifically, for independent piece piece corresponding to information setting can be selected to select policy information.In other words, the piece selects plan Slightly information and independent piece select information and predetermined control command signal mapping relations to be all present.In this case, control module In the information deposited in calling registration module, the independent piece of Selection and call does not select information, and piece choosing strategy letter corresponding to only calling Breath.

For example, policy information indicates that independent piece selects information effective for refresh command, then chip controller is receiving brush In the case of newer command, information is selected to export independent chip selection signal according to independent piece.It should be understood that control command signal can also be all Such as write operation command signal, read operation command signal or activation（Activate, ACT）Any one in command signal.

In another example policy information indicates that independent chip selection signal is invalid for read command signal, then chip controller according to Predetermined piece selects information to generate and exports multiple independent chip selection signals.For example, if policy information indicates that independent piece selects information pin Invalid to read command, then chip controller will not export independent chip selection signal, but export in the case where receiving read command First chip selection signal.It should be understood that control command signal can also be in act command signal, refresh command signal, write operation signal Any one.Predetermined piece selects information to could be arranged to give tacit consent to, and specifically, it is all interior can to indicate that chip controller is chosen Deposit chip.

Different strategies is defined as a result of policy information, and for different control commands so that for need not The control command for exporting independent chip selection signal only exports a chip selection signal, without exporting multiple independent chip selection signals, from And reduce the transmission of unnecessary information, improve the utilization rate of bandwidth.

According to an embodiment of the invention, registration module is additionally operable to receive the second independent piece choosing instruction of Memory Controller Hub output Signal and the second chip selection signal, wherein the second independent piece select indication signal and the second chip selection signal joint instructions registration module according to First address signal deposits independent piece and selects information.

Ordered it should be understood that the first chip selection signal and the second chip selection signal carry the choosing of identical piece.Second chip selection signal indicates Deposit independent piece and select information, the instruction of the first chip selection signal selects information to export independent chip selection signal according to the independent piece deposited.The Two independent pieces select indication signal and the second chip selection signal to be used to indicate that chip controller deposits independent piece according to the first address signal Information is selected, for example, chip controller can be when the second independent piece selects indication signal and the second chip selection signal is simultaneously effective, deposit The independent piece carried in first address signal selects information.Specifically, it is high level that can select indication signal in the second independent piece When, it is defined as effectively, and when the second chip selection signal is low level, the second chip selection signal is defined as effectively.Ying Li It solution, can also be defined as effectively when it is low level that the second independent piece, which selects indication signal, and be high electricity in the second chip selection signal Usually, the second chip selection signal is defined as effectively.

Because chip controller can select indication signal and the second chip selection signal to judge whether storage receipt with the second independent piece Only piece selects information so that when that need not deposit independent piece and select information, chip controller is only forwarding without the operation of deposit The signal of reception, so as to enhance the flexibility that Memory Controller Hub is controlled chip controller, while improve the utilization of bandwidth Rate.

According to an embodiment of the invention, control module is additionally operable to receive the first independent piece choosing instruction of Memory Controller Hub output Signal, wherein the first independent piece select indication signal and the first chip selection signal joint instructions control module according to the first chip selection signal and The independent piece deposited in registration module selects information to generate multiple independent chip selection signals.

It should be understood that the first independent piece selects indication signal and the first chip selection signal joint instructions chip controller according to first The independent piece deposited in signal and chip controller is selected to select information to generate multiple independent chip selection signals.Indicated with the second independent piece choosing Signal and the second chip selection signal are similar, for example, chip controller can select indication signal and first choosing letter in the first independent piece When number simultaneously effective, handle independent piece and select information, and select information to generate independent chip selection signal according to independent piece.Specifically, with Second independent piece selects indication signal similar, indication signal can be selected to be determined in high level or in low level the first independent piece To be effective.It is similar to the second chip selection signal, the first chip selection signal can be defined as effectively in high level or in low level.

Because chip controller can select indication signal and the first chip selection signal to judge whether to generate according to the first independent piece Independent chip selection signal so that chip controller operates when that need not export independent chip selection signal without corresponding, so as to increase The flexibility that strong Memory Controller Hub is controlled chip controller, further enhancing Memory Controller Hub to internal memory chip controls Flexibility.

According to an embodiment of the invention, control module is additionally operable to receive the enabled instruction of the first clock of Memory Controller Hub output Signal, the first clock enable signal, the first clock enable indication signal and the first clock enable signal joint instructions chip controls Device enables the multiple individually clocks of information generation according to the independent clock deposited in the first clock enable signal and chip controller to be made Energy signal, the second independent clock that registration module is additionally operable to receive Memory Controller Hub output enables indication signal, second clock makes Energy signal and the second address signal, the second independent clock enable indication signal and second clock enable signal joint instructions chip control Device processed deposits independent clock according to the second address signal and enables information, and the second address signal carries independent clock and enables information, list Only clock enables the address information of information.

It should be understood that clock enable signal is similar with chip selection signal, the instruction of clock enable signal selects multiple memory chips to hold The operation of row control command signal designation.Independent chip selection signal is similar to independent clock enable signal, for example, can set individually Clock enable signal is effective when being high level or low level.

It should be understood that address signal instruction registration module deposits independent clock and enables information.For example, it may be registration module root According to the control command signal and address signal of instruction registration operations information is enabled to deposit independent clock.Can also deposit mould Root tuber deposits independent clock according to address signal and enables information.

It should also be understood that the signal for carrying the enabled information of independent clock can be during the complete operation of each memory chip Only send once, can also send repeatedly.Such as Memory Controller Hub is only in once complete write-in, reading or the refresh operation of data During first control command signal before send and carry the signal that independent clock enables information, control module is in the behaviour The independent clock for calling registration module deposit for the later control command signal of memory chip in work enables information.

Specifically, independent clock can be directed to and enable the enabled policy information of clock corresponding to information setting.In other words, The clock enables policy information and independent clock enables information and predetermined control command signal all has mapping relations.This In the case of, for control module in the information deposited in calling registration module, the independent clock of Selection and call does not enable information, and only adjusts Policy information is enabled with corresponding clock.

For example, policy information indicates that the enabled information of independent clock is effective for act command, then chip controller is ordered in ACT In the case of order, information is enabled according to independent clock and exports independent clock enable signal.It should be understood that control command signal can be with It is any one in such as write operation command signal, read operation command signal or refresh command signal.

It should be understood that the first clock enable signal carries the enabled order of identical clock with second clock enable signal.Second The instruction of clock enable signal deposits independent clock and enables information, and the first clock enable signal is indicated according to the independent clock deposited Enabled information exports independent clock enable signal.Second independent clock enables indication signal and second clock enable signal is used to refer to Show that chip controller deposits independent clock according to the first address signal and enables information, for example, chip controller can be single second When only clock enables indication signal and simultaneously effective second clock enable signal, deposit independent clock and enable information.Specifically, It can be defined as effectively when it is high level that the second independent clock, which enables indication signal, and in the enabled letter of second clock When number being low level, second clock enable signal is defined as effectively.It should be understood that can also be in the enabled instruction of the second independent clock When signal is low level, it is defined as effectively, and when second clock enable signal is high level, by second clock enable signal It is defined as effectively.

It should be understood that the first independent clock enables indication signal and the first clock enable signal joint instructions chip controller root The multiple enabled letters of individually clock of information generation are enabled according to the independent clock deposited in the first clock enable signal and chip controller Number.Enabling indication signal to the second independent clock, also second clock enable signal is similar, for example, can be with chip controller When the first independent clock enables indication signal and the first clock enable signal is simultaneously effective, handle independent clock and enable information, And information is enabled according to independent clock and generates independent clock enable signal.Specifically, believe with the enabled instruction of the second independent clock It is number similar, the first independent clock can be enabled to indication signal and be defined as effectively in high level or in low level.With second Clock enable signal is similar, can be defined as the first clock enable signal effectively in high level or in low level.

Due to exporting independent clock enable signal for each memory chip so that memory chip clock signal when not needed In the case of, do not receive the order of clock signal.Due to generating independent clock enable signal, so that chip controller can be with Independent control chip, such as specific chip is in sleep pattern, so as to reduce the power consumption of chip.

Fig. 3 is the schematic diagram of Memory Controller Hub according to another embodiment of the present invention.The Memory Controller Hub 300 Including：Generation module 310, for generating the first chip selection signal, the first independent piece selects indication signal and control command signal；Output Module 320, for selecting indication signal to chip controller the first chip selection signal of output and the first independent piece, wherein the first independent piece Indication signal and the first chip selection signal joint instructions chip controller is selected to be deposited according in the first chip selection signal and chip controller Independent piece select information to generate multiple independent chip selection signals, independent piece selects information to be used to generate multiple independent chip selection signals, multiple Independent chip selection signal corresponds with multiple memory chips, the first chip selection signal be used in referring to showing the multiple internal memory cores of selection Piece, independent piece select information to be used to indicate individually to select the few memory chip of multiple memory chips；Output module is additionally operable to more Individual memory chip output control command signal, so that at least one memory chip in multiple memory chips is defeated according to chip controls The multiple individually chip selection signals gone out perform operation corresponding with control command signal.

According to an embodiment of the invention, output module is additionally operable to export the first address signal, address letter to chip controller Number carrying independent piece selects information and independent piece to select the address information of information.

According to an embodiment of the invention, address signal also carrying sheets selects policy information, and piece selects policy information to be used to indicate list Whether only piece selects information effective for control command signal, wherein, output module is additionally operable to order to chip controller output control Make signal.

According to an embodiment of the invention, output module is additionally operable to select indication signal to chip controller the second independent piece of output With the second chip selection signal, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions chip controller base area Location information deposits independent piece and selects information.

Fig. 4 is the indicative flowchart of the method for the control memory chip of one embodiment of the present of invention.Fig. 5 A are bases The schematic diagram of the signal stream of the memory system of embodiments of the invention.Fig. 5 B are chip controllers according to an embodiment of the invention Signal stream schematic diagram.

The method described by Fig. 4 is described with reference to Fig. 5 A and Fig. 5 B, wherein Fig. 5 A show Memory Controller Hub, chip Method for transmitting signals between controller and memory chip.Fig. 5 B particularly illustrate the control module pin in chip controller To the operation performed by multiple signals.

In this embodiment, for convenience describe, the first independent piece select indication signal, the second independent piece select indication signal, First independent clock enables indication signal and the second independent clock enables indication signal and is referred to as indication signal, the first address signal Address signal is referred to as with the second address signal, and the first chip selection signal and the second chip selection signal are referred to as chip selection signal, when first Clock enable signal and second clock enable signal are referred to as clock enable signal.In addition, the present embodiment is formed using dram chip DIMM memory bars.

410, registration module receives the bus line command signal of Memory Controller Hub output.

Bus line command signal includes address signal, control command signal, chip selection signal, clock enable signal and instruction letter Number.

420, registration module selects indication signal to determine to deposit independent piece choosing letter according to the second chip selection signal and the second independent piece Breath, registration module enable indication signal according to second clock enable signal and the second independent clock and determine that depositing independent clock enables Information.

For example, when the second chip selection signal and the second independent piece select indication signal simultaneously effective, represent that registration module determines Deposit independent piece and select information.When second clock enable signal and simultaneously effective enabled indication signal of the second independent clock, represent Registration module determines that depositing independent clock enables information.For example, it is effective during high level to be predefined for the second chip selection signal, make Second independent piece selects indication signal and the second independent clock to enable indication signal and is predefined for effective during low level, and makes second clock Enable signal is predefined for effective during high level.

430, registration module deposits independent chip selection information and independent clock enables information.

Address signal carry independent piece select information, independent clock enable information and independent piece select information address information and Independent clock enables the address information of information.Memory Controller Hub will be independent by the address signal in bus and control command signal Piece selects information and independent clock to enable information and be written in registration module.Registration module is divided into piece and selects registration module and clock again Enabled registration module, it is respectively used to deposit independent piece and selects information and independent clock to enable information, for example, table 1 shows deposit mould The independent piece that block is deposited selects information and independent clock to enable information and have particular address a0 and a1 respectively.

Table 1

The address of the parameter of deposit	The parameter type of deposit
		a0	Independent piece selects information

a1	Independent clock enables information

440, registration module deposit selects the piece of information to select policy information for independent piece, and the piece selects policy information to be used to indicate Independent piece selects the application strategy of information.The clock that registration module deposit enables information also directed to independent clock enables policy information, The clock enables policy information and is used for the application strategy for indicating that independent clock enables information.

For example, whether the piece selects policy information indicator to select information effective the independent piece of act command signal.For example, this when Whether clock policy information indicator enables information to the independent clock of act command signal effective.

For example, piece can be selected policy information to be defined as the policy information for act command, i.e., when control module receives During the signal of act command, determined whether to select information to export independent chip selection signal according to independent piece according to the policy information.If should Policy information nevertheless indicates that selects information to export independent chip selection signal according to independent piece, then control module selects information defeated according to independent piece Go out independent chip selection signal.If policy information instruction exports chip selection signal according to predetermined default information, control module according to Predetermined default information output chip selection signal, for example, default information is set to indicate that all independent chip selection signals by control module All output is effective, and ignores independent piece and select information.In other words, it is similar to chip selection signal, all individually chip selection signals is all referred to Memory chip corresponding to showing carries out execution act command.The operational orders such as other control commands such as reading order or refresh command with Act command is similar, will not be repeated here.

It is also possible to clock is enabled into policy information is defined as policy information for act command, i.e., when control module connects When receiving the signal of act command, determined whether to select information to export independent chip selection signal according to independent piece according to the policy information.Ying Li Solution, in the present embodiment, similar operations is used to chip selection signal and clock enable signal, for example, to independent chip selection signal and list The definition of the policy information of only clock enable signal is for same control command, however, it is also possible to be defined as not With the policy information of control command.

450, control module receive bus line command signal in control command signal, chip selection signal, clock enable signal with And indication signal.

460, control module determines to handle the chip selection signal according to chip selection signal and indication signal, and according to clock Enable signal and indication signal determine to handle clock enable signal.

Control module is used for the information deposited according to registration module, generates and exports each dram chip in DIMM memory bars Independent chip selection signal and independent clock enable signal.

As shown in figure 5, control module 220 selects control module 221 and clock to make energy control module 222 including piece.Deposit mould Block 210 selects registration module 211 and clock to enable registration module 212 including piece.Registration module 210 selects registration module 211 including piece Registration module 212 is enabled with clock be respectively used to deposit piece select relevant information and clock to enable relevant information.The piece selected control molding Block 221 generates and exports the independent chip selection signal of corresponding each dram chip, and the clock generates energy control module 222 and exported The independent clock enable signal of corresponding each dram chip.

470, control module determines policy information be present.

Policy information in registration module be present, therefore strategically information judges control module, it should be appreciated that if do not had Policy information, then information is selected to judge according to independent piece.

480, control module is determined using the policy information for control command signal according to the control command signal of reception.

For example, the policy information corresponding to the act command is present, and policy information instruction selects information according to independent piece Output information signal is enabled with independent, therefore control module is not to select information and the enabled letter of predetermined clock according to predetermined piece Breath output, but select information and independent clock to enable information and export independent chip selection signal and the enabled letter of independent clock according to independent piece Number.

490, control module exports independent chip selection signal and independent clock enable signal to memory chip.

Independent chip selection signal and independent clock enable signal corresponding to each memory chip reception.For example, corresponding internal memory The independent chip selection signal of chip indicates the chip in the case of write operation order in not selected state, then memory chip reception To after the signal, without write operation.

It should be understood that registration module, which can not also deposit independent clock, enables information, correspondingly, control module can not also be right Clock enable signal processes, i.e., unfavorable to generate independent clock enable signal with clock enable signal.

Fig. 6 is the flow chart of the control method of chip controller according to an embodiment of the invention.In the present embodiment, it is Description succinctly with conveniently, only by taking the chip selection signal as an example.Judgement of the control module to clock enable signal and to chip selection signal and What is operated is similar, will not be repeated here.It should also be understood that dram chip of the present embodiment using DIMM forms, but the present invention Embodiment is not limited to this.

610, the signal of bus, including address signal, indication signal, chip selection signal and control are received from Memory Controller Hub Command signal.

620, judge whether to handle chip selection signal according to chip selection signal and indication signal.

Specifically, in chip selection signal and all effective indication signal, represent that chip controller is carried out to the chip selection signal Processing.In other words, the chip selection signal is the order of the dram chip in the DIMM controlled for the chip controller.Work as piece When effective when selecting signal and indication signal difference, represent that the chip controller does not do any processing to chip selection signal.If it is determined that Result be yes, then perform 640, if it is determined that result be no, then perform 630.

630, chip selection signal is output to memory chip by chip controller, without generating and not exporting independent piece choosing letter Number, i.e., independent chip selection signal is non-selected state.

640, chip controller selection processing chip selection signal, further, control module judges this control by registration module Whether system order has corresponding policy information.If it is determined that result be yes, that is, predetermined policy information be present, then perform 660, If it is determined that result be no, i.e., in the absence of predetermined policy information, then perform 650.

650, control module selects information to generate and exports independent chip selection signal according to independent piece.

660, control module judges to select information to export according to independent piece or select letter according to predetermined piece according to policy information Breath output.For example, it can be default information that predetermined piece, which selects information,.

670, if policy information instruction selects information to export according to predetermined piece, for example, according to default information, then control mould Block generates according to default information and exports corresponding signal.Specifically, default information can be set to indicate that all independent Chip selection signal all indicates effectively, and ignores independent piece and select information.Stated differently, since multiple individually pieces select information all to indicate Effect, the situation that multiple memory chips receive multiple individually chip selection signals is similar to the situation for receiving chip selection signal, Suo Youdan Only chip selection signal all indicates that corresponding memory chip is operated, for example, entering the operation such as line activating or refreshing.If policy information Instruction does not export according to acquiescence, then control module performs 650, i.e. control module is selected information to generate and exported individually according to independent piece Chip selection signal.

Fig. 7 is the indicative flowchart of the method for control memory chip according to an embodiment of the invention.Fig. 7 side Method is performed by chip controller, including herein below.

710, chip controller receives the first chip selection signal of Memory Controller Hub output.

720, chip controller selects information generation more according to the independent piece deposited in the first chip selection signal and chip controller Individual independent chip selection signal, plurality of individually chip selection signal correspond with multiple memory chips, and the first chip selection signal is used to refer to Show the multiple memory chips of selection, independent piece selects information to be used to indicate individually to select at least one internal memory core in multiple memory chips Piece.

730, chip controller exports multiple independent chip selection signals to multiple memory chips respectively, so as to multiple memory chips In the control command signal that is exported according to Memory Controller Hub of at least one memory chip perform it is corresponding with control command signal Operation.

Therefore, technical scheme selects information by depositing independent piece in chip controller, according to from internal memory control The chip selection signal and the independent piece of deposit that device processed receives select information to generate multiple independent chip selection signals, and respectively to multiple interior Deposit chip and export multiple independent chip selection signals.Information is selected due to having deposited independent piece in chip controller, therefore without internal memory control Device processed sends independent piece for each order and selects information, so as to reduce the occupancy to transmission bandwidth.

Alternatively, as another embodiment, deposited in chip controller according in the first chip selection signal and chip controller Independent piece select information generation multiple individually before chip selection signals, Fig. 7 method also includes：Chip controller receives Memory control First address signal of device output, the first address signal carry independent piece and select information and independent piece to select the address information of information；Core Piece controller deposits independent piece according to the first address signal and selects information.

According to an embodiment of the invention, the first address signal also carrying sheets selects policy information, and piece selects policy information to be deposited with Select information corresponding in chip controller and with independent piece, piece selects policy information to be used to indicate that independent piece selects information for control Whether command signal is effective, wherein, method also includes：Chip controller receives the control command signal of Memory Controller Hub output, Wherein, chip controller selects information to generate multiple independent pieces according to the independent piece deposited in the first chip selection signal and chip controller Signal is selected, including：As chankings selects policy information to indicate that independent piece selects information effective for control command signal, then chip controller Information is selected to generate multiple independent chip selection signals according to the first chip selection signal and independent piece.

Alternatively, also include as another embodiment, Fig. 7 method：As chankings selects policy information to indicate independent piece choosing letter Breath is directed to control command invalidating signal, then chip controller selects information to generate multiple lists according to the first chip selection signal and predetermined piece Only chip selection signal, predetermined piece select multiple memory chips corresponding to multiple individually chip selection signal selections of information instruction generation.

Alternatively, also include as another embodiment, Fig. 7 method：Chip controller receives Memory Controller Hub output Second independent piece selects indication signal and the second chip selection signal, wherein the second independent piece selects indication signal and the second chip selection signal to combine Instruction chip controller deposits independent piece according to the first address signal and selects information.

Alternatively, also include as another embodiment, Fig. 7 method：Chip controller receives Memory Controller Hub output First independent piece selects indication signal, wherein the first independent piece selects indication signal and the first chip selection signal joint instructions chip controller Independent piece according to being deposited in the first chip selection signal and chip controller selects information to generate multiple independent chip selection signals.

Alternatively, also include as another embodiment, Fig. 7 method：Chip controller receives Memory Controller Hub output First clock enable signal；Chip controller makes according to the independent clock deposited in the first clock enable signal and chip controller The multiple individually clock enable signals of energy information generation, multiple individually clock enable signals and multiple memory chips one-to-one corresponding, the One clock enable signal is used for the clock signal for controlling multiple memory chips, and multiple individually clock enable signals are respectively used to individually Control the clock signal of at least one chip in multiple memory chips；Chip controller exports more to multiple memory chips respectively Individual individually clock enable signal.

Alternatively, as another embodiment, in chip controller according in the first clock enable signal and chip controller Before the independent clock of deposit enables the multiple individually clock enable signals of information generation, Fig. 7 method also includes：Chip controller The second address signal of Memory Controller Hub output is received, address signal carries independent clock and enables information and the enabled letter of independent clock The address information of breath, the second address signal carry the address information that independent clock enables information and independent clock enables information；Core Piece controller deposits independent clock according to the second address signal and enables information.

According to an embodiment of the invention, the second address signal also carries clock and enables policy information, the enabled strategy letter of clock Breath be deposited with chip controller and with independent clock enable information it is corresponding, clock enable policy information be used for indicate individually Whether the enabled information of clock is effective for control command signal, wherein, method also includes：Chip controller receives Memory Controller Hub The control command signal of output, wherein chip controller are independent according to being deposited in the first clock enable signal and chip controller Clock enables the multiple individually clock enable signals of information generation, including：If clock enables policy information and indicates that independent clock makes Energy information is effective, then chip controller enables information according to the first clock enable signal and independent clock and generates multiple independent clocks Enable signal.

Alternatively, also include as another embodiment, Fig. 7 method：If the enabled policy information instruction of clock is independent Clock enables information and is directed to control command invalidating signal, then chip controller makes according to the first clock enable signal and predetermined clock The multiple individually clock enable signals of energy information generation, multiple internal memory cores corresponding to multiple individually clock enable signals selections of generation Piece.

Alternatively, also include as another embodiment, Fig. 7 method：Chip controller receives Memory Controller Hub output Second independent clock enables indication signal and second clock enable signal, wherein the second independent clock enables indication signal and second Clock enable signal joint instructions chip controller deposits independent clock according to the second address signal and enables information.

Alternatively, also include as another embodiment, Fig. 7 method：Chip controller receives Memory Controller Hub output First clock enables indication signal, wherein the first clock enables indication signal and the first clock enable signal joint instructions chip control Device processed enables information according to the independent clock deposited in the first clock enable signal and chip controller and generates multiple independent clocks Enable signal.

Fig. 8 is the indicative flowchart of the method for control memory chip according to another embodiment of the present invention.Fig. 8 side Method is performed by Memory Controller Hub, including herein below.

810, Memory Controller Hub exports the first chip selection signal to chip controller and the first independent piece selects indication signal, wherein First independent piece selects indication signal and the first chip selection signal joint instructions chip controller according to the first chip selection signal and chip control The independent piece deposited in device processed selects information to generate multiple independent chip selection signals, and independent piece selects information to be used to generate multiple individually piece choosings Signal, multiple individually chip selection signals correspond with multiple memory chips, and the first chip selection signal is used to indicate to select multiple internal memories Chip, independent piece select information to be used to indicate individually to select at least one memory chip in multiple memory chips.

820, Memory Controller Hub to multiple memory chip output control command signals, so as in multiple memory chips at least Multiple individually chip selection signals that one memory chip exports according to chip controls perform operation corresponding with control command signal.

Alternatively, also include as another embodiment, Fig. 8 method：Memory Controller Hub exports first to chip controller Address signal, address signal carry independent piece and select information and independent piece to select the address information of information.

According to an embodiment of the invention, address signal also carrying sheets selects policy information, and piece selects policy information to be used to indicate list Whether only piece selects information effective for control command signal, wherein, method also includes：Memory Controller Hub exports to chip controller Control command signal.

Alternatively, also include as another embodiment, Fig. 8 method：Memory Controller Hub exports second to chip controller Independent piece selects indication signal and the second chip selection signal, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions Chip controller deposits independent piece according to address information and selects information.

Alternatively, also include as another embodiment, Fig. 8 method：Memory Controller Hub exports first to chip controller Clock enable signal and the first independent clock enable indication signal, wherein the first clock enables indication signal and the first clock enables Combined signal indicates chip controller according to the enabled letter of the independent clock deposited in the first clock enable signal and chip controller The multiple individually clock enable signals of breath generation, independent clock enables information and is used to generate multiple individually clock enable signals, multiple Independent clock enable signal corresponds with multiple memory chips, and the first clock enable signal is used to control multiple memory chips Clock signal, multiple individually clock enable signals be respectively used to individually control at least one chip in multiple memory chips when Clock signal.

Alternatively, also include as another embodiment, Fig. 8 method：Memory Controller Hub exports second to chip controller Address signal, the second address signal carry the address information that independent clock enables information and independent clock enables information.

According to an embodiment of the invention, address signal also carries clock and enables policy information, and clock enables policy information and used It is whether effective for control command signal that information is enabled in the independent clock of instruction.

Alternatively, also include as another embodiment, Fig. 8 method：Memory Controller Hub exports second to chip controller Independent clock enables indication signal and second clock enable signal, wherein the second independent clock enables indication signal and second clock Enable signal joint instructions chip controller deposits independent clock according to the second address signal and enables information.

Fig. 9 is the schematic diagram of chip controller according to an embodiment of the invention.Chip controller 900 wraps Include：Register 910 and controller 920, register 910 are connected with controller 920, and wherein register 910 is used to deposit individually Piece selects information；Controller 920 is used for：Receive the first chip selection signal of Memory Controller Hub output；According to the first chip selection signal and defeated The independent piece for going out register deposit selects information to generate multiple independent chip selection signals, plurality of individually chip selection signal and multiple internal memories Chip corresponds, and the first chip selection signal is used to indicate to select multiple memory chips, and independent piece selects information to be used to indicate individually to select Select at least one memory chip in multiple memory chips；Multiple independent chip selection signals are exported to multiple memory chips respectively, with Just the control command signal that at least one memory chip in multiple memory chips exports according to Memory Controller Hub performs and control Operated corresponding to command signal.

According to an embodiment of the invention, register is additionally operable to：Deposited in controller according to the first chip selection signal and register Independent piece select information generation multiple individually before chip selection signals, receive the first address signal of Memory Controller Hub output, first Address signal carries independent piece and selects information and independent piece to select the address information of information；Independent piece choosing is deposited according to the first address signal Information.

According to an embodiment of the invention, the first address signal also carrying sheets selects policy information, and piece selects policy information to be deposited with Select information corresponding in chip controller and with independent piece, piece selects policy information to be used to indicate that independent piece selects information for control Whether command signal is effective, and controller is additionally operable to receive the control command signal of Memory Controller Hub output, is believed according to first choosing Number and chip controller in the independent piece deposited select information to generate multiple independent chip selection signals, including：As chankings selects policy information Indicate that independent piece selects information effective for control command signal, then select information generation multiple according to the first chip selection signal and independent piece Independent chip selection signal；As chankings selects policy information to indicate that independent piece selects information to be directed to control command invalidating signal, then according to first Chip selection signal and predetermined piece select information to generate multiple independent chip selection signals, and predetermined piece selects the multiple independent of information instruction generation Multiple memory chips corresponding to chip selection signal selection.

According to an embodiment of the invention, register is additionally operable to receive the second independent piece choosing instruction letter of Memory Controller Hub output Number and the second chip selection signal, wherein the second independent piece select indication signal and the second chip selection signal joint instructions chip controller according to First address signal deposits independent piece and selects information.

According to an embodiment of the invention, controller is additionally operable to receive the first independent piece choosing instruction letter of Memory Controller Hub output Number, wherein the first independent piece select indication signal and the first chip selection signal joint instructions chip controller according to the first chip selection signal and The independent piece deposited in chip controller selects information to generate multiple independent chip selection signals.

According to an embodiment of the invention, controller is additionally operable to receive the enabled instruction letter of the first clock of Memory Controller Hub output Number, the first clock enable signal, the first clock enables indication signal and the first clock enable signal joint instructions chip controller The multiple individually clocks of information generation are enabled according to the independent clock deposited in the first clock enable signal and chip controller to enable Signal, the second independent clock that register is additionally operable to receive Memory Controller Hub output enable the enabled letter of indication signal, second clock Number and the second address signal, the second independent clock enable indication signal and second clock enable signal joint instructions chip controller Independent clock is deposited according to the second address signal and enables information, the second address signal carry independent clock enable information, it is independent when Clock enables the address information of information.

Figure 10 is the schematic diagram of internal memory according to an embodiment of the invention.Internal memory 1000 includes：In multiple Deposit chip 1010 and the chip controller 900 such as Fig. 9.

Figure 11 is the schematic diagram of Memory Controller Hub according to an embodiment of the invention.Memory Controller Hub 1100, including：Processor 1110 and transmitter 1120, wherein processor 1110 are connected with transmitter 1120, processor 1110 For generating the first chip selection signal, the first independent piece selects indication signal and control command signal；Transmitter 1120, for chip Controller exports the first chip selection signal and the first independent piece selects indication signal, wherein the first independent piece selects indication signal and first Combined signal instruction chip controller is selected to select information to generate according to the independent piece deposited in the first chip selection signal and chip controller Multiple independent chip selection signals, independent piece select information to be used to generate multiple independent chip selection signals, multiple individually chip selection signals with it is multiple Memory chip corresponds, and the first chip selection signal is for, to the multiple memory chips of selection are shown, independent piece to select information to be used in referring to Instruction individually selects the few memory chip of multiple memory chips, wherein, transmitter 1120 is additionally operable to defeated to multiple memory chips Go out control command signal, so as at least one memory chip in multiple memory chips according to chip controls export it is multiple individually Chip selection signal performs operation corresponding with control command signal.

According to an embodiment of the invention, transmitter is additionally operable to export the first address signal, address signal to chip controller Carry the address information that independent piece selects information and independent piece selects information.

According to an embodiment of the invention, address signal also carrying sheets selects policy information, and piece selects policy information to be used to indicate list Whether only piece selects information effective for control command signal, wherein, transmitter is additionally operable to chip controller output control order Signal.

According to an embodiment of the invention, transmitter be additionally operable to chip controller export the second independent piece select indication signal and Second chip selection signal, wherein the second independent piece selects indication signal and the second chip selection signal joint instructions chip controller according to address Information deposits independent piece and selects information.

According to an embodiment of the invention, transmitter be additionally operable to chip controller export the second independent piece select indication signal and Second chip selection signal, the second independent piece select indication signal and the second chip selection signal joint instructions chip controller according to address information Post and state independent piece and select information.

The terms "and/or", only a kind of incidence relation for describing affiliated partner, expression may have three kinds of passes System, for example, A and/or B, can be represented：Individualism A, while A and B be present, these three situations of individualism B.In addition, herein Middle character "/", it is a kind of relation of "or" to typically represent forward-backward correlation object.

Those of ordinary skill in the art are it is to be appreciated that the list of each example described with reference to the embodiments described herein Member and algorithm steps, it can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware With the interchangeability of software, the composition and step of each example are generally described according to function in the above description.This A little functions are performed with hardware or software mode actually, application-specific and design constraint depending on technical scheme.Specially Industry technical staff can realize described function using distinct methods to each specific application, but this realization is not It is considered as beyond the scope of this invention.

It is apparent to those skilled in the art that for convenience of description and succinctly, foregoing description is The specific work process of system, device and unit, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.

In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, can be with Realize by another way.For example, device embodiment described above is only schematical, for example, the unit Division, only a kind of division of logic function, can there is other dividing mode, such as multiple units or component when actually realizing Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.In addition, shown or beg for The mutual coupling of opinion or direct-coupling or communication connection can be the INDIRECT COUPLINGs by some interfaces, device or unit Or communication connection or electricity, the connection of mechanical or other forms.

The unit illustrated as separating component can be or may not be physically separate, show as unit The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple On NE.Some or all of unit therein can be selected to realize scheme of the embodiment of the present invention according to the actual needs Purpose.

In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can also It is that unit is individually physically present or two or more units are integrated in a unit.It is above-mentioned integrated Unit can both be realized in the form of hardware, can also be realized in the form of SFU software functional unit.

Through the above description of the embodiments, it is apparent to those skilled in the art that the present invention can be with Realized with hardware, or firmware is realized, or combinations thereof mode is realized.When implemented in software, can be by above-mentioned function It is stored in computer-readable medium or is transmitted as one or more instructions on computer-readable medium or code.Meter Calculation machine computer-readable recording medium includes computer-readable storage medium and communication media, and wherein communication media includes being easy to from a place to another Any medium of individual place transmission computer program.Storage medium can be any usable medium that computer can access.With Exemplified by this but it is not limited to：Computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storages, disk Storage medium or other magnetic storage apparatus or can be used in carrying or store with instruction or data structure form expectation Program code and can be by any other medium of computer access.In addition.Any connection can be suitably turn into computer Computer-readable recording medium.For example, if software is using coaxial cable, optical fiber cable, twisted-pair feeder, Digital Subscriber Line（DSL）Or such as The wireless technology of infrared ray, radio and microwave etc is transmitted from website, server or other remote sources, then coaxial electrical The wireless technology of cable, optical fiber cable, twisted-pair feeder, DSL or such as infrared ray, wireless and microwave etc is included in affiliated medium In fixing.As used in the present invention, disk（Disk）And dish（disc）Including compressing laser disc（CD）, laser disc, laser disc, numeral it is logical Use laser disc（DVD）, floppy disk and Blu-ray Disc, the replicate data of the usual magnetic of which disk, and dish is then with laser come optical duplication Data.Above combination above should also be as being included within the protection domain of computer-readable medium.

In a word, the preferred embodiment of technical solution of the present invention is the foregoing is only, is not intended to limit the present invention's Protection domain.It is all the present invention principle within, any modification, equivalent substitution and improvements made etc., should be included in the present invention Protection domain within.

Claims

A kind of 1. chip controller, it is characterised in that including：

Registration module, information is selected for depositing independent piece；

Control module, it is used for：Receive the first chip selection signal of Memory Controller Hub output；According to first chip selection signal and described The independent piece of registration module deposit selects information to generate multiple independent chip selection signals, wherein the multiple individually chip selection signal with it is multiple Memory chip corresponds, and first chip selection signal is used to indicate to select the multiple memory chip, the individually piece choosing letter Cease for indicating individually to select at least one memory chip in the multiple memory chip；Exported respectively to multiple memory chips The multiple independent chip selection signal, so that at least one memory chip in the multiple memory chip is according to the Memory control The control command signal of device output performs operation corresponding with the control command signal.
2. chip controller according to claim 1, it is characterised in that the registration module is additionally operable to：In the control The independent piece that module is deposited according to first chip selection signal and the registration module selects information to generate multiple independent chip selection signals Before,

The first address signal of the Memory Controller Hub output is received, first address signal carries the individually piece and selects information The address information of information is selected with the individually piece；

Information is selected according to the first address signal deposit individually piece.
3. chip controller according to claim 2, it is characterised in that first address signal also carrying sheets choosing strategy Information, described is selected policy information to be deposited with the chip controller and selects information corresponding with the individually piece, described Piece selects policy information to be used to indicate that the individually piece selects information whether effective for the control command signal, the control module It is additionally operable to receive the control command signal of the Memory Controller Hub output,

It is described to select information generation multiple individually according to the independent piece deposited in first chip selection signal and the chip controller Chip selection signal, including：

If described is selected the policy information instruction individually piece to select information effective for the control command signal, according to institute State the first chip selection signal and the individually piece selects information to generate the multiple independent chip selection signal；

If described is selected the policy information instruction individually piece to select information to be directed to the control command invalidating signal, according to institute State the first chip selection signal and predetermined piece selects information to generate multiple independent chip selection signals, the predetermined piece selects information instruction generation It is the multiple individually chip selection signal selection corresponding to the multiple memory chip.
4. the chip controller according to Claims 2 or 3, it is characterised in that the registration module is additionally operable to described in reception Second independent piece of Memory Controller Hub output selects indication signal and the second chip selection signal, wherein the second independent piece choosing instruction letter Number and the second chip selection signal joint instructions described in chip controller the independent piece is deposited according to first address signal Select information.
5. according to the chip controller described in any one of claim 1-3, it is characterised in that the control module is additionally operable to The the first independent piece for receiving the Memory Controller Hub output selects indication signal, wherein the first independent piece selects indication signal and institute Chip controller described in the first chip selection signal joint instructions is stated to post according in first chip selection signal and the chip controller The independent piece deposited selects information to generate the multiple independent chip selection signal.
6. according to the chip controller described in any one of claim 1-3, it is characterised in that

The first clock that the control module is additionally operable to receive the Memory Controller Hub output enables indication signal, the first clock makes Energy signal, first clock enable chip controller root described in indication signal and the first clock enable signal joint instructions Information, which is enabled, according to the independent clock deposited in the first clock enable signal and the chip controller generates the multiple list Only clock enable signal,

When the registration module is additionally operable to receive the enabled indication signal of the second independent clock of the Memory Controller Hub output, second Clock enable signal and the second address signal, the second independent clock enable indication signal and second clock enable signal connection Close and indicate that the chip controller enables information, second address according to the second address signal deposit individually clock Signal carries the address information that independent clock enables information, the individually clock enables information.
A kind of 7. internal memory, it is characterised in that including：Multiple memory chips and the core as described in any one of claim 1 to 6 Piece controller.
A kind of 8. Memory Controller Hub, it is characterised in that including：

Generation module, for generating the first chip selection signal, the first independent piece selects indication signal and control command signal, wherein described First independent piece selects indication signal and the first chip selection signal joint instructions chip controller according to first chip selection signal Information is selected to generate multiple independent chip selection signals with the independent piece deposited in the chip controller,

Output module, it is described for selecting indication signal to the chip controller the first chip selection signal of output and the first independent piece Independent piece selects information to be used to generating multiple independent chip selection signals, a pair of the multiple individually chip selection signal and multiple memory chips 1 Should, first chip selection signal is used to indicate to select the multiple memory chip, and the individually piece selects information to be used to indicate individually At least one memory chip in the multiple memory chip is selected,

The output module is additionally operable to the multiple memory chip output control command signal, so as to the multiple memory chip In at least one memory chip according to the chip controller export it is multiple individually chip selection signals perform with it is described control order Make and being operated corresponding to signal.
9. Memory Controller Hub according to claim 8, it is characterised in that the output module is additionally operable to the chip control Device processed exports the first address signal, and the address signal carries the address that the individually piece selects information and the individually piece selects information Information.
10. Memory Controller Hub according to claim 9, it is characterised in that the address signal also carrying sheets choosing strategy letter Breath, described is selected policy information to be used to indicate that the individually piece selects information whether effective for the control command signal,

The output module is additionally operable to export the control command signal to the chip controller.
11. according to the Memory Controller Hub described in any one of claim 9-10, it is characterised in that

The output module is additionally operable to select indication signal and the second chip selection signal to the chip controller the second independent piece of output, Wherein described second independent piece selects chip controller described in indication signal and the second chip selection signal joint instructions according to The address information deposit individually piece selects information.
A kind of 12. method for controlling internal memory, it is characterised in that including：

Chip controller receives the first chip selection signal of Memory Controller Hub output；

The chip controller selects information to give birth to according to the independent piece deposited in first chip selection signal and the chip controller Into multiple independent chip selection signals, wherein the multiple individually chip selection signal corresponds with multiple memory chips, described first Select signal be used for indicate select the multiple memory chip, the individually piece select information be used to indicating individually selecting it is the multiple interior Deposit at least one memory chip in chip；

The chip controller exports the multiple independent chip selection signal to the multiple memory chip respectively, so as to the multiple The control command signal that at least one memory chip in memory chip exports according to the Memory Controller Hub performs and the control Operated corresponding to command signal processed.
13. according to the method for claim 12, it is characterised in that believed in the chip controller according to described first choosing Number and the chip controller in before the independent piece deposited selects the multiple individually chip selection signals of information generation, methods described is also wrapped Include：

The chip controller receives the first address signal of the Memory Controller Hub output, and first address signal carries institute State the address information that independent piece selects information and the individually piece selects information；

The chip controller selects information according to the first address signal deposit individually piece.
14. according to the method for claim 13, it is characterised in that first address signal also carrying sheets choosing strategy letter Breath, described is selected policy information to be deposited with the chip controller and selects information corresponding with the individually piece, described Policy information is selected to be used to indicate that the individually piece selects information whether effective for the control command signal,

Wherein, methods described also includes：

The chip controller receives the control command signal of the Memory Controller Hub output,

Wherein, the chip controller selects letter according to the independent piece deposited in first chip selection signal and the chip controller Breath generates multiple independent chip selection signals, including：

If described is selected the policy information instruction individually piece to select information effective for the control command signal, the core Piece controller selects information to generate the multiple independent chip selection signal according to first chip selection signal and the individually piece；

If described is selected the policy information instruction individually piece to select information to be directed to the control command invalidating signal, the core Piece controller selects information to generate multiple independent chip selection signals, the predetermined piece according to first chip selection signal and predetermined piece Select the multiple memory chip corresponding to the multiple individually chip selection signal selection of information instruction generation.
15. the method according to claim 13 or 14, it is characterised in that also include：

The second independent piece that the chip controller receives the Memory Controller Hub output selects indication signal and the second chip selection signal, Wherein described second independent piece selects chip controller described in indication signal and the second chip selection signal joint instructions according to The first address signal deposit individually piece selects information.
16. according to the method described in any one of claim 12-14, it is characterised in that also include：

The first independent piece that the chip controller receives the Memory Controller Hub output selects indication signal, wherein described first is single Only piece select chip controller described in indication signal and the first chip selection signal joint instructions according to first chip selection signal and The independent piece deposited in the chip controller selects information to generate the multiple independent chip selection signal.
17. according to the method described in any one of claim 12-14, it is characterised in that also include：

The first clock that the chip controller receives the Memory Controller Hub output enables the enabled letter of indication signal, the first clock Number, the second independent clock enables indication signal, second clock enable signal and the second address signal, wherein first clock makes Chip controller described in energy indication signal and the first clock enable signal joint instructions is according to the enabled letter of first clock Number and the chip controller in the independent clock deposited enable the multiple individually clock enable signal of information generation, described the Two independent clocks enable chip controller described in indication signal and the second clock enable signal joint instructions according to described the The double-address signal deposit individually clock enables information, and second address signal carries independent clock and enables information, described Independent clock enables the address information of information.
A kind of 18. method for controlling memory chip, it is characterised in that including：

Memory Controller Hub exports the first chip selection signal and the first independent piece to chip controller and selects indication signal, wherein, described the One independent piece select indication signal and the first chip selection signal joint instructions chip controller according to first chip selection signal and The independent piece deposited in the chip controller selects information to generate multiple independent chip selection signals, and the individually piece selects information to be used to give birth to Into multiple independent chip selection signals, the multiple individually chip selection signal corresponds with multiple memory chips, first choosing letter Number it is used to indicate to select the multiple memory chip, the individually piece selects information to be used to indicate individually to select the multiple internal memory core At least one memory chip in piece；

The Memory Controller Hub is to the multiple memory chip output control command signal, so as in the multiple memory chip Multiple individually chip selection signals that at least one memory chip exports according to the chip controls perform and the control command signal Corresponding operation.
19. according to the method for claim 18, it is characterised in that also include：

The Memory Controller Hub exports the first address signal to the chip controller, and the address signal carries the independent piece Information and the individually piece is selected to select the address information of information.
20. according to the method for claim 19, it is characterised in that the address signal also carrying sheets selects policy information, institute Stating piece selects policy information to be used to indicate that the individually piece selects information whether effective for the control command signal,

Methods described also includes：The Memory Controller Hub exports the control command signal to the chip controller.
21. according to the method described in any one of claim 19-20, it is characterised in that also include：

The Memory Controller Hub exports the second independent piece to the chip controller and selects indication signal and the second chip selection signal, wherein The second independent piece selects chip controller described in indication signal and the second chip selection signal joint instructions according to the address The information deposit individually piece selects information.