WO2019000456A1

WO2019000456A1 - Data mask transmission method, memory controller, memory chip, and computer system

Info

Publication number: WO2019000456A1
Application number: PCT/CN2017/091331
Authority: WO
Inventors: 肖世海; 朗诺斯弗洛里安; 杨伟
Original assignee: 华为技术有限公司
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03
Also published as: CN110720126A; CN110720126B

Abstract

The present application provides a data mask (DM) transmission method, a memory controller, a memory chip, and a computer system. The method comprises: a memory controller transmits a first write command to a memory chip, wherein the first write command comprises first indication information, the first indication information is used to indicate that data blocks to be written comprise a masked data block, the number of data blocks to be written is N, wherein N is an integer greater than or equal to 2; and the memory controller sends, according to the first write command, the N data blocks to the memory chip, wherein one of the N data blocks is a first DM information block, the first DM information block is used to indicate the location of the masked data block in the data blocks to be written, and the N data blocks comprise a non-masked data block among the data blocks to be written. The embodiments of the present application realize transmission of a DM without adding a pin.

Description

Method for transmitting data mask, memory controller, memory chip and computer system

Technical field

The present application relates to the field of computers and, more particularly, to a method of transmitting a data mask, a memory chip, and a computer system.

Background technique

The most commonly used storage medium in existing computer memory is dynamic random access memory (DRAM). The memory of the computer is often in the form of dual inline memory modules (DIMMs), and the memory controller and the DIMM are generally connected by a double data rate (DDR) bus. The memory controller can access the data in the DRAM through the DDR bus between the memory controller and the DIMM.

The DDR DRAM memory chip usually has a data mask (DM) pin, and the DM pin is used to indicate whether the write data of the current cycle is masked. For example, the DDR4 standard has a DM_n pin, and when the DM_n pin is low, it indicates that the data currently sampled at the same time as the DM_n pin is invalid. However, the ×4 DRAM (that is, the bit width of the DRAM chip is 4 bits) does not have the DM function. The DIMMs composed of ×4 DRAMs have high capacity and are usually used in servers with high performance requirements. If there is a way to solve the DM transmission of ×4 DRAM without increasing the pins, it will be beneficial to improve the performance of the server.

Therefore, how to realize the transmission of DM without increasing the pin has become an urgent problem to be solved.

Summary of the invention

The application provides a method for transmitting a data mask, a memory controller, a memory chip and a computer system, which can realize the transmission of the DM without increasing the pin.

The first aspect provides a method for transmitting a data mask DM, the method includes: the memory controller sends a first write command to the memory chip, where the first write command includes first indication information, where the first The indication information is used to indicate that the data block to be written has a mask data block, the number of the data block to be written is N, N is an integer greater than or equal to 2; the memory controller is configured according to the first write command Sending N data blocks to the memory chip, where one of the N data blocks is a first DM information block, the first DM information block is used to indicate mask data in the data block to be written The location of the block, the N data blocks including non-masked data blocks in the data block to be written.

Therefore, in the embodiment of the present application, by using one of the N data blocks to be transmitted as a DM information block, the transmission of the DM is implemented without adding a pin, and the N data blocks include data to be written. The non-masked data block in the block can ensure the transmission of the useful data, realizes the transmission of the DM without increasing the amount of data transmitted, can avoid additional transmission time, and saves transmission resources.

It should be understood that, in this embodiment of the present application, the first DM information block may include N bits of DM information, where the N bits have a one-to-one correspondence with the N data blocks to be written. That is to say, each bit in the DM information corresponds to a data block to be written (which may also be referred to as an original data block).

Through the first DM information, the memory controller can notify the memory chip which of the N data blocks to be written are mask data blocks and which are non-mask data blocks. For example, the corresponding bit of the data block to be written is 0, it can be said that the data block to be written is a non-masked data block, and when the bit corresponding to the data block to be written is 1, it can indicate that the data block to be written is a mask data block.

It should be understood that the first DM information block may be any one of the N data blocks that are sent, which is not limited by the embodiment of the present application.

It should be understood that the memory chip in the embodiment of the present application may include a DRAM chip, a phase change memory (PCM) chip, or a resistive random access memory (RRAM) chip, etc., and the embodiment of the present application is not limited thereto. .

Optionally, in an implementation manner of the first aspect, the first DM information block is the first data block of the N data blocks.

In the embodiment of the present application, the DM information is transmitted in the first data block, so that the memory chip can know whether the subsequently received data block is a mask block according to the DM information, so that after receiving the data block, if the data is received, The block is a non-masked data block, and the memory chip can directly write the non-masked data block into the storage medium of the memory chip, and can improve the writing efficiency without waiting for other data blocks to be received.

It should be understood that, in the embodiment of the present application, the storage medium may also be referred to as a storage array, and the embodiment of the present application is not limited thereto.

Optionally, in an implementation manner of the first aspect, the first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N; The 2nd to nth data blocks in the data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th to the Nth data in the N data blocks The block is the n+1th to Nthth data block in the data block to be written.

That is, the N data blocks sent by the memory controller to the memory chip do not include the first one of the N data blocks to be written, and the N data blocks include the first DM information block and the N All data blocks except the first masked data block in the data block to be written.

It should be understood that the data block to be written in the embodiment of the present application may also be referred to as an original data block, and the N data blocks to be written may be referred to as N original data blocks, and the DM information blocks are not included in the N original data blocks. The N data blocks to be written are different from the N data blocks (the actually transmitted data blocks) sent by the memory controller, and the transmitted N data blocks include DM information blocks.

Specifically, the memory controller may send the DM information according to the following preset rule: firstly, the DM information is transmitted, and then the memory controller finds the first mask data block in the data block to be written according to the DM information, that is, to be written. The incoming data block 3, the data before the first masked mask data block (ie, the data block 1 and the data block 2 to be written) are sequentially transmitted after the DM information, that is, the transmitted data. Block 2 and data block 3 correspond to data block 1 and data block 2 to be written, and then the first mask data block is not transmitted, and the data after the first mask data block, that is, the data block to be written 4 To 8, according to the location of the original data, send in order.

Therefore, the embodiment of the present application discards the data of the first mask data block in the data block corresponding to the transmission BL (which may be referred to as a data block or an original data block to be written), by adding a DM information block, The transmission of the DM is realized on the basis of not increasing the amount of data transmitted, avoiding additional transmission time and saving transmission resources.

It should be understood that in the first case described above, the case where the memory controller does not transmit the first mask data block is described, but the embodiment of the present application is not limited thereto. For example, in practical applications, the memory controller may not The last masked data block is transmitted, that is, the transmitted N data blocks include all of the first DM information block and the data blocks to be written except the last mask data block. Correspondingly, the memory controller can transmit the N data blocks according to a similar rule of the first case. To avoid repetition, details are not described herein again.

Optionally, in an implementation manner of the first aspect, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N; the N data blocks The 2nd to Z+1th data blocks in the The Z non-masked data blocks, when Z is less than or equal to N-2, the Z+2th to Nth data blocks of the N data blocks are preset data blocks.

That is to say, the N data blocks (the actually transmitted N data blocks) sent by the memory controller to the memory chip do not include the mask data in the N data blocks to be written (which may also be referred to as original data blocks). Block, the N data blocks include a first DM information block and all non-masked data blocks in the N data blocks to be written and a preset data block.

It should be understood that when only one masked data block is included in the data block to be written, the transmitted N data blocks include the first DM information block and the N-1 non-masked data blocks. When the data block to be written includes multiple mask data blocks, for example, including NZ mask data blocks, the transmitted N data blocks include the first DM information block and the Z non-mask databases. Block and NZ-1 preset data blocks.

Specifically, the memory controller may send the DM information according to the following preset rule: firstly, the DM information is transmitted, and then the memory controller determines, according to the DM information, whether each data block to be written is a masked data block, if it is a mask data. The block is not transmitted, and if it is a non-masked data block, it is transmitted along with the previously transmitted data block. After the non-masked block transmission is completed, the remaining transport blocks may transmit the preset data block. For example, the preset data block includes 8 bits of 0, or 8 bits of 1. The embodiment of the present application is not limited thereto.

Therefore, in the embodiment of the present application, by discarding the data of the first mask data block in the data block corresponding to the transmission BL, by transmitting a DM information block, the DM transmission is realized without increasing the amount of data transmitted. It avoids extra transmission time and saves transmission resources.

Optionally, in an implementation manner of the first aspect, the method further includes: the memory controller sends a second write command to the memory chip; the memory controller sends a P to the memory chip according to the second write command. a data block, one of the P data blocks is a second DM information block, the second DM information block is used to indicate K in the Q data blocks to be written by the memory chip according to the second write command. The position of the masked data block, the P data block includes the non-masked data block of the Q data blocks, wherein the number of the non-masked data blocks in the Q data blocks is M, Q=N , P=Q/2, K is greater than or equal to Q/2+1, and M is an integer greater than 0 and less than or equal to P-1, and M+K=Q.

It should be understood that the second write command may be a write command with a burst chop attribute or a flag, and the burst length corresponding to the second write command is half of the burst length corresponding to the first write command.

Therefore, in the embodiment of the present application, when the number of mask data blocks to be transmitted is greater than or equal to Q/2+1, the useful data block transmission can be completed because at most Q/2 data blocks are needed. Therefore, the present application implements In this case, the burst length is halved, and in the case of implementing DM transmission, the waste of resources is further reduced, and the computer performance can be improved.

The second aspect provides a method for transmitting a data mask DM. It should be understood that the method of the second aspect corresponds to the first aspect, and the second aspect describes the transmission DM of the embodiment of the present application from the memory chip side. The method of the first aspect of the present invention describes a method for transmitting a DM according to an embodiment of the present application. For the corresponding features of the second aspect, reference may be made to the description in the first aspect. To avoid repetition, the detailed description is omitted here.

It should be understood that the memory chip in the embodiment of the present application may include a DRAM chip, a PCM chip, or a RRAM chip, etc., and the embodiment of the present application is not limited thereto.

Specifically, in the second aspect, the method for transmitting the DM includes: receiving, by the memory chip, a first write command sent by the memory controller, where the first write command includes first indication information, where the first indication information is used. Indicates that the data block to be written has a mask data block, the number of the data block to be written is N, N is an integer greater than or equal to 2; the memory chip receives the memory controller according to the first write command Sending N data blocks, where one of the N data blocks is a first DM information block, the first DM information block is used to indicate the data to be written a location of the masked data block in the block, the N data blocks including the non-masked data block in the data block to be written, the memory chip, according to the indication of the first DM information block, the to-be-written The non-masked data block in the data block is written in the storage medium of the memory chip.

Specifically, after acquiring the N data blocks, the memory chip may determine the mask data block and the non-mask data block in the N data blocks to be written according to the DM information, and may decode and receive according to a preset rule. An address of the non-masked data block of the N data blocks in the storage medium of the memory chip, and writing the non-masked data block in the data block to be written into the storage medium according to the decoded address .

Optionally, in an implementation manner of the second aspect, the first DM information block is the first data block of the N data blocks.

Optionally, in an implementation manner of the second aspect, the first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N; The 2nd to nth data blocks in the data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th to the Nth data in the N data blocks The block is the n+1th to Nthth data block in the data block to be written.

Optionally, in an implementation manner of the second aspect, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N; the N data blocks The second to the Z+1th data blocks are the Z non-masked data blocks, and when Z is less than or equal to N-2, the Z+2th to Nth data blocks in the N data blocks are pre- Set the data block.

Optionally, in an implementation manner of the second aspect, the method further includes: the memory chip receiving a second write command sent by the memory controller; the memory chip receiving the memory controller to send according to the second write command P data blocks, one of the P data blocks is a second DM information block, the second DM information block is used to indicate that the memory chip is to be written in the Q data blocks according to the second write command. The position of the K mask data blocks, the P data blocks include non-masked data blocks in the Q data blocks, wherein the number of non-masked data blocks in the Q data blocks is M, Q =N, P=Q/2, K is greater than or equal to Q/2+1, M is an integer greater than 0 and less than or equal to P-1, M+K=Q; the memory chip is in accordance with the indication of the second DM information block And writing the non-masked data block of the Q data blocks to be written into the storage medium.

Specifically, after acquiring the P data blocks, the memory chip may determine the mask data block and the non-mask data block in the N data blocks to be written according to the DM information, and may decode the data according to the preset rule. An address of the non-masked data block in the received P data block in the storage medium of the memory chip, and writing the non-masked data block in the data block to be written into the storage medium according to the decoded address in.

In a third aspect, a memory controller is provided. It should be understood that the memory controller of the third aspect corresponds to the first aspect, and the memory controller is capable of implementing the method implemented by the memory controller in the first aspect, the memory controller For the operation and/or function of each module, refer to the description of the first aspect. In order to avoid repetition, detailed description is omitted here. Said.

Specifically, the memory controller includes: a front end interface connected to a processor in the computer system, the front end interface is configured to receive a write request of the processor, where the write request includes a data block to be written, and the data to be written The number of blocks is N, N is an integer greater than or equal to 2; the memory bus interface is connected to the memory chip through a double rate DDR bus, and the memory bus interface is configured to: send a first write to the memory chip according to the write request a command, the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block, and send N to the memory chip according to the first write command. a data block, wherein one of the N data blocks is a first DM information block, where the first DM information block is used to indicate a location of the mask data block in the N data blocks to be written, The N data blocks include non-masked data blocks in the data block to be written.

Optionally, in an implementation manner of the third aspect, the first DM information block is the first data block of the N data blocks.

Optionally, in an implementation manner of the third aspect, the first mask data block in the data block to be written is the nth data block, where n is greater than 0 and less than or equal to N; the N data The second to nth data blocks in the block are the first to n-1th data blocks in the data block to be written, and the n+1th to Nth data blocks in the N data blocks are The n+1th to Nthth data blocks in the data block to be written.

Optionally, in an implementation manner of the third aspect, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N; the N data blocks The second to the Z+1th data blocks are the Z non-masked data blocks, and when Z is less than or equal to N-2, the Z+2th to Nth data blocks in the N data blocks are pre- Set the data block.

Optionally, in an implementation manner of the third aspect, the memory bus interface is further configured to send a second write command to the memory chip, and send P data blocks to the memory chip according to the second write command, where One of the P data blocks is a second DM information block, and the second DM information block is used to indicate K mask data blocks in the Q data blocks to be written by the memory chip according to the second write command. The P data block includes a non-masked data block in the Q data blocks, where the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/ 2, K is greater than or equal to Q/2+1, and M is an integer greater than 0 and less than or equal to P-1, and M+K=Q.

In a fourth aspect, a memory chip is provided. It should be understood that the memory chip of the fourth aspect corresponds to the second aspect, and the memory chip can implement the method implemented by the memory chip in the second aspect, and operations of each module of the memory chip For the sake of avoiding repetition, the detailed description is omitted as appropriate.

Specifically, the memory chip includes: a storage medium for storing data; and a media controller connected to the memory controller in the computer system through the double rate DDR bus, and the media controller receives the memory controller to send through the DDR bus. a first write command, the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block, and the number of the data block to be written Is N, N is greater than or An integer equal to 2; the media controller receives, by the DDR bus, N data blocks sent by the memory controller according to the first write command, where one of the N data blocks is a first DM information block, The first DM information block is used to indicate a location of a masked data block in the N data blocks to be written, the N data blocks including a non-masked data block in the data block to be written, the medium The controller writes the non-masked data block in the data block to be written into the storage medium according to the indication of the first DM information block.

Optionally, in an implementation manner of the fourth aspect, the first DM information block is the first data block of the N data blocks.

Optionally, in an implementation manner of the fourth aspect, the first mask data block in the data block to be written is the nth data block, and n is greater than 0 and less than or equal to N; the N data The second to nth data blocks in the block are the first to n-1th data blocks in the data block to be written, and the n+1th to Nth data blocks in the N data blocks are The n+1th to Nthth data blocks in the data block to be written.

Optionally, in an implementation manner of the fourth aspect, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N; the N data blocks The second to the Z+1th data blocks are the Z non-masked data blocks, and when Z is less than or equal to N-2, the Z+2th to Nth data blocks in the N data blocks are pre- Set the data block.

Optionally, in an implementation manner of the fourth aspect, the media controller is further configured to receive a second write command sent by the memory controller, where the media controller is further configured to receive the P commands sent by the memory controller. a data block, where one of the P data blocks is a second DM information block, the second DM information block is used to indicate K of the Q data blocks to be written by the memory chip according to the second write command. a position of the masked data block, the P data block includes a non-masked data block of the Q data blocks, where the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, M is an integer greater than 0 and less than or equal to P-1, M+K=Q; the media controller is further configured to indicate according to the second DM information And writing the non-masked data block of the Q data blocks to be written into the storage medium.

In a fifth aspect, a computer system is provided. It should be understood that the computer system may include the memory controller of the third aspect and the memory chip of the fourth aspect, the memory controller and the memory chip. For the description of the foregoing method embodiment, The detailed description is omitted as appropriate in order to avoid repetition.

Specifically, the memory controller is connected to the memory chip through a double rate DDR bus, and the memory controller sends a first write command to the memory chip through the DDR bus, where the first write command includes first indication information, The first indication information is used to indicate that the data block to be written has a mask data block, and the number of the data block to be written is N, N is an integer greater than or equal to 2; a write command sends N data blocks to the memory chip through the DDR bus, wherein one of the N data blocks is a first DM information block, and the first DM information block is used to indicate the to-be-written The location of the masked data block in the data block, the N data blocks including the a non-masked data block in the data block to be written; the memory chip writes the non-masked data block in the data block to be written into the memory chip according to the indication of the first DM information block In the storage medium.

Optionally, in an implementation manner of the fifth aspect, the first DM information block is the first data block of the N data blocks.

Optionally, in an implementation manner of the fifth aspect, the first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N; The 2nd to nth data blocks in the data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th to the Nth data in the N data blocks The block is the n+1th to Nthth data block in the data block to be written.

Optionally, in an implementation manner of the fifth aspect, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N; the N data blocks The second to the Z+1th data blocks are the Z non-masked data blocks, and when Z is less than or equal to N-2, the Z+2th to Nth data blocks in the N data blocks are pre- Set the data block.

Optionally, in an implementation manner of the fifth aspect, the memory controller is further configured to send a second write command to the memory chip, where the memory controller is further configured to send the memory chip to the memory chip according to the second write command. P data blocks, one of the P data blocks is a second DM information block, the second DM information block is used to indicate that the memory chip is to be written in the Q data blocks according to the second write command. The position of the K mask data blocks, the P data blocks include non-masked data blocks in the Q data blocks, wherein the number of non-masked data blocks in the Q data blocks is M, Q =N, P=Q/2, K is greater than or equal to Q/2+1, M is an integer greater than 0 and less than or equal to P-1, M+K=Q; the memory chip is further used to generate information according to the second DM An indication of the block, the non-masked data block of the Q data blocks to be written is written into the storage medium.

DRAWINGS

FIG. 1 is a schematic structural diagram of a computer system to which an embodiment of the present application is applicable.

2 is a schematic block diagram of a method of transmitting a DM.

3 is a flow chart of a method of transmitting a DM in accordance with one embodiment of the present application.

4 is a schematic block diagram of a method of transmitting a DM according to an embodiment of the present application.

FIG. 5 is a flowchart of a method of transmitting a DM according to another embodiment of the present application.

FIG. 6 is a schematic block diagram of a method of transmitting a DM according to another embodiment of the present application.

FIG. 7 is a flowchart of a method of transmitting a DM according to another embodiment of the present application.

FIG. 8 is a schematic block diagram of a method of transmitting a DM according to another embodiment of the present application.

9 is a schematic block diagram of a memory controller in accordance with one embodiment of the present application.

FIG. 10 is a schematic block diagram of a memory chip in accordance with an embodiment of the present application.

11 is a schematic block diagram of a computer system in accordance with one embodiment of the present application.

Detailed ways

The technical solutions in the present application will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a computer system to which an embodiment of the present application is applicable. The computer system 100 includes a memory controller 110 and a DIMM 120. The DIMM 120 includes at least one memory chip. It should be understood that the memory chip in the embodiment of the present application may include a DRAM chip, a PCM chip, or a RRAM chip. The memory chip is described as an example of a DRAM chip, but the embodiment of the present application is not limited thereto. The memory controller 110 and the DIMM 120 are connected by a double data rate (DDR) bus. The memory controller 110 can control data exchange between the DRAM chip and a central processing unit (CPU) through the DDR bus.

The memory controller 110 is connected to a central processing unit (CPU) and is controlled by the CPU. It should be understood that, in the embodiment of the present application, the memory controller 110 may be separate from the central processing unit (CPU), or the memory controller 110 may be integrated into the CPU.

It should be understood that the technical solutions of the embodiments of the present application may be applied to a plurality of different memory organization forms. Only the form of the dual in-line memory module (DIMM) is shown in FIG. 1, but the embodiment of the present application is not limited to Therefore, the embodiment of the present application may also take other forms, for example, the chip controller and the processor may be on one board, or the chip controller may be used as a daughter card or a daughter board of other forms.

In order to facilitate understanding of the implementation of the present application, the DDR bus of the embodiment of the present application is introduced below.

A DDR bus typically includes an address bus, a command bus, and a data bus. The data bus in the DDR bus includes a bi-directional data strobe (DQS) signal line and a DQ signal line. In conventional DRAM-based DIMMs, the memory controller and DIMM are based on the DQS signal transmitted on the DQS signal line for data transmission on the DQ signal line.

Taking write data as an example, the memory controller sends a DQS signal and a data to be written to the DRAM chip through the DQS signal line and the DQ signal line, respectively, and the DRAM chip latches (or samples) the DQ signal line based on the received DQS signal. Transmitted data to be written. Similarly, during the data reading process, the memory device sends the DQS signal and the read data to the memory controller through the DQS signal line and the DQ signal line, respectively, and the memory controller latches the DQ signal line transmission based on the DQS signal. Data that has been read. Generally, data transmitted on the DQ signal line (also referred to as DQ signal) is transmitted, and the DQS signal transmitted on the DQS signal line is mainly used for clock synchronization between the memory controller and the DIMM, and the DQS signal is equivalent to a clock. Synchronization signal.

It should be noted that a DQS signal line refers to a line that can logically form a DQS signal. In practice, in one case, the DQS signal can be transmitted through a physical DQS line. In this case, one DQS signal line corresponds to one physical DQS line. In the other case, when the DQS signal is a differential signal, the DQS signal needs to be transmitted through two physical DQS lines. In this case, one DQS signal line corresponds to two physical DQS lines.

In order to enable different bit width DRAMs to work on the same DDR bus, the DDR data bus is generally grouped. For example, a DDR bus compatible with x4 DRAM (ie, the bit width of the DRAM chip is 4 bits) and x8 DRAM (that is, the bit width of the DRAM chip is 8 bits) is taken as an example. In the design of a standard DIMM, usually a set of DDR data buses includes Eight DQ signal lines and two DQS signal lines, which are designed to be of equal length on the board. In this way, the DDR bus can work normally whether it is connected to ×4 DRAM or connected to ×8 DRAM.

It should be understood that, in practice, the DDR bus may include multiple sets of data buses. For example, for DIMMs supporting Error Correction Code (ECC), the DDR data bus generally includes 72 DQ signal lines and 18 DQS signal lines. These data buses are divided into 9 groups of data buses, each of which includes 8 DQ signal lines and 2 DQS signal lines. For DIMMs that do not support ECC, the DDR data bus generally includes 64 DQ signal lines and 16 Strip DQS signal lines, these data buses are divided into 8 groups of data buses, each group of data bus includes 8 DQ signal lines and 2 DQS signal lines.

Since one DQS of each group of data buses in the ×8 DRAM is idle, the idle DQS can be set to the function of the DM pin, and since no DQS is idle in the ×4 DRAM, the x4 DRAM does not have the DM pin function. The DIMMs composed of ×4 DRAMs have high capacity and are usually used in servers with high performance requirements. If there is a way to solve the DM transmission of ×4 DRAM without increasing the pins, it will be beneficial to improve the performance of the server.

For the write data of the DRAM chip of ×4, as shown in Fig. 2, the transmission mode without increasing the pin is to increase the transmission period of the DM after transmitting the data, taking DDR5 as an example, the ×4 DRAM chip The burst length of one write data is generally BL16. Since DM information needs to be transmitted, the data transmission of DM is added after BL16. For example, the burst length required for DM data transmission is BL2, then the entire burst length is BL18.

It should be understood that, in the embodiment of the present application, a chip width of a ×4 DRAM is 4 bits, a chip width of the ×8 DRAM is 8 bits, and when a data amount of one burst transmission is 64 bits, a chip corresponding to a ×4 DRAM chip has a burst. The length BL is 16, which requires 8 transfer cycles, and the data is transferred twice per cycle. For example, data is transmitted once on each of the upper and lower edges of each cycle, and 4 bits are transmitted at a time. Similarly, when the amount of data transmitted in one burst is 64 bits, the burst length BL corresponding to the chip of ×8 DRAM is 8, requiring four transfer cycles, and data is transferred twice per cycle.

For example, data is transmitted once on each of the upper and lower edges of each cycle, and 8 bits are transmitted at a time.

For the transmission scheme shown in FIG. 2, since additional DM information needs to be transmitted, an additional DM information transmission time is added on the bus based on the transmission data, which wastes the bus bandwidth of the DDR.

In view of the above problems, the embodiment of the present application proposes a method for transmitting a DM, which can solve the above problem, and implements delivery of DM information without adding additional DM transmission time and additional pins.

Specifically, since the DM information needs to be transmitted, it means that at least one block of data is masked. Here, the masked data block can be referred to as a masked data block, because the memory chip is captured. After the code data block, the mask data block is masked, the memory chip does not rewrite the mask data block, and the memory chip only rewrites the unmasked data block. According to the above analysis, when the data is actually written, the masked data block is an unnecessary data block or a useless data block.

Therefore, the embodiment of the present application can implement DM transmission by using one of the transmitted N data blocks as a DM information block, and the N data blocks include non-masked data blocks to be written in the data block. On the basis of ensuring the transmission of useful data, the transmission of the DM can be realized without increasing the amount of data transmitted, avoiding additional transmission time and saving transmission resources.

Hereinafter, a method for transmitting a DM according to an embodiment of the present application will be described in detail with reference to the accompanying drawings.

FIG. 3 is a flowchart of a method for transmitting a DM according to an embodiment of the present application. The method 300 shown in FIG. 3 includes:

The memory controller sends a first write command to the memory chip, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block. The number of written data blocks is N, and N is an integer greater than or equal to 2.

In other words, the first indication information can indicate that the first write command is a command with a write of the DM.

Taking the DDR4 command as an example, one of the pins A17, A13, and A11 can be used to distinguish between normal write and DM write in the embodiment of the present application.

For example, if the selected pin is, for example, A17, the first indication information corresponds to the case where A17 is at a high level. Correspondingly, when A17 is low, the corresponding write command can be a normal write command, that is, a write command without DM.

The burst length (BL) and the address of the data to be written may be defined in the first write command. It should be understood that the data block to be written may be a data block corresponding to the BL. Taking DDR5 as an example, the memory chip can be a ×4 DRAM chip, and the burst data amount is 64 bits, then the BL can be 16. The corresponding mask granularity in the embodiment of the present application can be the data amount transmitted twice in one cycle. That is, 8 bits, that is, one data block can be 8 bits, that is, the data block to be written can be 8 blocks, that is, N=8.

Optionally, in practical applications, one data block may also correspond to a plurality of periodic data blocks. For example, one data block is 16 bits of data transmitted in two cycles; one data block may also correspond to data transmitted at one time. The amount, that is, 4 bits, is not limited to this embodiment.

It should also be understood that the amount of burst data normally transmitted in the embodiment of the present application may not be 64 bits, for example, the burst data amount of one transmission is 32 bits, or the burst data amount is other bit numbers, and accordingly, the BL is also Other values may be used, and embodiments of the present application are not limited thereto.

320. The memory controller sends N data blocks to the memory chip according to the first write command, where one of the N data blocks includes a first DM information block, where the first DM information block is used to indicate the to-be-written The location of the masked data block in the incoming data block, the N data blocks including the non-masked data block in the data block to be written.

It should be understood that the memory chip in the embodiment of the present application may include a DRAM chip, a PCM chip, or a RRAM chip. The following is an example in which the memory chip is a DRAM chip, but the embodiment of the present application is not limited thereto.

Specifically, the memory controller may send the N data blocks according to a burst length defined by the first write command. In the embodiment of the present application, after the memory controller sends the first write command, the N data blocks can be sent to the memory chip. It should be understood that, in the embodiment of the present application, each data block may include write data sent by one transfer period. Therefore, the memory controller may sequentially send the N data blocks through N cycles.

It should be understood that the first DM information block may be any one of the N data blocks that are sent. The example does not limit this.

Optionally, the first DM information block is the first one of the N data blocks that are transmitted.

In the scheme as described in FIG. 2, since the DRAM chip does not know in advance which block is a mask block, after all the data blocks are acquired, it is necessary to wait until the DM information is acquired before knowing whether each data block is hidden. The code block is still a non-masked block, and then the non-masked data block in the previously acquired data block can be written into the memory, resulting in a long processing cycle and affecting the writing efficiency. In the embodiment of the present application, the DM information is transmitted in the first data block, so that the memory chip can know whether the subsequently received data block is a mask block according to the DM information, so after receiving the data block, if The data block is a non-masked data block, and the memory chip can directly write the non-masked data block into the storage medium of the memory chip, and can improve the writing efficiency without waiting for other data blocks to be received.

In the following, the first DM information block is used as the first data block in the N data blocks as an example, but the embodiment of the present application is not limited thereto. For example, the first DM information block may be N. The intermediate block in the data block, or the first DM information block, may be the last one of the N data blocks.

It should be understood that the memory controller sends N data blocks to the memory chip as long as the first DM information block and all the non-masked data blocks in the data block to be written are included, and the embodiment of the present application does not send the N data. The remaining data blocks in the data blocks are qualified. Optionally, the remaining data blocks in the N data blocks may include a mask data block or a preset data block. The specific form of transmitting N data blocks in the embodiment of the present application will be described in detail below.

Case 1:

The first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th to the Nth of the N data blocks The data blocks are the n+1th to Nthth data blocks in the data block to be written.

For example, as shown in FIG. 4, taking DDR5 as the memory chip as the ×4 DRAM chip, the burst data amount is 64 bits, and the data block to be written (also referred to as the original data block) is 8 blocks, that is, N= 8. The data blocks to be written are data block 1 to data block 8, wherein each data block corresponds to 8-bit data. As shown in FIG. 4, the masked data block in the data block to be written includes data block 3, data block 4, data block 7, and data block 8. The non-masked data block includes a data block 1, a data block 2, a data block 4, and a data block 5. The DM information corresponding to the data block to be written is 00110011. When the value of the DM information bit is 0, it indicates that the corresponding data block is a non-masked data block, and when the DM information bit has a value of 1, it indicates that the corresponding data block is a masked data block.

It can be seen from FIG. 4 that the first mask data block in the data block to be written is the data block 3, and therefore, in the actual transmission, the data block 3 is not transmitted, and the remaining data blocks are transmitted.

Specifically, in actual transmission, the memory controller can sequentially transmit 8 data blocks through 8 cycles. The first data block of the transmitted 8 data blocks is the first DM information block, the second data block transmitted corresponds to the data block 1 to be written, and the third data block to be transmitted corresponds to the to-be-written data block. Data block 2, the 4th to 8th data blocks of the transmission correspond to the data block 4 to the data block 8 to be written, respectively.

According to the description of the foregoing case 1, it can be concluded that in case 1, the memory controller can send the DM information according to the following preset rule: firstly, the DM information is transmitted, and then the memory controller finds the number to be written according to the DM information. According to the first mask data block in the block, that is, the data block 3 to be written, the data before the first masked mask data block (ie, the data block 1 and the data block 2 to be written) And sequentially transmitted after the DM information in sequence, that is, the transmitted data block 2 and the data block 3 correspond to the data block 1 and the data block 2 to be written, and then the first mask data block is not transmitted, the first mask The data following the code data block, that is, the data blocks 4 to 8 to be written, are sequentially transmitted in accordance with the position of the original data.

The specific process of the memory controller transmitting the data block of the DM information according to the preset rule of the first case is described in detail below with reference to FIG.

The method shown in FIG. 5 can be performed by a memory controller, and the method 500 shown in FIG. 5 includes:

510. Send DM information.

That is, the DM information is transmitted through the first data block. For example, the DM information is 00110011.

520. Determine a first mask data block according to the DM information.

Specifically, the memory controller determines the first masked data block in the data block to be written, for example, the first masked data block is the data block 3 to be written.

530. Determine whether the current data block to be written is a data block before the first mask data block.

Specifically, after determining the first amount of the mask data block, the memory controller sequentially determines whether the current data block to be written is from the first data to be written to the Nth data block to be written. Is the data block before the data block 3. If yes, step 540 is performed; if no, step 550 is performed.

540, then the first data block is transmitted in sequence.

Specifically, since the data block 1 to be written is the data before the first mask data block, the data in the data block 1 to be written is transmitted in the second data block to be transmitted, due to the to-be-written The data block 2 is the data before the first mask data block, so the data in the data block 2 to be written is transferred in the third data block of the transmission.

550. Determine whether the current data block to be written is the first mask data block.

If the data block to be written is the first mask data block, step 560 is performed, otherwise step 570 is performed.

560. The current data block to be written is not transmitted.

Specifically, when the data block to be written is the first mask data block, it is not transmitted.

570. Determine that the current data block to be written completes the transmission.

Specifically, if the current data block with the transmission completes the transmission, step 590 is performed, and the transmission ends; otherwise, step 580 is performed.

580, according to the location of the data block to be written.

That is to say, if the data block to be written is the data block after the first mask data block, the data is transmitted according to the original position of the data block to be written.

590, the transmission ends.

Case 2:

The data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and when Z is less than or equal to N-2, the Z+2 to the Nth of the N data blocks The data blocks are preset data blocks.

That is, the N data blocks sent by the memory controller to the memory chip do not include the mask data blocks in the N data blocks to be written; the transmitted N data blocks include the first DM information block and the N data blocks. All non-masked data blocks in the data block to be written and preset data blocks.

For example, as shown in FIG. 6, taking DDR5 and the memory chip as an x4 DRAM chip as an example, the burst data amount is 64 bits, and the data block to be written (also referred to as a raw data block) is 8 blocks, that is, N= 8. The data blocks to be written are data block 1 to data block 8, wherein each data block corresponds to 8-bit data. As shown in FIG. 6, the masked data block in the data block to be written includes data block 3, data block 4, data block 7, and data block 8. The non-masked data block includes a data block 1, a data block 2, a data block 4, and a data block 5. The DM information corresponding to the data block to be written is 00110011. When the value of the DM information bit is 0, it indicates that the corresponding data block is a non-masked data block, and when the DM information bit has a value of 1, it indicates that the corresponding data block is a masked data block.

Specifically, in actual transmission, the memory controller can sequentially transmit 8 data blocks through 8 cycles. The first data block of the transmitted 8 data blocks is the first DM information block, and the 2nd to 5th data blocks transmitted correspond to the data block to be written and the data block to be written 2. The data block 5 to be written and the data block 6 to be written, the 6th to 8th data blocks transmitted correspond to the preset data block.

According to the description of the second case, it can be concluded that in the second case, the memory controller can send the DM information according to the following preset rules: firstly, the DM information is transmitted, and then the memory controller determines each data to be written according to the DM information. Whether the block masks the data block, if it is a masked data block, it does not transmit. If it is a non-masked data block, it is transmitted along with the previously transmitted data block. After the non-masked block transmission is completed, the remaining transport blocks may transmit the preset data block. For example, the preset data block includes 8 bits of 0, or 8 bits of 1. The embodiment of the present application is not limited thereto.

The specific process of the data controller transmitting the data block of the DM information according to the preset rule of the second case is described in detail below with reference to FIG.

The method shown in FIG. 7 can be performed by a memory controller, and the method 700 shown in FIG. 7 includes:

710. Send DM information.

720. Determine, according to the DM information, whether the current data block to be written is a mask data block.

The memory controller sequentially determines whether the current data block to be written is a mask data block from the first data to be written to the Nth data block to be written. . If yes, step 730 is performed; if no, step 740 is performed.

730. The current data block to be written is not transmitted.

Specifically, when the data block to be written is a mask data block, it is not transmitted.

740, followed by the transmission of the last transmitted data block.

Specifically, when the data block to be written currently is a non-masked data block, the data block transmitted before is transmitted.

750. Determine whether the data block to be written is transmitted.

If the data block to be written is transferred, step 760 is performed, and if the data block to be written is not transmitted, step 720 is performed.

760. Determine whether a transmission period of the BL corresponding to the first write command ends.

If the transmission period ends, step 780 is performed and the transmission ends. If the transmission period is the end, step 770 is performed.

770, transmitting a preset data block.

Specifically, after the DM information block and the non-masked data block are transmitted, if the transmission period is not completed, the preset data block is transmitted until the end of the transmission period.

780, the transfer ends.

330. The memory chip writes the non-masked data block in the data block to be written into the storage medium of the memory chip according to the indication of the first DM information block.

It should be understood that the preset rules in the first case and the second case are rules that are known in advance by the memory controller and the memory chip. After the memory controller sends the data block according to the preset rule, the memory chip acquires the N data blocks. The mask data block and the non-mask data block in the N data blocks to be written may be determined according to the DM information, and the unmasked data in the received N data blocks may be decoded according to the preset rule. The address of the block in the storage medium of the memory chip, and the non-masked data block in the data block to be written is written into the storage medium according to the decoded address.

It should be understood that the foregoing embodiment of FIG. 4 and FIG. 6 describes that the number of data blocks to be transmitted is eight, and the corresponding DM information is 8 bits, that is, the case where the data amount of one data block is exactly equal, but the embodiment of the present application is The data block to be transmitted may also be 4 or 16 or the like. Correspondingly, the number of bits of the transmission information may correspond to the number of data blocks.

It should be noted that, in the foregoing case 2, when the number of masked data blocks is large, the N data blocks sent by the memory controller include only a small number of non-masked data blocks and the first DM information block, including more useless. The default data block causes a waste of resources.

In particular, when the number K of masked data blocks is greater than or equal to Q/2+1, the useful data block transmission can be completed because Q/2 data blocks are required at most, Q=N. Therefore, in this case, in this embodiment, only Q/2 data blocks can be transmitted, and the remaining Q/2 data blocks are discarded.

Correspondingly, as another embodiment, the method of the embodiment of the present application may further include:

The memory controller sends a second write command to the memory chip;

The memory controller sends P data blocks to the memory chip according to the second write command, where one of the P data blocks is a second DM information block, and the second DM information block is used to indicate that the memory chip is The second write command positions the K mask data blocks in the Q data blocks to be written, the P data blocks include non-masked data blocks in the Q data blocks, where the Q data blocks The number of non-masked data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is an integer greater than 0 and less than or equal to P-1, M+K= Q.

It should be understood that in order to distinguish between different embodiments, Q is used here, in fact Q = N, where Q can be replaced with N.

It should be understood that the second write command may be a write command with a burst chop attribute or a flag, and the burst length corresponding to the second write command is half of the burst length corresponding to the first write command, for example The burst length corresponding to the second write command is 8, Q=8, and correspondingly, P=4.

For example, as shown in FIG. 8, taking DDR5 and the memory chip as a ×4 DRAM chip as an example, the amount of data to be written is 64 bits, and the data block to be written (which may also be referred to as a raw data block) is 8 blocks. That is, N=8. The data blocks to be written are data block 1 to data block 8, wherein each data block corresponds to 8-bit data. As shown in FIG. 8, the mask data block in the data block to be written includes data block 3, data block 4, data block 5, data block 7, and data block 8. The non-masked data block includes data block 1, data block 2, and data block 4. The DM information corresponding to the data block to be written is 00111011. When the value of the DM information bit is 0, it indicates that the corresponding data block is a non-masked data block, and when the DM information bit has a value of 1, it indicates that the corresponding data block is a masked data block.

Specifically, during actual transmission, the memory controller can sequentially transfer 4 data blocks through 4 cycles. The first data block of the transmitted 4 data blocks is a first DM information block, and the 2nd to 4th data blocks transmitted correspond to the data block to be written, the data block 2 to be written, and Data block 6 to be written.

It should be understood that the embodiment of FIG. 8 describes the case where P is exactly equal to M+1, that is, the number M of non-masked data blocks to be written is exactly equal to P-1. In this case, The first DM information block plus the M non-masked data blocks happens to fill the N data blocks. Optionally, when M is smaller than P-1, similar to case 2 described above, a preset data block may also be included in the P data blocks.

According to the above description, in the embodiment of FIG. 8, the memory controller may send the DM information according to the following preset rule: firstly, the DM information is transmitted, and then the memory controller determines whether each data block to be written is masked according to the DM information. The code data block is not transmitted if it is a masked data block, and if it is a non-masked data block, it is transmitted along with the previously transmitted data block. After the non-masked block transmission is completed, the remaining transport blocks may transmit the preset data block. For example, the preset data block includes 8 bits of 0, or 8 bits of 1. The embodiment of the present application is not limited thereto.

In the embodiment shown in FIG. 8, after the memory controller sends the data block according to the preset rule, after the memory chip acquires the P data blocks, the memory chip can determine the N data blocks to be written according to the DM information. The mask data block and the non-mask data block, and can decode the address of the non-masked data block in the received P data block in the storage medium of the memory chip according to the preset rule, and according to the decoded An address that writes the non-masked data block in the data block to be written into the storage medium.

It should be noted that, in the above, taking the memory chip as ×4 DRAM as an example, a method of implementing transmission of DM information without using additional pins and additional transmission time is described, but the embodiment of the present application is not limited to ×4 DRAM, for example, The method of the embodiment of the present application can also be applied to the X8 DRAM. As described above, the idle DQS in the ×8 DRAM can be used to implement the method for transmitting the DM information. When the method of the embodiment of the present application is applied to the ×8 DRAM, the method may not Using the redundant DQS pins to transmit DM information can reduce the amount of pins used, save pin resources, and improve computer performance.

It should be understood that, in the above embodiment, the memory chip is a DRAM chip as an example, but the embodiment of the present application is not limited thereto. In the embodiment of the present application, the memory chip may also be other types of chips, such as a nonvolatile A memory (none volatile memory (NVM) chip, etc., for example, the memory chip may include a phase change memory (phase Change memory, PCM) chip, resistive memory (RRAM) chip. It should also be understood that the width of the data bus of the memory chip is not limited in the embodiment.

It should be noted that the examples of the above embodiments are only intended to help those skilled in the art to understand the embodiments of the present application, and the embodiments of the present application are not limited to the specific numerical values or specific examples illustrated. A person skilled in the art will be able to make various modifications or changes in the embodiments according to the examples given above, and such modifications or variations are also within the scope of the embodiments of the present application. The method for transmitting DM information in the embodiment of the present application is described in detail with reference to FIG. 1 to FIG. 8 . The memory controller of the embodiment of the present application is described below with reference to FIG. 9 , and the memory chip of the embodiment of the present application is described in combination with FIG. 10 . Figure 11 depicts a computer system of an embodiment of the present application.

FIG. 9 is a schematic structural diagram of a memory controller according to an embodiment of the present application. The memory controller shown in FIG. 9 can receive a read/write request of the CPU, and reads and writes the memory according to the acquired read/write request. Specifically, the memory controller 900 shown in FIG. 9 includes:

The front-end interface 910 is connected to a processor in the computer system, and the front-end interface is configured to receive a write request of the processor, where the write request includes a data block to be written, and the number of the data block to be written is N. N is an integer greater than or equal to 2;

The memory bus interface 920 is connected to the memory chip through a double rate DDR bus, and the memory bus interface is used for:

And sending, by the write request, a first write command to the memory chip, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block. The number of data blocks to be written is N, and N is an integer greater than or equal to 2;

And the memory bus interface sends N data blocks to the memory chip according to the first write command write request, wherein one of the N data blocks is a first DM information block, and the first DM information block is used by the first DM information block. And indicating a location of the masked data block in the N data blocks to be written, the N data blocks including the non-masked data blocks in the N data blocks to be written.

Optionally, as another embodiment, the memory controller 900 may further include a control circuit that can generate a first write command according to a write request received by the front end port 910 and control the memory bus interface 920 to pass the double rate DDR. The bus sends a first write command to the memory chip and transmits the N data blocks.

Optionally, as another embodiment, the first DM information block is the first data block of the N data blocks.

Optionally, as another embodiment, the first mask data block in the data block to be written is the nth data block, where n is greater than 0 and less than or equal to N;

Optionally, as another embodiment, the data block to be written has Z non-masked data blocks, where the Z is an integer greater than 0 and less than N;

Optionally, in another embodiment, the memory bus interface is further configured to send a second write command to the memory chip. And sending, according to the second write command, P data blocks to the memory chip, where one of the P data blocks is a second DM information block, and the second DM information block is used to indicate that the memory chip is according to the second Writing a command to the position of the K mask data blocks in the Q data blocks to be written, the P data blocks including the non-masked data blocks in the Q data blocks, wherein the non-masked data blocks in the Q data blocks The number of masked data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is an integer greater than 0 and less than or equal to P-1, and M+K=Q.

It should be understood that the memory controller 900 can implement the various processes performed by the memory controller in the method embodiments of FIGS. 2-8. The operations and/or functions of the various modules in the memory controller 900 are respectively implemented in order to implement the corresponding processes in the method embodiments of FIG. 2 to FIG. For details, refer to the description in the foregoing method embodiments. To avoid repetition, the detailed description is omitted here.

FIG. 10 is a schematic structural diagram of a memory chip according to an embodiment of the present application. The memory chip shown in FIG. 10 can receive read and write commands sent by the memory controller, and perform read and write processing according to the read and write commands. Specifically, the memory chip 1000 shown in FIG. 10 includes:

a storage medium 1010, configured to store data;

The media controller 1020 is connected to the memory controller in the computer system through a double rate DDR bus.

Receiving, by the DDR bus, the first write command sent by the memory controller, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask a code data block, the number of data blocks to be written is N, and N is an integer greater than or equal to 2;

Receiving, by the DDR bus, the N data blocks sent by the memory controller according to the first write command, where the data block of the N data blocks is a first DM information block, the first DM information a block is used to indicate a location of a masked data block in the N data blocks to be written, the N data blocks including non-masked data blocks in the data block to be written,

The media controller writes the non-masked data block in the data block to be written into the storage medium according to the indication of the first DM information block.

It should be understood that, in the embodiment of the present application, the media controller 1020 may include a control circuit, a communication interface, and a buffer. The media controller may receive the first write command and the N data blocks through the communication interface, and the control circuit may The data block is stored in the buffer, and the non-masked data block is selected from the N data blocks and written into the storage medium according to the DM information.

Optionally, in another embodiment, the media controller is further configured to receive a second write command sent by the memory controller;

The media controller is further configured to receive P data blocks sent by the memory controller, where one of the P data blocks is a second DM information block, where the second DM information block is used to indicate that the memory chip is configured according to the The second write command positions the K mask data blocks in the Q data blocks to be written, the P data blocks include non-masked data blocks in the Q data blocks, where the Q data blocks are The number of non-masked data blocks is M, M is less than or equal to P-1, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is greater than 0 and less than or equal to P-1. Integer, M+K=Q;

The medium controller is further configured to write the non-masked data block of the Q data blocks to be written into the storage medium according to the indication of the second DM information.

It should be understood that the memory chip 1000 can implement the various processes performed by the memory chip in the method embodiments of FIGS. 2-8. The operations and/or functions of the various modules in the memory chip 1000 are respectively implemented in order to implement the corresponding processes in the method embodiments of FIG. 2 to FIG. For details, refer to the description in the foregoing method embodiments. To avoid repetition, the detailed description is omitted here.

11 is a schematic structural diagram of a computer system of an embodiment of the present application. The computer system 1100 of FIG. 11 includes the memory controller 900 depicted in FIG. 9, and the memory chip 1000 depicted in FIG.

Specifically, the memory controller is connected to the memory chip through a double rate DDR bus.

The memory controller sends a first write command to the memory chip through the DDR bus, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has mask data. a block, the number of data blocks to be written is N, and N is an integer greater than or equal to 2;

The memory controller sends N data blocks to the memory chip through the DDR bus according to the first write command, wherein one of the N data blocks is a first DM information block, and the first DM information block is used by the first DM information block. And indicating a location of the mask data block in the data block to be written, the N data blocks including the non-masked data blocks in the N data blocks to be written;

The memory chip writes the non-masked data block in the data block to be written into the storage medium of the memory chip according to the indication of the first DM information block.

Optionally, a buffer or other medium may also be included in the computer system 1100 of the embodiment of the present application. Specifically, the memory controller and the memory chip can be connected through the buffer or the media controller. The memory controller is connected to a buffer or a media controller; a buffer or a media controller memory connection.

Optionally, as another embodiment, the first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N;

Optionally, in another embodiment, the memory controller is further configured to send a second write command to the memory chip;

The memory controller is further configured to send P data blocks to the memory chip according to the second write command, where one of the P data blocks is a second DM information block, and the second DM information block is used to indicate The memory chip includes a position of the K mask data blocks in the Q data blocks to be written according to the second write command, where the P data blocks include non-masked data blocks in the Q data blocks, where The number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is an integer greater than 0 and less than or equal to P-1. M+K=Q;

The memory chip is further configured to write the non-masked data block of the Q data blocks to be written into the storage medium according to the indication of the second DM information block.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The unit described as a separate component may or may not be physically separated as a unit display The components may or may not be physical units, ie may be located in one place, or may be distributed over multiple network elements. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program code. .

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A method for transmitting a data mask DM, comprising:

The memory controller sends a first write command to the memory chip, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block, The number of data blocks to be written is N, and N is an integer greater than or equal to 2;

The memory controller sends N data blocks to the memory chip according to the first write command, where one of the N data blocks is a first DM information block, and the first DM information block And a location for indicating a masked data block in the data block to be written, where the N data blocks include non-masked data blocks in the data block to be written.
The method of claim 1, wherein the first DM information block is the first one of the N data blocks.
The method according to claim 2, wherein the first mask data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th of the N data blocks The Nth data block is the n+1th to Nthth data block in the data block to be written.
The method according to claim 2, wherein the data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and the Z+2th to Nth data blocks of the N data blocks are preset data block.
The method according to any one of claims 1 to 4, further comprising:

The memory controller sends a second write command to the memory chip;

The memory controller sends P data blocks to the memory chip according to the second write command, one of the P data blocks is a second DM information block, and the second DM information block is used for Instructing the memory chip to select a location of K mask data blocks in the Q data blocks to be written according to the second write command, the P data blocks including non-mask data in the Q data blocks a block, wherein the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is greater than 0 and less than or equal to An integer of P-1, M+K=Q.
A method for transmitting a data mask DM, comprising:

The memory chip receives a first write command sent by the memory controller, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask data block. The number of data blocks to be written is N, and N is an integer greater than or equal to 2;

The memory chip receives N data blocks sent by the memory controller according to the first write command, where one of the N data blocks is a first DM information block, and the first DM information The block is configured to indicate a location of the masked data block in the data block to be written, where the N data blocks include a non-masked data block in the data block to be written,

The memory chip writes the non-masked data block in the data block to be written into the storage medium of the memory chip according to the indication of the first DM information block.
The method of claim 6, wherein the first DM information block is the first one of the N data blocks.
The method according to claim 7, wherein the first number of masks in the data block to be written According to the block, the nth data block, n is an integer greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th of the N data blocks The Nth data block is the n+1th to Nthth data block in the data block to be written.
The method according to claim 7, wherein the data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and the Z+2th to Nth data blocks of the N data blocks are preset data block.
The method according to any one of claims 6 to 9, further comprising:

The memory chip receives a second write command sent by the memory controller;

The memory chip receives P data blocks sent by the memory controller according to the second write command, and one of the P data blocks is a second DM information block, and the second DM information block is used by the memory module. And indicating, in the location of the K mask data blocks in the Q data blocks to be written by the memory chip according to the second write command, the P data blocks include a non-mask in the Q data blocks a data block, wherein the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is greater than 0 and less than An integer equal to P-1, M+K=Q;

The memory chip writes the non-masked data block of the Q data blocks to be written into the storage medium according to the indication of the second DM information block.
A memory controller, comprising:

The front end interface is connected to a processor in the computer system, and the front end interface is configured to receive a write request of the processor, where the write request includes a data block to be written, and the number of the data block to be written N, N is an integer greater than or equal to 2;

A memory bus interface is coupled to the memory chip via a double rate DDR bus, the memory bus interface for:

Transmitting, according to the write request, a first write command to the memory chip, where the first write command includes first indication information, where the first indication information is used to indicate that the data block to be written has a mask Code data block

Transmitting, according to the first write command, N data blocks to the memory chip, where one of the N data blocks is a first DM information block, where the first DM information block is used to indicate the The location of the masked data block in the N data blocks to be written, the N data blocks including the non-masked data blocks in the data block to be written.
The memory controller according to claim 11, wherein the first DM information block is the first one of the N data blocks.
The memory controller according to claim 12, wherein the first masked data block in the data block to be written is the nth data block, and n is greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th of the N data blocks The Nth data block is the n+1th to Nthth data block in the data block to be written.
The memory controller according to claim 12, wherein the data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and the Z+2th to Nth data blocks of the N data blocks are preset data block.
A memory controller according to any one of claims 11 to 14, wherein

The memory bus interface is further configured to send a second write command to the memory chip, and send P data blocks to the memory chip according to the second write command, where one of the P data blocks is a second DM information block, where the second DM information block is used to indicate a location of the K mask data blocks in the Q data blocks to be written by the memory chip according to the second write command, the P The data block includes a non-masked data block in the Q data blocks, where the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, and K is greater than Or equal to Q/2+1, M is an integer greater than 0 and less than or equal to P-1, M+K=Q.
A memory chip, comprising:

a storage medium for storing data;

A media controller connected to a memory controller in a computer system via a double rate DDR bus.

The media controller receives a first write command sent by the memory controller by using the DDR bus, where the first write command includes first indication information, where the first indication information is used to indicate that the device is to be written. a data block has a mask data block, the number of data blocks to be written is N, and N is an integer greater than or equal to 2;

The media controller receives, by the DDR bus, N data blocks that are sent by the memory controller according to the first write command, where one of the N data blocks is a first DM information block, The first DM information block is used to indicate a location of a mask data block in the N data blocks to be written, where the N data blocks include non-mask data in the data block to be written. Piece,

The media controller writes the non-masked data block in the data block to be written into the storage medium according to the indication of the first DM information block.
The memory chip of claim 16, wherein the first DM information block is the first one of the N data blocks.
The memory chip according to claim 17, wherein the first mask data block in the data block to be written is the nth data block, and n is greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th of the N data blocks The Nth data block is the n+1th to Nthth data block in the data block to be written.
The memory chip according to claim 17, wherein the data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and the Z+2th to Nth data blocks of the N data blocks are preset data block.
A memory chip according to any one of claims 16 to 19, characterized in that

The media controller is further configured to receive a second write command sent by the memory controller;

The media controller is further configured to receive P data blocks sent by the memory controller, where one of the P data blocks is a second DM information block, and the second DM information block is used to indicate Determining, by the memory chip, a location of K mask data blocks in the Q data blocks to be written according to the second write command, the P data blocks including non-masked data blocks in the Q data blocks, The number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is greater than 0 and less than or equal to P- An integer of 1, M+K=Q;

The medium controller is further configured to write the non-masked data block of the Q data blocks to be written into the storage medium according to the indication of the second DM information.
A computer system, comprising:

Memory chip,

a memory controller connected to the memory chip through a double rate DDR bus

The memory controller sends a first write command to the memory chip by using the DDR bus, where the first write command includes first indication information, where the first indication information is used to indicate a data block to be written. Having a masked data block, the number of data blocks to be written is N, and N is an integer greater than or equal to 2;

The memory controller sends N data blocks to the memory chip through the DDR bus according to the first write command, where one of the N data blocks is a first DM information block, Decoding, by the first DM information block, a location of the masked data block in the data block to be written, where the N data blocks include non-masked data blocks in the N data blocks to be written;

The memory chip writes the non-masked data block in the data block to be written into the storage medium of the memory chip according to the indication of the first DM information block.
The computer system according to claim 21, wherein said first DM information block is a first one of said N data blocks.
The computer system according to claim 22, wherein the first masked data block in the data block to be written is the nth data block, and n is an integer greater than 0 and less than or equal to N;

The second to nth data blocks of the N data blocks are the 1st to n-1th data blocks in the data block to be written, and the n+1th of the N data blocks The Nth data block is the n+1th to Nthth data block in the data block to be written.
The computer system according to claim 22, wherein the data block to be written has Z non-masked data blocks, wherein the Z is an integer greater than 0 and less than N;

The second to the Z+1th data blocks of the N data blocks are the Z non-masked data blocks, and the Z+2th to Nth data blocks of the N data blocks are preset data block.
A computer system according to any one of claims 21 to 24, wherein

The memory controller is further configured to send a second write command to the memory chip;

The memory controller is further configured to send P data blocks to the memory chip according to the second write command, where one of the P data blocks is a second DM information block, and the second DM The information block is used to indicate a location of the K mask data blocks in the Q data blocks to be written by the memory chip according to the second write command, where the P data blocks include the Q data blocks a non-masked data block, wherein the number of non-masked data blocks in the Q data blocks is M, Q=N, P=Q/2, K is greater than or equal to Q/2+1, and M is greater than 0 and an integer less than or equal to P-1, M+K=Q;

The memory chip is further configured to write the non-masked data block of the Q data blocks to be written into the storage medium according to the indication of the second DM information block.