CN108139993A

CN108139993A - Memory device, Memory Controller Hub, data buffer storage device and computer system

Info

Publication number: CN108139993A
Application number: CN201680058607.2A
Authority: CN
Inventors: 肖世海; 杨伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-08-29
Filing date: 2016-08-29
Publication date: 2018-06-08
Anticipated expiration: 2036-08-29
Also published as: CN108139993B; WO2018039855A1

Abstract

A kind of memory device, Memory Controller Hub, data buffer storage device and computer system, the memory device (20) include：NVM(24)；NVM controller (22), it is connected by DDR buses with Memory Controller Hub, the NVM controller (22) carries out accessing operation, and carry out data transmission on the part DQS signal line in the DDR buses with the Memory Controller Hub according to the order of the Memory Controller Hub to the NVM (24).The memory device (20) using the part DQS signal line transmission data in DDR buses solves the problems, such as that extra data can not be transmitted between Memory Controller Hub and memory device.

Description

Memory device, Memory Controller Hub, data buffer storage device and computer system

Technical field

The present invention relates to computer field of storage more particularly to a kind of memory device, Memory Controller Hub, data buffer storage device and computer systems.

Background technique

With the development of technology, if the nonvolatile memories such as phase transition storage (Phase Change Memory, PCM) (None Volatile Memory, NVM) are with more and more extensive.After system cut-off, NVM remains to save data, and NVM has density high, the advantages that scalability is good, therefore, NVM are believed to substitution dynamic random access memory (Dynamic Random Access Memory, DRAM), as new memory.

But compared with DRAM, there is also some gaps for the performance of NVM, it is difficult to completely compatible existing Double Data Rate (Double Data Rate, DDR) standard.Specifically, Memory Controller Hub generally passes through DDR bus and accesses to the data in DRAM, and the read-write of data all has certain delay, the reading of DRAM is delayed and writes the fixed value that delay is generally 30ns or so, and the reading of the NVM such as PCM delay is about 100ns, writing delay is about 500ns, the two difference is larger, designs since the read-write sequence of DDR bus is the read-write delay based on DRAM, if NVM is used in DDR bus, need to solve timing compatibling problem.

In the prior art, in order to solve the timing compatibling problem of NVM Yu DDR bus, NVM is not connected directly usually with DDR bus, but it is connected by NVM controller with DDR bus, and pass through the temporary data read out from NVM of spatial cache inside NVM controller, or the data of NVM to be written, the structure of NVM controller may refer to Fig. 1.

As seen from Figure 1, the data of NVM either to be written, or be required to be scheduled and cache inside NVM controller from the data read in NVM, the delay that will lead to reading data and write-in in this way is not fixed.Since read-write delay is not fixed, the interactive relevant information of NVM is just needed between NVM controller and Memory Controller Hub, to guarantee the accuracy of the two data transmission procedure.For example, NVM controller when sending the data read to Memory Controller Hub, needs to notify the corresponding relationship of the read request of the Memory Controller Hub data read and Memory Controller Hub sending；For another example, when the spatial cache inside NVM is occupied full, NVM controller needs that the Memory Controller Hub inner buffer space is notified to expire, and can not continue to write to data.

Therefore, it is current urgent problem to be solved that additional data (the relevant information of such as NVM) how are transmitted between NVM controller and Memory Controller Hub.

Summary of the invention

The application provides a kind of memory device, Memory Controller Hub, data buffer storage device and computer system, to solve the problems, such as that extra data can not be transmitted between NVM controller and Memory Controller Hub.

In a first aspect, providing a kind of memory device, the memory device includes: nonvolatile memory NVM；NVM controller, it is connected by Double Data Rate DDR bus with Memory Controller Hub, the NVM controller carries out accessing operation to the NVM according to the order of the Memory Controller Hub, and carries out data transmission on the part DQS signal line in the DDR bus with the Memory Controller Hub.

With reference to first aspect, in certain implementations of first aspect, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the NVM controller carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, and first group of data/address bus is any group in the multi-group data bus.

With reference to first aspect, in certain implementations of first aspect, the NVM controller carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, it include: the transmission that the NVM controller carries out target data according to first DQS signal on the DQ signal wire in first group of data/address bus with the Memory Controller Hub, at least one of the data that the target data includes the data of the NVM to be written and reads out from the NVM；During DQ signal wire in first group of data/address bus transmits the target data, the NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal.

With reference to first aspect, in certain implementations of first aspect, the target data includes the first object data read out from the NVM, the NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal, during including: the DQ signal wire transmission first object data in first group of data/address bus, the NVM controller sends the first data on the second DQS signal line in first group of data/address bus according to first DQS signal, first data include first mesh Mark the mark of data and at least one of the memory address of the first object data.

With reference to first aspect, in certain implementations of first aspect, first data further include at least one of following information: having been written into the mark of the data in the NVM；Indicate whether the information for successfully writing data into the NVM；And the information of the state of the data buffer storage in the instruction NVM controller.

With reference to first aspect, in certain implementations of first aspect, the target data includes the second target data of the NVM to be written, the NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal, during including: DQ signal wire transmission second target data in first group of data/address bus, the NVM controller receives the second data on the second DQS signal line in first group of data/address bus according to first DQS signal, second data include the mark of second target data.

With reference to first aspect, in certain implementations of first aspect, the NVM includes at least one RANK.

It optionally, can also be in the check information of the second DQS signal line of first group of data/address bus upload delivery data, such as the error correcting code (Error Correction Code, ECC) of data.

Second aspect provides a kind of Memory Controller Hub, and the Memory Controller Hub includes: scheduler, for receiving the access request of processor；Rambus interface, it is connected by Double Data Rate DDR bus with memory device, the rambus interface is according to the access request, the order for accessing the nonvolatile memory NVM in the memory device is sent to the memory device, and is carried out data transmission on the part DQS signal line in the DDR bus with the memory device.

In conjunction with second aspect, in certain implementations of second aspect, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the rambus interface carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, and first group of data/address bus is any group in the multi-group data bus.

In conjunction with second aspect, in certain implementations of second aspect, the rambus interface carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, comprising: the rambus interface is according to first DQS signal in first group of number According to the transmission for carrying out target data on the DQ signal wire in bus with the memory device, at least one of the data that the target data includes the data of the NVM to be written and reads out from the NVM；During DQ signal wire in first group of data/address bus transmits the target data, the rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal.

In conjunction with second aspect, in certain implementations of second aspect, the target data includes the first object data read out from the NVM, the rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, during including: the DQ signal wire transmission first object data in first group of data/address bus, the rambus interface receives the first data on the second DQS signal line in first group of data/address bus according to first DQS signal, first data include the mark of the first object data and at least one of the memory address of the first object data.

In conjunction with second aspect, in certain implementations of second aspect, first data further include at least one of following information: having been written into the mark of the data in the NVM；Indicate whether the information for successfully writing data into the NVM；And the information of the state of the data buffer storage in the instruction NVM controller.

In conjunction with second aspect, in certain implementations of second aspect, the target data includes the second target data of the NVM to be written, the rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, during including: DQ signal wire transmission second target data in first group of data/address bus, the rambus interface sends the second data on the second DQS signal line in first group of data/address bus according to first DQS signal, second data include the mark of second target data.

Optionally, during Memory Controller Hub accesses memory device, rambus interface can determine the type of storage unit to be visited, and in the case where determining storage unit to be visited is DRAM, rambus interface selects the corresponding functional interface of DRAM to access DRAM.In the case where determining storage unit to be visited is NVM, rambus interface selects the corresponding functional interface of NVM to access NVM.Wherein, functional interface can be interface in logic.In practice, two functional interfaces can share same group of physical interface.

In conjunction with second aspect, in certain implementations of second aspect, the NVM includes at least one RANK.The third aspect, provides a kind of data buffer storage device, and the data buffer storage device is located at memory Between controller and memory device, and it is connected respectively with the Memory Controller Hub and the memory device by Double Data Rate DDR bus, the memory device includes nonvolatile memory NVM, the data buffer storage device includes: rambus interface, during the Memory Controller Hub sends the data of the NVM to be written to the memory device or receives from the memory device from the data that the NVM is read, the data transmitted on the part DQS signal line in DDR bus described in the rambus interface；Buffer, the data arrived for caching the rambus interface.

In conjunction with the third aspect, in certain implementations of the third aspect, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the rambus interface is according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, the data transmitted on DQ signal wire and the second DQS signal line in first group of data/address bus are received, first group of data/address bus is any group in the multi-group data bus.

Fourth aspect provides a kind of computer system, the Memory Controller Hub as described in any implementation including memory device and second aspect or second aspect as described in any implementation in first aspect or first aspect.

In conjunction with fourth aspect, in certain implementations of fourth aspect, the computer system further includes the data buffer storage device as described in any implementation of the third aspect or the third aspect.

In the prior art, the DQS signal on DQS signal line is used to latch the data on DQ signal wire, and the application transmits data using the part DQS signal line in DDR bus, solves the problems, such as that extra data can not be transmitted between Memory Controller Hub and memory device.

Detailed description of the invention

To describe the technical solutions in the embodiments of the present invention more clearly, attached drawing needed in the embodiment of the present invention will be briefly described below, apparently, drawings described below is only some embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, it is also possible to obtain other drawings based on these drawings.

Fig. 1 is the connection relationship diagram of Memory Controller Hub Yu the memory device based on NVM.

Fig. 2 is the schematic diagram of memory device provided in an embodiment of the present invention.

Fig. 3 is × 4DRAM and × 8DRAM share the schematic diagram of DDR bus.

Fig. 4 is × the read-write sequence figure of 4DRAM.

Fig. 5 is × the read-write sequence figure of 8DRAM.

Fig. 6 is the schematic diagram that provided in an embodiment of the present invention × 4DRAM and × 8NVM share DDR bus.

Fig. 7 is the read-write sequence figure of provided by one embodiment of the present invention × 8NVM.

Fig. 8 be another embodiment of the present invention provides × the read-write sequence figure of 8NVM.

Fig. 9 is the schematic diagram of the Memory Controller Hub of the embodiment of the present invention.

Figure 10 is the schematic diagram of the data buffer storage device of the embodiment of the present invention.

Figure 11 is the architecture diagram of the memory provided by one embodiment of the present invention comprising DRAM and NVM.

Figure 12 be another embodiment of the present invention provides the memory comprising DRAM and NVM architecture diagram.

Figure 13 is the architecture diagram for the memory comprising DRAM and NVM that further embodiment of this invention provides.

Figure 14 is the schematic diagram of the computer system of the embodiment of the present invention.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.

Generally it is connected by DDR bus between Memory Controller Hub and memory device, in order to make it easy to understand, first simply being introduced DDR bus.DDR bus includes address bus (address bus), command line (Command bus) and data/address bus (data bus).Data/address bus in DDR bus includes that bi-directional data latches (Bi-directional Data Strobe, DQS) signal wire and DQ signal wire.In traditional memory device based on DRAM, Memory Controller Hub and memory device are carried out data transmission on DQ signal wire based on the DQS signal transmitted on DQS signal line.To write data instance, Memory Controller Hub passes through DQS signal line and DQ signal wire respectively and sends DQS signal and data to be written to memory device, and memory device can latch the data to be written transmitted on (or sampling) DQ signal wire based on the DQS signal received.Similarly, in data read process, memory device passes through the data that DQS signal line and DQ signal wire send DQS signal to Memory Controller Hub and read out respectively, and Memory Controller Hub can latch the data read transmitted on DQ signal wire based on DQS signal.In a word, in the prior art, what is transmitted on DQ signal wire is data (alternatively referred to as DQ signal), and the DQS signal transmitted on DQS signal line is mainly used for realizing that the clock between Memory Controller Hub and memory device is synchronous, and DQS signal is equivalent to a kind of clock sync signal.

It should be noted that a DQS signal line refers to the line for being capable of forming DQS signal in logic, in practice, in a kind of situation, DQS signal can be transmitted by the DQS line of a physics.? In this case, the DQS line of the corresponding physics of a DQS signal line.In another case, DQS signal needs to be transmitted by the DQS line of two physics when DQS signal is differential signal.In this case, the DQS line of corresponding two physics of a DQS signal line.

Below with reference to Fig. 2, the memory device of the present invention is described in detail embodiment.Fig. 2 is memory device provided in an embodiment of the present invention.Memory device 20 includes:

NVM 24, the NVM 24 may include at least one NVM chip, for example, NVM 24 can be a NVM RANK, alternatively, NVM 24 can be NVM DIMM.

NVM controller 22 is connected by DDR bus with Memory Controller Hub, and NVM controller 22 carries out accessing operation to NVM 24 according to the order of Memory Controller Hub, and carries out data transmission on the part DQS signal line in DDR bus with Memory Controller Hub.

It should be noted that be used for transmission the part DQS signal line of data selection mode can there are many, be described in detail below with reference to specific embodiment.

It is possible, firstly, to which the packet design mode based on existing DDR bus, chooses the DQS signal line for transmitting data-signal from one group of data/address bus of DDR bus, in order to make it easy to understand, first introducing the packet design mode of existing DDR bus.

Data/address bus in DDR bus includes that a plurality of DQS signal line and a plurality of DQ signal wire in order to allow the DRAM of different bit wides to work in same DDR bus, can generally be grouped design in practice to DDR data/address bus.By taking the DDR bus of compatibility × 4DRAM (i.e. the bit wide of dram chip is 4) and × 8DRAM (i.e. the bit wide of dram chip is 8) as an example, in dual inline memory module (the Dual Inline Memory Modules of standard, DIMM in design), usual one group of DDR data/address bus includes 8 DQ signal wires and 2 DQS signal lines, these signal wires do isometric design on circuit boards, so, either connect × 4DRAM still meets × 8DRAM, DDR bus can work normally.Below with reference to Fig. 3-Fig. 5, the working method of the DDR bus of compatibility × 4DRAM and × 8DRAM is described in detail.

Fig. 3 is × 4DRAM and × 8DRAM share the schematic diagram of DDR bus.Fig. 3 shows 2 DIMM altogether, wherein the dram chip inside DIMM 0 is × 4DRAM, and the dram chip inside DIMM 1 is × 8DRAM.Further, Fig. 3 shows one group of data/address bus in DDR bus, this group of data/address bus includes 8 DQ signal wires (DQ [0:7] in Fig. 3) and 2 DQS signal lines (DQS [0] and DQS [1] in Fig. 3) altogether.It should be understood that for convenience, Fig. 3 illustrates only one group of data/address bus in DDR bus, and in practice, DDR bus may include multi-group data bus, for example, the DIMM for supporting error correcting code (Error Correction Code, ECC) For, DDR data/address bus generally comprises 72 DQ signal wires and 18 DQS signal lines, these data/address bus are divided into 9 groups of data/address bus, and every group of data/address bus includes 8 DQ signal wires and 2 DQS signal lines；For not supporting the DIMM of ECC, DDR data/address bus generally comprises 64 DQ signal wires and 16 DQS signal lines, these data/address bus are divided into 8 groups of data/address bus, and every group of data/address bus includes 8 DQ signal wires and 2 DQS signal lines.

For DIMM 0, since its internal storage chip is × 4DRAM, one DQS signal line needs to latch 4 DQ signal wires, therefore, DQS [0] and DQS [1] is used to transmission DQS signal, wherein the DQS signal transmitted on DQS [0] is for latching the data transmitted on DQ [0:3], the DQS signal transmitted on DQS [1] is for latching the data transmitted on DQ [4:7], and the specific read-write sequence of × 4DRAM is referring to fig. 4.

For DIMM 1, since its internal storage chip is × 8DRAM, one DQS signal line needs to latch 8 DQ signal wires, therefore, any one DQS signal line in DQS [0] and DQS [1] can complete the latch of DQ [0:7], and another DQS signal line does not have actual semiotic function.The specific read-write sequence of × 8DRAM is in Fig. 5 that DQS [0] completes the latch of all DQ lines in one group of DQS data/address bus, and DQS [1] is responsible for terminating with the TDQS pin of DIMM 1, without transmitting DQS signal referring to the difference of Fig. 5, Fig. 5 and Fig. 4.

As seen from Figure 5, packet design bring is the result is that in some cases, certain DQS signal lines in one group of data/address bus only provide termination function, such as the DQS [1] being connected with the TDQS pin of DIMM 1 in Fig. 5 without transmitting DQS signal.

It should be noted that, the above is only the packet design mode of DDR data/address bus is described so that × 4DRAM and × 8DRAM share DDR bus as an example, the embodiment of the present invention is without being limited thereto, and the packet design mode that the DRAM of other different bit wides shares DDR bus is similar, and and will not be described here in detail.In a word, when the DRAM of different bit wides shares DDR bus, every group of data/address bus in DDR bus includes a plurality of DQS signal line, when the wide DRAM of the high bit in the DRAM of different bit wides is connected with DDR bus, it just will appear in a plurality of DQS signal line and do not transmit DQS signal, the DQS signal line of termination is only provided.

On the basis of the packet design of DDR bus, the DQS signal line for being used for transmission data can be chosen as follows.

Optionally, as one embodiment, DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, NVM controller is according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus first Carry out data transmission on DQ signal wire and the second DQS signal line in group data/address bus with Memory Controller Hub, wherein first group of data/address bus is any group in multi-group data bus.Further, in some embodiments, every group of data/address bus in multi-group data bus can choose the DQS signal line for being used for transmission data according to mode identical with first group of data/address bus.

In the prior art, the DQS signal on DQS signal line is used to latch the data on DQ signal wire, and the embodiment of the present invention transmits data using the part DQS signal line in DDR bus, solves the problems, such as that extra data can not be transmitted between Memory Controller Hub and memory device.For example, the relevant information of NVM can be transmitted, between Memory Controller Hub and memory device to guarantee the accuracy of the information interaction of NVM controller and Memory Controller Hub.

Further, DQ signal wire transmitting data of the NVM controller based on the first DQS signal in first group of data/address bus.Assuming that DDR bus is the DRAM of the DRAM in order to be compatible with the first bit wide and the second bit wide and designs, wherein, second is wider than the first bit wide, the embodiment of the present invention is equivalent to the working method that the dram chip of the second bit wide is simulated using NVM controller, the data transmitted on the DQ signal wire in first group of data/address bus are latched by a DQS signal line, it thus will appear the DQS signal line without transmitting DQS signal, such DQS signal line transmission extra data can be chosen, possibility is provided to interact the relevant information of NVM for NVM controller and Memory Controller Hub between.

With the first bit wide for 4, for second bit wide is 8, NVM can simulate × 8DRAM (this NVM is known as × 8NVM below) by NVM controller, so, during NVM controller and Memory Controller Hub interaction data, every group of data/address bus in DDR bus will appear a DQS signal line without transmitting DQS signal, Fig. 6 is × and 4DRAM and × 8NVM shares the schematic diagram of DDR bus, and this existing DQS signal line without transmitting DQS signal is the DQS1 being connected with TDQS pin in Fig. 6.

Assuming that the grouping of DDR bus is designed for compatibility × 4DRAM and × 8DRAM, in the case where supporting ECC, DDR data/address bus may include 72 DQ signal wires and 18 DQS signal lines, these data/address bus are divided into 9 groups, every group includes 8 DQ signal wires and 2 DQS signal lines, first group of data/address bus can be any group in 9 groups, first DQS signal line can be any one (another is the second DQS signal line) in 2 DQS signal lines in first group of data/address bus, the first DQS signal is transmitted on first DQS signal line, NVM controller can latch the data transmitted on other 8 DQ signal wires in first group of data/address bus according to the first DQS signal, and latch the data transmitted on the second DQS signal line.In further embodiments, ECC is not being supported In the case where, DDR data/address bus may include 64 DQ signal wires and 16 DQS signal lines, these data/address bus are divided into 8 groups, every group includes 8 DQ signal wires and 2 DQS signal lines, first group of data/address bus can be any group in 8 groups, first DQS signal line can be any one (another is the second data/address bus) in 2 DQS signal lines in first group of data/address bus, the first DQS signal is transmitted on first DQS signal line, NVM controller can be according to the first DQS signal, latch the data transmitted on other 8 DQ signal wires in first group of data/address bus, and latch the data transmitted on the second DQS signal line.

Optionally, as one embodiment, NVM controller carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with Memory Controller Hub according to the first DQS signal, it include: the transmission that NVM controller carries out target data according to the first DQS signal on the DQ signal wire in first group of data/address bus with Memory Controller Hub, target data includes at least one of the data of NVM to be written and the data read out from NVM；During DQ signal wire transmission objectives data in first group of data/address bus, NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with Memory Controller Hub according to the first DQS signal.

In the prior art, the RANK in memory shares DDR bus, and each RANK is time-multiplexed to DDR bus, will not influence each other, and when a RANK transmits data, the data/address bus of other RANK is in terminated state, does not transmit signal.

The characteristic for the DDR data/address bus that is time-multiplexed between RANK is utilized, it is specified that the second DQS signal line in first group of data/address bus transmits data during the DQ signal wire transmission objectives data of first group of data/address bus in the embodiment of the present invention.Time division multiplexing characteristic based on DDR data/address bus, during the DQ signal wire transmission objectives data of first group of data/address bus, second DQS signal line is occupied by NVM, and the data transmission on the second DQS signal line, which will not transmit the data of other memories or other RANK, to be impacted.

Below with reference to Fig. 7, by can connect simultaneously × the DDR bus of 4DRAM and × 8DRAM for be described in detail.Fig. 7 shows the process that NVM controller simulation × 8DRAM carries out reading and writing data.Specifically, in write field scape, NVM controller writes delay after receiving activation command (ACT) and write order (WR), according to the instruction of tWL parameter, writes data into the spatial cache of NVM controller.Before data are written, it needs first to obtain DQS signal from DQS [0], and after the time interval of tWPRE parameter instruction, starts to latch the data transmitted on DQ [0:7], and after the time interval of tRPST parameter instruction, stop latching the data transmitted on DQ [0:7]；In reading scene, after Memory Controller Hub sends activation command and read command, the limit of the performance by NVM medium System, data can not be read according to the timing of DRAM, after NVM controller knows the spatial cache for having data to read from NVM NVM controller, NVM controller can notify Memory Controller Hub to read data by certain pins, then, Memory Controller Hub can send TB order to NVM controller, and (delay between read command and TB order is non-constant time lag, this is determined by NVM medium self character), NVM is received after the order, according to the reading delay of tRL parameter instruction, it places data on DQ [0:7], before placing data into DQ [0:7], it needs to first pass through DQS [0] and sends DQS signal to Memory Controller Hub, so, Memory Controller Hub receives after DQS signal, it will be after the time interval that tRPRE parameter indicates , start to latch the data transmitted on DQ [0:7], and after the time interval of tRPST parameter instruction, stop latching the data transmitted on DQ [0:7].As can be seen from Figure 7, during latching the data transmitted on DQ [0:7] based on DQS [0], also data are transmitted on DQS [1] simultaneously, such as transmit the relevant information of NVM, since every group of data/address bus includes 8 DQ signal wires and 2 DQS signal lines, the data of 64Byte are often transmitted by DQ signal wire, so that it may transmit additional 9Byte data using DQS [1], provide sufficient support for the transmitting of NVM relevant information.

It should be noted that, in the embodiment of the present invention, when the second DQS signal line of first group of data/address bus uploads delivery data, data-signal on second DQS signal line of first group of data/address bus can be identical as the DQS signal phase on the first DQS signal line of first group of data/address bus, can also be identical as the signal phase on the DQ signal wire of first group of data/address bus.By taking × 8NVM as an example, Fig. 7 is the example of the signal same-phase on the DQ signal wire of the data-signal and every group of data/address bus on the second DQS signal line of first group of data/address bus；Fig. 8 is the example of the DQS signal same-phase on the first DQS signal line of the data-signal and first group of data/address bus on the second DQS signal line of first group of data/address bus.

The embodiment of the present invention is not specifically limited the data type transmitted on the second DQS signal line in first group of data/address bus, in practice, it can be selected according to the type for the target data transmitted on the DQ signal wire in first group of data/address bus, be described in detail below with reference to specific embodiment.

Optionally, in some embodiments, target data includes the first object data read out from NVM, NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with Memory Controller Hub according to the first DQS signal, during including: the DQ signal wire transmission first object data in first group of data/address bus, NVM controller sends the first data according to the first DQS signal on the second DQS signal line in first group of data/address bus, and the first data include at least one of mark and memory address of first object data of first object data.It is the corresponding data of which read request that the mark of first object data, which may be used to indicate the first object data,；In addition, the mark of first object data can be corresponding with the read address of the read request of first object data.

Further, the first data further include at least one of following information: having been written into the mark of the data in NVM；Indicate whether the information for successfully writing data into NVM；And the information of the state of the data buffer storage in instruction NVM controller.

Optionally, in some embodiments, target data includes the second target data of NVM to be written, NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with Memory Controller Hub according to the first DQS signal, during including: DQ signal wire the second target data of transmission in first group of data/address bus, NVM controller receives the second data according to the first DQS signal on the second DQS signal line in first group of data/address bus, and the second data include the mark of the second target data.It is the corresponding data of which write request that the mark of second target data, which may be used to indicate second target data,；In addition, the mark of the second target data can be corresponding with the write address of the write request of the second target data.

It further, can also be in the check information of the second DQS signal line upload delivery data of first group of data/address bus, such as ECC.

In the application, the DQS signal line for being used for transmission data can be known as to NM bus (i.e. NVM Message Bus), data in NM bus are properly termed as NM packet, and for write field scape, NM packet may include the mark WID (Write ID) of data to be written.For reading scene, RID (Read ID, i.e., the mark of data to be read) can be set for data to be read, and the RID of the data read is returned by NM packet.Alternatively, RID can not be arranged for data to be read, the address of the data read is directly returned to by NM packet.

Further, whether be written in NVM if necessary to confirmation data and (carry out writing complete confirmation), then status informations such as whether the WID and the WID that can carry the data for having been written into NVM in NM packet are effective, malfunction.

Further, either reading scene or write field scape, NM packet may include ECC, for protect transmission data correctness.

It is illustrated by taking DDR 4 as an example below, in DDR 4, the DIMM with ECC function of DDR 4 has the pin of 18 DQS signal lines of connection (every DQS signal line includes two differential signal lines), 9 DQS signal lines therein can be used as NM bus, and the corresponding relationship between them is as shown in Table 1:

Table one: the corresponding relationship of DQS signal line and NM bus

The DIMM pin of DDR 4	NM bus
DQS1#/DQS1	NM[0]
DQS3#/DQS3	NM[1]

DQS5#/DQS5	NM[2]
DQS7#/DQS7	NM[3]
DQS9#/DQS9	NM[4]
DQS11#/DQS11	NM[5]
DQS13#/DQS13	NM[6]
DQS15#/DQS15	NM[7]
DQS17#/DQS17	NM[8]

For write field scape, NM [0:8] can carry the relevant information of NVM according to mode shown in table two.

Table two: for the definition mode of the NM packet of write field scape

As shown in Table 2, a clock (clock) may include 2 beats (beat), and each beat can transmit different information.For write field scape, NM bus can be used to transmit the mark (WID) of data to be written, can also transmit the ECC field for verifying NM packet (the NM packet of this transmission).RFU (Reserved For Future Use) in table two is reserved field.

For scene is read, NM [0:8] can carry the relevant information of NVM according to mode shown in table three.

Table three: for the definition mode for the NM packet for reading scene

In table three, RID is the mark of the data read, and R-ADDR is the address of the data read, and the two can be transmitted simultaneously, can also only transmit one of them.Such as, when Memory Controller Hub reads data, if be embedded in read request data to be read RID (or, Memory Controller Hub indicates the RID of data to be read by other modes such as such as synchronous countings with NVM controller), NVM controller is after getting data in NVM, the RID of the data can be carried in NM packet, know which read request is the data correspond to so that Memory Controller Hub is based on the RID.For another example, when Memory Controller Hub reads data, if NVM can not get the corresponding RID of read request, NVM controller is after getting data in NVM, the memory address of the data can be carried in NM packet, know which read request is the data correspond to so that Memory Controller Hub is based on the memory address.Furthermore, in some embodiments, the mark WID for having been written into the data of NVM can be returned by NM packet, it is equivalent to and the data of write-in NVM is confirmed, Valid in table three can indicate whether the WID returned is effective WID, STAU can occupy 1 or multidigit, and whether designation date is successfully written NVM or mistake occurs for designation date writing process.Further, in some embodiments, WC/PWC (write credit increase/persistent write credit increase) field can be increased in table 3, with the residual capacity (or idle capacity) etc. for indicating the write buffer space in NVM controller, Memory Controller Hub can be determined based on the residual capacity Whether new data are written.

Above in association with Fig. 2 to Fig. 8, the memory device of the embodiment of the present invention is described in detail, below in conjunction with Fig. 9, the Memory Controller Hub of the present invention is described in detail embodiment, it should be appreciated that the signal processing mode between Memory Controller Hub and memory device is similar, for sake of simplicity, and will not be described here in detail.

Fig. 9 is the schematic diagram of the Memory Controller Hub of the embodiment of the present invention.The Memory Controller Hub 90 of Fig. 9 includes:

Scheduler 92, for receiving the access request of processor；

Rambus interface 94, it is connected by Double Data Rate DDR bus with memory device, the rambus interface 94 is according to the access request, the order for accessing the nonvolatile memory NVM in the memory device is sent to the memory device, and is carried out data transmission on the part DQS signal line in the DDR bus with the memory device.

In the prior art, DQS signal line is used to latch the data on DQ signal wire, and the embodiment of the present invention transmits data using the part DQS signal line in DDR bus, solves the problems, such as that extra data can not be transmitted between Memory Controller Hub and memory device.For example, the relevant information of NVM can be transmitted, between Memory Controller Hub and memory device to guarantee the accuracy of the information interaction of NVM controller and Memory Controller Hub.

Optionally, in some embodiments, rambus interface 94 can determine the type of storage unit to be visited, in the case where the storage unit is DRAM, rambus interface 94 selects the corresponding functional interface of DRAM to access DRAM, in the case where the storage unit is NVM, rambus interface 94 selects the corresponding functional interface of NVM to access NVM.Said memory cells for example can be RANK.

Rambus interface 94 determine the type of storage unit to be visited mode can there are many, such as, in DIMM standard, DIMM has serial presence check Electrically Erasable Programmable Read-Only Memory (Serial Presence Detect Electrically Erasable Programmable Read-Only Memory, SPD EEPROM), the EEPROM can pass through the serial interface access except DDR address/data/command line, the type information (type information of such as RANK) of storage unit can be stored in the EEPROM, rambus interface 94 can know the type of storage unit by accessing the EEPROM.

Rambus interface 94 may include two functional interfaces: FUNC1 and FUNC2.It should be understood that functional interface can be interface in logic, in practice, two functional interfaces can share same group of physical interface, and by taking × 8DRAM as an example, two functional interfaces can share 8 DQ signal wires and 2 DQS signal line.FUNC1 can support the data transfer mode of DRAM, for example, every group of data/address bus includes 2 DQS signal lines for × 4DRAM, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 4 DQ lines；For × 8DRAM, every group of data/address bus includes 2 DQS signal lines, and the DQS signal transmitted on 1 DQS signal line can latch the data transmitted on 8 DQ signal wires, and another 1 DQS signal line does not transmit signal, only provides termination function.FUCN2 can be the functional interface for supporting DQS signal line transmitting data, for × 8NVM, every group of data packet includes 2 DQS signal lines, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 8 DQ signal wires, another 1 DQS signal line is also used for transmitting data, for example, the relevant information of transmitting NVM.

Optionally, in some embodiments, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, and the rambus interface 94 carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus.

Optionally, in some embodiments, the rambus interface 94 carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, it include: the transmission that the rambus interface 94 carries out target data according to first DQS signal on the DQ signal wire in first group of data/address bus with the memory device, at least one of the data that the target data includes the data of the NVM to be written and reads out from the NVM；During DQ signal wire in first group of data/address bus transmits the target data, the rambus interface 94 carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal.

Optionally, in some embodiments, the target data includes the first object data read out from the NVM, the rambus interface 94 carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, during including: the DQ signal wire transmission first object data in first group of data/address bus, the rambus interface 94 receives the first data on the second DQS signal line in first group of data/address bus according to first DQS signal, first data include the mark of the first object data and at least one of the memory address of the first object data.

Optionally, in some embodiments, first data further include at least one of following information: having been written into the mark of the data in the NVM；Indicate whether successfully to write data into the NVM's Information；And the information of the state of the data buffer storage in the instruction NVM controller.

Optionally, in some embodiments, the target data includes the second target data of the NVM to be written, the rambus interface 94 carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, during including: DQ signal wire transmission second target data in first group of data/address bus, the rambus interface 94 sends the second data on the second DQS signal line in first group of data/address bus according to first DQS signal, second data include the mark of second target data.

Optionally, in some embodiments, the NVM includes at least one RANK.

Above in association with Fig. 2 to Fig. 9, the memory device and Memory Controller Hub of the embodiment of the present invention is described in detail, below in conjunction with Figure 10, the data buffer storage device of the present invention is described in detail embodiment, the data buffer storage device is between Memory Controller Hub and memory device, during Memory Controller Hub and memory device transmission data, data buffer storage device can first cache data interactive therebetween, by certain signal processing (such as amplifying processing to signal), it is further continued for being sent to opposite end, the accuracy of signal transmitting can be improved in this way.Therefore, if being provided with such data buffer storage device between memory device and Memory Controller Hub, the data buffer storage device is also required to using the signal processing mode similar with Memory Controller Hub and memory device, to support to upload delivery data in DQS signal line, specific signal processing mode may refer to above, and and will not be described here in detail.

Figure 10 is the schematic diagram of the data buffer storage device of the embodiment of the present invention.The data buffer storage device 100 of Figure 10 is connected with the Memory Controller Hub and the memory device respectively between Memory Controller Hub and memory device, and through DDR bus, and the memory device includes NVM,

The data buffer storage device 100 includes:

Rambus interface 102, during the Memory Controller Hub sends the data of the NVM to be written to the memory device or receives from the memory device from the data that the NVM is read, the rambus interface 102 receives the data transmitted on the part DQS signal line in the DDR bus；

Buffer 104, the data received for caching the rambus interface 102.

Optionally, as one embodiment, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the rambus interface 102 is according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, the data transmitted on DQ signal wire and the second DQS signal line in every group of data/address bus are received, first group of data/address bus is any group in the multi-group data bus.

Some memories both include NVM, it again include DRAM, and the organizational form of NVM and DRAM in memory can there are many, for different types of organizational form, the specific implementation of data buffer storage device (hereinafter referred DB (Data Buffer)) can also be different, is described in detail below with reference to Figure 11 to Figure 13.

Figure 11 shows a kind of organizational form of NVM controller and DRAM and NVM in memory, in Figure 11, the data line of NVM controller 110 is connected by DB 111 with memory bank 112 (in Figure 11 by taking 4 slot of DDR as an example), and Memory Controller Hub 113 is then attached to.NVM controller 110 is connected with NVM 114 with DRAM 115, and DRAM 115 is located at after NVM 114, and the data/address bus of DRAM 115 is connected with NVM controller 110.In this organizational form, since DB 111 needs the data of interaction between cache controller 113 and memory device, with regard to needing to latch data interactive therebetween, therefore, DB 111 is also required to support the data transmission of DQS signal line, and 111 signal processing mode of DB can refer to Fig. 7 or Fig. 8.

Figure 12 shows another organizational form of NVM controller and DRAM and NVM in memory, the data/address bus of DRAM 125 and NVM controller 120 meets DB 121 respectively, DB 121 is connected to Memory Controller Hub 123 by memory bank 122 (in Figure 12 by taking DDR4 slot as an example) again, and NVM 124 is located at after NVM controller 120.For this organizational form, the function of DB 121 had both needed support the data transmission of common DRAM 125, it is also desirable to DQS signal line be supported to transmit data.

Figure 13 shows a kind of example of the internal structure of the DB under organizational form shown in Figure 12, includes two functional interfaces: FUNC1 and FUNC2 inside DB 121 as can be seen from Figure 13.It should be understood that functional interface can be interface in logic, in practice, two functional interfaces can share same group of physical interface, and by taking × 8DRAM as an example, two functional interfaces can share 8 DQ signal wires and 2 DQS signal lines.FUNC1 can support the data transfer mode of DRAM, for example, every group of data/address bus includes 2 DQS signal lines for × 4DRAM, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 4 DQ lines；For × 8DRAM, every group of data/address bus includes 2 DQS signal lines, and the DQS signal transmitted on 1 DQS signal line can latch the data transmitted on 8 DQ signal wires, and another 1 DQS signal line does not transmit signal, only provides termination function.FUCN2 can be the functional interface for supporting DQS signal line transmitting data, for × 8NVM, every group of data packet includes 2 DQS signal lines, the DQS signal transmitted on 1 DQS signal line latches the data transmitted on 8 DQ signal wires, another 1 DQS signal line is also used for transmitting data, for example, the relevant information of transmitting NVM.In addition, DB 121 further includes a control interface, the control inputted by control interface System order, DB 121 can be switched between FUNC1 and FUNC2.

Figure 14 is the schematic diagram of the computer system of the embodiment of the present invention.The computer system 140 of Figure 14 includes the memory device 20 of Fig. 1 description and the Memory Controller Hub 90 of Fig. 9 description.

Optionally, in some embodiments, computer system 140 can also include the data buffer storage device 100 of Figure 10 description.

Those of ordinary skill in the art may be aware that unit described in conjunction with the examples disclosed in the embodiments of the present disclosure and algorithm steps, can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Professional technician can use different methods to achieve the described function each specific application, but such implementation should not be considered as beyond the scope of the present invention.

It is apparent to those skilled in the art that for convenience and simplicity of description, system, the specific work process of device and unit of foregoing description can refer to corresponding processes in the foregoing method embodiment, details are not described herein.

In several embodiments provided herein, it should be understood that disclosed systems, devices and methods may be implemented in other ways.Such as, the apparatus embodiments described above are merely exemplary, such as, the division of the unit, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of device or unit, can be electrical property, mechanical or other forms.

The unit as illustrated by the separation member may or may not be physically separated, and component shown as a unit may or may not be physical unit, it can and it is in one place, or may be distributed over multiple network units.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.

In addition, the functional units in various embodiments of the present invention may be integrated into one processing unit, it is also possible to each unit and physically exists alone, can also be integrated in one unit with two or more units.

If the function is realized in the form of SFU software functional unit and when sold or used as an independent product, can store in a computer readable storage medium.Based on this understanding, substantially the part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products technical solution of the present invention in other words, which is stored in a storage medium In, including some instructions use is so that a computer equipment (can be personal computer, server or the network equipment etc.) performs all or part of the steps of the method described in the various embodiments of the present invention.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), the various media that can store program code such as magnetic or disk.

Claims

A kind of memory device, which is characterized in that the memory device includes:

Nonvolatile memory NVM；

NVM controller, it is connected by Double Data Rate DDR bus with Memory Controller Hub, the NVM controller carries out accessing operation to the NVM according to the order of the Memory Controller Hub, and carries out data transmission on the part DQS signal line in the DDR bus with the Memory Controller Hub.
Memory device as described in claim 1, it is characterized in that, the DDR bus includes multi-group data bus, every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the NVM controller carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, and first group of data/address bus is any group in the multi-group data bus.
Memory device as claimed in claim 2, it is characterized in that, the NVM controller carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, comprising:

The NVM controller carries out the transmission of target data, at least one of the data that the target data includes the data of the NVM to be written and reads out from the NVM according to first DQS signal on the DQ signal wire in first group of data/address bus with the Memory Controller Hub；

During DQ signal wire in first group of data/address bus transmits the target data, the NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal.
Memory device as claimed in claim 3, which is characterized in that the target data includes the first object data read out from the NVM,

The NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal, comprising:

During DQ signal wire in first group of data/address bus transmits the first object data, the NVM controller sends the first data according to first DQS signal on the second DQS signal line in first group of data/address bus, and first data include the mark of the first object data and at least one of the memory address of the first object data.
Memory device as claimed in claim 4, which is characterized in that first data further include at least one of following information:

Have been written into the mark of the data in the NVM；

Indicate whether the information for successfully writing data into the NVM；And

Indicate the information of the state of the data buffer storage in the NVM controller.
Memory device as described in any one of claim 3-5, which is characterized in that the target data includes the second target data of the NVM to be written,

The NVM controller carries out data transmission on the second DQS signal line in first group of data/address bus with the Memory Controller Hub according to first DQS signal, comprising:

During DQ signal wire in first group of data/address bus transmits second target data, the NVM controller receives the second data according to first DQS signal on the second DQS signal line in first group of data/address bus, and second data include the mark of second target data.
Such as memory device of any of claims 1-6, which is characterized in that the NVM includes at least one RANK.
A kind of Memory Controller Hub, which is characterized in that the Memory Controller Hub includes:

Scheduler, for receiving the access request of processor；

Rambus interface, it is connected by Double Data Rate DDR bus with memory device, the rambus interface is according to the access request, the order for accessing the nonvolatile memory NVM in the memory device is sent to the memory device, and is carried out data transmission on the part DQS signal line in the DDR bus with the memory device.
Memory Controller Hub as claimed in claim 8, it is characterized in that, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the rambus interface carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, and first group of data/address bus is any group in the multi-group data bus.
Memory Controller Hub as claimed in claim 9, it is characterized in that, the rambus interface carries out data transmission on the DQ signal wire and the second DQS signal line in first group of data/address bus with the memory device according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, comprising:

The rambus interface carries out the transmission of target data, at least one of the data that the target data includes the data of the NVM to be written and reads out from the NVM according to first DQS signal on the DQ signal wire in first group of data/address bus with the memory device；

During DQ signal wire in first group of data/address bus transmits the target data, the rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal.
Memory Controller Hub as claimed in claim 10, which is characterized in that the target data includes the first object data read out from the NVM,

The rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, comprising:

During DQ signal wire in first group of data/address bus transmits the first object data, the rambus interface receives the first data according to first DQS signal on the second DQS signal line in first group of data/address bus, and first data include the mark of the first object data and at least one of the memory address of the first object data.
Memory Controller Hub as claimed in claim 11, which is characterized in that first data further include at least one of following information:

Have been written into the mark of the data in the NVM；

Indicate whether the information for successfully writing data into the NVM；And

Indicate the information of the state of the data buffer storage in the NVM controller.
Memory Controller Hub as described in any one of claim 10-12, which is characterized in that the target data includes the second target data of the NVM to be written,

The rambus interface carries out data transmission on the second DQS signal line in first group of data/address bus with the memory device according to first DQS signal, comprising:

During DQ signal wire in first group of data/address bus transmits second target data, the rambus interface sends the second data according to first DQS signal on the second DQS signal line in first group of data/address bus, and second data include the mark of second target data.
Memory Controller Hub as described in any one of claim 8-13, which is characterized in that the NVM includes at least one RANK.
A kind of data buffer storage device, which is characterized in that the data buffer storage device between Memory Controller Hub and memory device, and by Double Data Rate DDR bus respectively with the Memory Controller Hub and institute Memory device to be stated to be connected, the memory device includes nonvolatile memory NVM,

The data buffer storage device includes:

Rambus interface, during the Memory Controller Hub sends the data of the NVM to be written to the memory device or receives from the memory device from the data that the NVM is read, the data transmitted on the part DQS signal line in DDR bus described in the rambus interface；

Buffer, the data arrived for caching the rambus interface.
Data buffer storage device as claimed in claim 15, it is characterized in that, the DDR bus includes multi-group data bus, wherein every group of data/address bus includes DQ signal wire, the first DQS signal line and the second DQS signal line, the rambus interface is according to the first DQS signal transmitted on the first DQS signal line in first group of data/address bus, the data transmitted on DQ signal wire and the second DQS signal line in first group of data/address bus are received, first group of data/address bus is any group in the multi-group data bus.
A kind of computer system, which is characterized in that including memory device such as of any of claims 1-7, and the Memory Controller Hub as described in any one of claim 8-14.
Computer system as claimed in claim 17, which is characterized in that the computer system further includes the data buffer storage device as described in claim 15 or 16.