CN104111902B - Communication system and method based on Double Data Rate synchronous DRAM interface - Google Patents
Communication system and method based on Double Data Rate synchronous DRAM interface Download PDFInfo
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Abstract
The present invention relates to mobile terminal, discloses a kind of communication system and method based on Double Data Rate synchronous DRAM interface.In the present invention, the master controller of communication system is communicated by simplifying Double Data Rate synchronous DRAM interface with from controller, the interface includes 6 signal wires, chip selection signal (CS#), positive clock signals (CK), negative clock signal (CK#), read-write selection signal (WE#) are output signal in the host controller, are being input signal from controller；Data-signal (DQ), data strobes (DQS) are input/output signal；DQS and CK is carried out data transmission with frequency using DQS upper and lower bilateral edge.High speed data transfer can be achieved using only 6 signal wires, baseband communication processor and application processor are respectively used to by master controller and from controller, solve the problems, such as that traditional UART interface transmission rate deficiency and USB software exploitation transplanting are excessively complicated.
Description
Technical field
The present invention relates to mobile terminal, more particularly to one kind realizes application processor (AP) and baseband communication processor (CP)
Between high speed data transfer simplification Double Data Rate synchronous DRAM (SDDR) interface communication system and method.
Background technology
As mobile communication technology develops rapidly, from 2G before to current 3G, particularly future soon will be commercial
4G LTE broadband wireless communication technologies so that the downstream transmission speed of wireless data improves rapidly, downlink transfer speed
It is required that the level from original several Mbps to Mbps up to a hundred, uplink speed has also reached several Mbps to tens Mbps water
It is flat.And in the 2G epoch, traditional utilization standard RS232 is asynchronous serial communication interface (referred to as " UART ") in baseband communication processing
The mechanics of communication carried out data transmission between device (CP) and application processor (AP) can not meet to require in speed.At present
Typically using USB interface technology or UART technologies as the communication interface between its high speed CP and AP, but both technologies is scarce
It is trapped in the 3G epoch clearly, and has arrived the 4G epoch and more seemed awkward.
Although USB interface technology obtains a wide range of applications on PC, for mobile phone terminal, because its software moves
The complexity and software development workload estimate of plant are huge, often cause an AP and CP data transfers communication because software issue makes
Launch plan is slowly even delayed, and the software complexities of USB technologies has been it as the communication between high speed CP and AP
Interface causes huge obstacle；Additionally while USB2.0high speed theoretical bandwidth is up to 480Mbps, but due to association
The influence of expense and Design of System Software is discussed, its usual actual effective bandwidth is typically difficult more than 200Mbps.
UART interface technology is due to the general principle of asynchronous transmission asynchronous-sampling, in order to ensure the stabilization of UART data transfers
Property, its internal sample rate, which typically requires, reaches 16 times of the baud rate that interface can be supported or so, and due to chip internal
The clock sampling rate of controller is typically up to also merely able to accomplish 100M~200M or so, so results in UART interface speed most
Ideal can only accomplish 10Mbps or so baud rate.UART speed, it is also substantially enough for existing 3G technology, but arrived 4G
The LTE epoch, when the communication speed requirement between CP and AP reaches descending Mbps up to a hundred and tens Mbps concurrent, this transmission skill
Art will be helpless.
The content of the invention
It is an object of the invention to provide a kind of communication based on Double Data Rate synchronous DRAM SDDR interfaces
System and method so that high speed data transfer is realized using only 6 signal wires, not only reduces the complexity of controller design,
Design cost is reduced, and eliminates the time overhead of cumbersome command access, improves effective transmission bandwidth of interface.
In order to solve the above technical problems, embodiments of the present invention, which provide one kind, is based on Double Data Rate synchronous dynamic random
The communication system of memory interface, comprising：Master controller and from controller；The master controller is synchronous by simplifying Double Data Rate
Dynamic RAM SDDR interfaces communicate with described from controller；
The SDDR interfaces include 6 signal wires, respectively transmit chip selection signal CS#, positive clock signals CK, negative clock letter
Number CK#, read-write selection signal WE#, data-signal DQ and data strobes DQS；Wherein, described CS#, CK, CK#, WE#
Be output signal in the master controller, it is described be input signal from controller；Described DQ, DQS believe for input and output
Number；The DQS and CK carries out DQ data transfers simultaneously with frequency, and using the upper and lower bilateral edge of the DQS.
Embodiments of the present invention additionally provide a kind of communication based on Double Data Rate synchronous DRAM interface
Method, comprise the steps of：
The transmission state of a control machine of the write control signal control master controller of the ahb bus of master controller is started working and connect
State of a control machine is received not work；
When monitoring that the transmission state machine of master controller is started working, check in the transmission FIFO of master controller whether there is number
According to；
When there are data in the transmission FIFO of master controller, chip selection signal CS# and read-write after combinational logic are controlled
Selection signal WE# is low level, and the transmission FIFO of master controller data are got into master controller by internal ahb bus
Transmission shift register in；
Control master controller sends bilateral edge of the shift register with primary signal DQS_WE inside master controller, together
Step is got to data on data DQ signal wires by turn, while DQS_WE signals are after delay phase-locked loop DLL postpones 1/4 phase
Signal, get on data strobe pulse DQS signal line；
It is described from monitoring control devices to CS# and when WE# is low level, start described in opened from the user equipment of controller
Beginning work, it is bilateral along alignment DQ data centers mode, the DQ data of synchronized sampling input, by described in the deposit of DQ data by DQS
The data for receiving shift register are got to from control from the reception shift register of controller, and by internal ahb bus
In the reception FIFO of device.
Embodiments of the present invention additionally provide a kind of communication based on Double Data Rate synchronous DRAM interface
Method, comprise the steps of：
The write control signal of the ahb bus of master controller realizes that the reception state of a control machine of master controller is started working and sent out
State of a control machine is sent not work；CS# is arranged to low level, WE# is arranged to high level；
It is low level from monitoring control devices to CS# and after WE# is high level, controls the transmission shift register from controller
Data are got on DQ signal wires by turn, data change with the double edge synchronizations of DQS；
DQS_RD is produced, as main control by 1/4 phase delay after DLL modules inside DQS signal arrival master controller
The control signal of the reception shift register of device, sample the DQ data of input；And shift LD will be received by internal ahb bus
The data of device are got in the reception FIFO of master controller.
In terms of existing technologies, the master controller of communication system is same by simplifying Double Data Rate for embodiment of the present invention
Step dynamic RAM interface communicates with from controller, and the interface includes 6 signal wires, chip selection signal (CS#), positive clock letter
Number (CK), negative clock signal (CK#), read-write selection signal (WE#) are output signal in the host controller, are being from controller
Input signal；Data-signal (DQ), data strobes (DQS) are input/output signal；DQS and CK utilizes with frequency
DQS upper and lower bilateral edge carries out data transmission.High speed data transfer can be achieved using only 6 signal wires, not only reduce control
The complexity of device design processed, reduces design cost, and eliminates the time overhead of cumbersome command access, improves interface
Effective transmission bandwidth.
In addition, the CS# is a frame synchronizing signal, when needing communication, the CS# is arranged to low level；
The WE# is used for controlling read-write to select, and when the WE# is high level, the communication system carries out read operation；When
When the WE# is low level, the communication system carries out write operation；
Wherein, when the communication system carries out read operation, the signal on the DQ and DQS signal line is by described from control
Device is sent to the master controller；
When the communication system carries out write operation, the signal on the DQ and DQS signal line is passed by the master controller
It is sent to described from controller.
Using only 1 single data DQ and 1 DQS latch signal, it can maximize to simplify and delete interface signal, delete original
The address signal relevant with addressing, command signal in ddr interface signal, it is only necessary to support read-write operation, be readily achieved corresponding hardware
Design.
In addition, the master controller includes：AHB interface module, reception FIFO, reception state of a control machine, reception displacement are posted
Storage, delay phase-locked loop DLL, state of a control machine is sent, FIFO is sent, sends shift register, combinational logic and two directions' inputing
Output buffer；
Exported after the bus clock signal BUSCLK of the AHB interface module is delayed as CK, it is delayed it is anti-phase after
Export as CK#, exported after the DLL delay locks as DQS；The write control signal PWRITE of the AHB interface module
CS# and WE# outputs are produced after the reception state of a control machine, the transmission state of a control machine, the combinational logic；It is described
The write data signal PWDATA of AHB interface module is through the transmission FIFO, transmission shift register, two directions' inputing output buffer
Exported afterwards as DQ；
DQS as input controls the reception shift register after the DLL delay locks；DQ as input
The AHB interface module is input to after the two directions' inputing output buffer, reception shift register, the reception FIFO.
In addition, described control and select described from the transmission from controller together from the input signal CS# and WE# of controller
State machine or user equipment；The bilateral trigger signal along as the reception shift register latch data of the DQS,
Or the trigger signal for sending shift register and writing out data.
In addition, the master controller is located in baseband communication processor CP, it is described to be located at application processor AP from controller
In；By the master controller and described realize that the data between the CP and the AP communicate from controller；
The AP, which also has, to be sent request signal GPIO_TxReq and receives request signal GPIO_RxReq output ends, described
CP also have send interrupt signal GPIO_Tx and receive interrupt signal GPIO_Rx inputs, the GPIO_TxReq with it is described
GPIO_Tx connections, the GPIO_RxReq are connected with the GPIO_Rx.
Baseband communication processor (CP) and application processor (AP) are respectively used to by master controller and from controller, is solved
Using traditional UART interface transmission rate deficiency between CP and AP, or developed using USB software and transplant the problem of excessively complicated.
In addition, application processor AP and baseband communication processor CP enter the flow of row data communication such as by SDDR interfaces
Under：
Initialized first：The packet that application processor AP and baseband communication processor CP make an appointment according to both sides
Head size configures respective receiving channel, carries out the preparation for receiving other side's data packet header information, wherein, header packet information includes：Number
According to type, data packet length；The CP and the AP are by the master controller and described realize that data communicate from controller；Institute
Master controller is stated to be located in Communication processor CP, it is described to be located at from controller in application processor AP；
CP sends data to AP：The CP directly transmits data packet head, after the CP has sent control sequence, waits institute
State AP one GPIO_RxReq rising edge of transmission to interrupt to the CP, followed by the effective packet of transmission；
The AP has received control sequence, and is configured according to header packet information from controller, is ready for effective data packets
Reception；
The AP starts to send effective data packets by CP described in GPIO_RxReq rising edge interrupt notifications；
The CP configures master controller, and is again started up sending effective data packets；
The AP received data packets, until packet is sent.
AP sends AT orders to CP：The data configuration that the AP will be sent is got well and prepares to be sent out in a manner of DMA or CPU write
The CP is given, and is interrupted by GPIO_TxReq rising edge to notify the CP to be ready for data receiver；
After the master controller is configured and started by the CP, touched by tetra- control signals of WE#, CS#, CK and CK#
Send out AP described and start to send data, after the reception of data packet header information is completed, WE#, CS#, CK and tetra- signals of CK# are extensive again
It is disarmed state again, the AP also drags down GPIO_TxReq pins with idle condition after having sent header packet information；
After the CP parses the type of data packet to be received and length according to the header packet information received, institute has been configured
Master controller is stated, waits the AP to send GPIO_TxReq rising edge again and interrupts；
The CP is after the rising edge for receiving GPIO_TxReq interrupts, again by tetra- controls of WE#, CS#, CK and CK#
Signal triggers the AP and carries out data transmission, and starts reception effective data packets in a manner of DMA, until data receiver finishes.
By being respectively used to baseband communication processor (CP) and application processor (AP) by master controller and from controller, save
The time overhead of cumbersome command access has been removed, has improved effective transmission bandwidth of interface.
Brief description of the drawings
Fig. 1 is the communication based on Double Data Rate synchronous DRAM interface according to first embodiment of the invention
The structural representation of system；
Fig. 2 is the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention
The internal structure schematic diagram of middle master controller；
Fig. 3 is the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention
Write operation timing diagram；
Fig. 4 is the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention
Read operation timing diagram；
Fig. 5 is the communication system based on Double Data Rate synchronous DRAM interface of second embodiment of the invention
Realize the schematic diagram of CP and AP interconnection communications；
Fig. 6 is the communication means based on Double Data Rate synchronous DRAM interface of four embodiment of the invention
Realize that CP sends data to AP flow chart；
Fig. 7 is the communication means based on Double Data Rate synchronous DRAM interface of sixth embodiment of the invention
Realize that AP sends data to CP flow chart.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, each reality below in conjunction with accompanying drawing to the present invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order that reader more fully understands the application and proposes many ins and outs.But even if without these ins and outs and base
Many variations and modification in following embodiment, each claim of the application technical side claimed can also be realized
Case.
The first embodiment of the present invention is related to a kind of communication based on Double Data Rate synchronous DRAM interface
System, as shown in figure 1, the system includes：Master controller and from controller；Master controller is by simplifying Double Data Rate synchronous dynamic
Random access memory SDDR interfaces communicate with from controller.SDDR interfaces include 6 signal wires, respectively transmit chip selection signal
(CS#), positive clock signals (CK), negative clock signal (CK#), read-write selection signal (WE#), data-signal (DQ) and data strobe
Pulse signal (DQS)；Wherein, CS#, CK, CK#, WE# are output signal in the host controller, are being input letter from controller
Number；DQ, DQS are input/output signal；DQS and CK carries out DQ data biographies simultaneously with frequency, and using DQS upper and lower bilateral edge
It is defeated.
On SDDR physical interface signal, with reference to existing Double Data Rate synchronous DRAM interface standard
On the basis of (Double Data Rate (DDR) SDRAM Standard, referred to as " ddr interface "), using similar to SPI interface
Without the Mechanism of command of addressing, so deleting the address signal A0~An relevant with addressing in ddr interface signal, (n is such as
For 12 or 13), BA0/BA1 and command signal RAS, CAS；Simultaneously because master controller (MASTER sides) and from controller (SLAVE
Side) have a respective FIFO, and using only 1bit data wire DQ, thus delete numerous data-signal DQ1~DQ15, LDM,
UDM、DQS1；Mechanism of command only need support read-write operation, so remove again without using to signal CKE.Finally, SDDR interfaces
6 signal wires altogether：Piece selects CS#, positive and negative clock CK and CK#, read-write selection WE#, 1 single data DQ and 1 single data gate pulse
DQS.It because SDDR will only need 6 signal wires, can be easier to complete hardware design, be designed particularly convenient for PCB layout.In addition,
Traditional addressing system and numerous cumbersome Mechanism of command have been abandoned, read write command mechanism has been only used, not only reduces control
The complexity of device design processed, also reduces design cost.
Each signal function of SDDR interfaces is described as follows：
(1) chip selection signal CS# is a frame synchronizing signal, and when needing communication, CS# is arranged to low level；That is,
This signal during communication is needed to drag down.
(2) differential clocks are to CK and CK#, are triggered in CK with the DQS of frequency upper lower edge during due to data, cause transmission cycle
Half is shortened, therefore in order to ensure the stabilization of transmission cycle and ensure the correct transmission of data, this requires that CK's is upper and lower
It is accurately controlled along spacing some.But because the change of the environmental factors such as temperature will cause the CK upper lower change along spacing,
Therefore correction can be played a part of by introducing anti-phase CK#.
(3) read and write selection signal WE# to be used for controlling read-write to select, when WE# is high level, communication system carries out reading behaviour
Make；When WE# is low level, communication system carries out write operation.
(4) 1 single data DQ and 1 DQS latch signal is used only, maximizes to simplify and deletes interface signal.Wherein DQS and when
Clock CK carries out DQ data transfers simultaneously with frequency, and using the bilateral edges of above and below DQS, data transmission rate is reached Bus Clock Rate
2 times.When communication system carries out read operation, the signal on DQ and DQS signal line from controller by being sent to master controller；
When communication system carries out write operation, the signal on DQ and DQS signal line is sent to from controller by master controller.
Refer to shown in Fig. 2, be to realize that one kind of master controller is internal to realize block diagram, master controller includes：AHB interface mould
Block, FIFO is received, state of a control machine is received, receives shift register, delay phase-locked loop DLL, send state of a control machine, send
FIFO, send shift register, combinational logic and two directions' inputing output buffer；Wherein, state machine and user equipment are sent
Independently of each other, that is, independent control is sent and received.
The bus clock signal BUSCLK of AHB interface module is delayed rear as CK outputs, delayed anti-phase conduct afterwards
CK# is exported, and is exported after DLL delay locks as DQS；The received control shapes of write control signal PWRITE of AHB interface module
State machine, produce CS# and WE# outputs after sending state of a control machine, combinational logic；The write data signal PWDATA of AHB interface module
Exported after sending FIFO, send shift register, two directions' inputing output buffer as DQ.DQS as input prolongs through DLL
Late after locking, control receives shift register；As input DQ through two directions' inputing output buffer, receive shift register,
AHB host interface modules are input to after receiving FIFO.
MASTER sides SDDR controllers (i.e. master controller) specific work process is described as follows：When MASTER will be to SLAVE
When carrying out write operation, its essence is the transmission FIFO to SDDR controllers carries out write operation.Now, the control of writing of ahb bus is believed
Number realize that sending state of a control machine starts working and receive state of a control machine and do not work；Once send state machine to start working, then
Check and send whether FIFO there are data.If there is data, the CS# after combinational logic drags down piece choosing and effectively drags down and write with WE#
Effectively, and the data for sending FIFO are got to by internal ahb bus and sent in shift register；And then control sends displacement
Register gets to data on DQ signal wires with the bilateral edges of primary signal DQS_WE inside MASTER controllers, synchronization by turn,
And signal of the DQS_WE signals after DLL postpones about 1/4 phase, get on DQS signal line.SLAVE ends are (i.e. from control
Device) monitor CS# it is low it is low with WE# after, start from the start-up operation of the user equipment of controller, and bilateral along right by DQS
Neat DQ data centers mode, the DQ data of synchronized sampling input.Interface signal specifically writes sequential, and reference is as shown in figure 3, MASTER
The original DQS_WE signals of side produce DQS after DLL about 1/4 phase delay, DQ data is schemed by DQS synchronized samplings
Shown in dotted line -- DQS is about adopted near the central point of DQ valid data windows, it is ensured that SLAVE sides sampled data it is correct
Property.
Similarly, substantially it is that the reception FIFO to master controller is read when MASTER will carry out read operation to SLAVE
Operation.Now the reception state of a control machine of master controller is started working and sends state of a control machine and do not work, and SLAVE ends are monitoring
It will be got to by turn on DQ signal wires from the data in the transmission FIFO of controller with after WE# height to CS# is low, data are double with DQS
Edge synchronization changes；And by about 1/4 phase delay, caused DQS_ after DLL modules inside DQS signal arrival master controller
Control signals of the RD as MASTER reception shift register, sample the DQ data of input.Interface signal specifically reads sequential, ginseng
Examine as shown in figure 4, DQ data synchronously change with DQS, i.e., the dotted line shown in figure -- DQ period divisions point and DQS's is bilateral
Along alignment, such DQS DQS_RE inside the MASTER sides after DLL about 1/4 phase delay again, it is ensured that MASTER hits
According to correctness.External interface read-write sequence figure does not embody related the internal signal DQS_WE and DQS_RD of controller DLL.
SDDR controllers (i.e. from controller) realization mechanism of SLAVE sides is similar with MASTER sides, CS#, WE#, CK and CK#
Four signals are changed into input signal, and CS# and WE# cooperate with to control it to send state machine or user equipment work together.Save
DLL modules, and trigger signal and sendaisle of the DQS bilateral edge as receiving channel shift register latch data are gone
Shift register writes out the trigger signal of data, and specifically, DQS's is bilateral along as the reception shift register from controller
The trigger signal of latch data, or send the trigger signal that shift register writes out data.
In order to improve efficiency of transmission, SDDR interface specifications suggest that the FIFO depth at MASTER and SLAVE ends is both configured to 16,
FIFO width is 32bit, and data frame length is 32bit.SDDR reference classes can be up to than the CK clock frequencies of ddr interface
200MHz, it is assumed that when the MASTER ends each data of control send and receive, the time interval between two adjacent data frames is
1CK is equivalent to 1*2=2bit.According to the read-write sequence waveform of diagram, significant figure is transmitted in the time in the frame that CS# is dragged down
According to 32bit, and invalid data occupies 1.5CK and is equivalent to 1.5*2=3bit, bilateral then every along sample mode based on DQS
Second reception or send transmission effective bandwidth be 200M*2*32bit/ (32+2+3)=346Mbps, it is such transmission effect
Effective transmission speed of the rate than USB2.0High Speed is also higher by much.By data it can be seen that SDDR proposed by the present invention
Interface, its transmission bandwidth can meet current 4G even 5G mobile communication in future high speed requirements well.
Compared with prior art, the master controller of communication system of the present invention is deposited by simplifying Double Data Rate synchronous dynamic random
Memory interface communicates with from controller, and the interface includes 6 signal wires, chip selection signal (CS#), positive clock signals (CK), it is negative when
Clock signal (CK#), read-write selection signal (WE#) are output signal in the host controller, are being input signal from controller；Number
It is believed that number (DQ), data strobes (DQS) are input/output signal；DQS and CK utilizes the upper and lower double of DQS with frequency
Edge carries out data transmission.High speed data transfer can be achieved using only 6 signal wires, not only reduce answering for controller design
Miscellaneous degree, design cost is reduced, and eliminate the time overhead of cumbersome command access, improve effective transmission belt of interface
It is wide.
Second embodiment of the present invention is related to a kind of communication based on Double Data Rate synchronous DRAM interface
System.Second embodiment has done further improvement on the basis of first embodiment, mainly thes improvement is that：In the present invention
In second embodiment, master controller is located in baseband communication processor CP, is located at from controller in application processor AP；Pass through
Master controller and realize that the data between CP and AP communicate from controller, as shown in Figure 5.
In addition, AP, which also has, sends request signal GPIO_TxReq and reception request signal GPIO_RxReq output ends, CP
Also having and send interrupt signal GPIO_Tx and receive interrupt signal GPIO_Rx inputs, GPIO_TxReq is connected with GPIO_Tx,
GPIO_RxReq is connected with GPIO_Rx.
When AP will send AT orders to CP, read operation is carried out equivalent to communication system, AP is notified by GPIO_TxReq
CP is ready for read operation, CP master controller by tetra- control signals of WE#, CS#, CK and CK# trigger AP from controller
Start to send data, CP receives data, until data receiver finishes.When CP will send data to AP, equivalent to communication system
Write operation is carried out, CP master controller triggers AP by tetra- control signals of WE#, CS#, CK and CK# and prepares to receive data, treats AP
After controller is ready to, pass through GPIO_RxReq notify CP carry out data transmission, AP receive data, until data receiver
Finish.
Baseband communication processor (CP) and application processor (AP) are respectively used to by master controller and from controller, can be compared with
Good meets in 4G LTE intelligent platform schemes, baseband communication processor CP and the requirement of application processor AP high speed data transfers
(up 75Mbps and descending 150Mbps), solve using traditional UART interface transmission rate deficiency between CP and AP, or adopt
The problem of excessively complicated is transplanted with USB software exploitation.
Third embodiment of the invention is related to a kind of communication party based on Double Data Rate synchronous DRAM interface
Method, comprise the steps of：
The write control signal control of the ahb bus of master controller sends state of a control machine and starts working and receive state of a control
Machine does not work；
When monitoring that the transmission state machine of master controller is started working, check in the transmission FIFO of master controller whether there is number
According to；
When there are data in the transmission FIFO of master controller, chip selection signal CS# and read-write after combinational logic are controlled
Selection signal WE# is low level, and the transmission FIFO of master controller data are got into master controller by internal ahb bus
Transmission shift register in；
Control master controller sends bilateral edge of the shift register with primary signal DQS_WE inside master controller, together
Step is got to data on data DQ signal wires by turn, while signal of the DQS_WE signals after DLL postpones 1/4 phase, gets to
On data strobe pulse DQS signal line；
From monitoring control devices to CS# and when WE# is low level, start the user equipment start-up operation from controller,
It is bilateral along alignment DQ data centers mode by DQS, the DQ data of synchronized sampling input, DQ data are stored in connecing from controller
Receive in shift register, and the data for receiving shift register are got to by reception FIFO from controller by internal ahb bus
In.
Four embodiment of the invention is related to a kind of communication party based on Double Data Rate synchronous DRAM interface
Method.4th embodiment has done further improvement on the basis of the 3rd embodiment, mainly thes improvement is that：Implement the 4th
In mode, baseband communication processor CP realizes that data communicate with application processor AP by master controller and from controller；Master control
Device processed is located in CP, is located at from controller in AP.That is, application processor AP and Communication processor CP pass through SDDR interfaces
Standard carries out data communication, and CP sides are MASTER, and AP sides are SLAVE, realize that the high-speed data between AP and CP leads to using SDDR
News.By being respectively used to baseband communication processor (CP) and application processor (AP) by master controller and from controller, eliminate
The time overhead of cumbersome command access, improve effective transmission bandwidth of interface.
Specifically, CP sends data to AP, as shown in fig. 6, before carrying out data transmission, AP and CP are pre- according to both sides
The data packet head size first arranged configures respective receiving channel, carries out the preparation for receiving other side's data packet header information, wherein, bag
Header includes：Data type, data packet length.That is, during initialization, AP sides and CP sides are all made an appointment according to both sides
Data packet head size configure the reception SDDR passages of its side, carry out the preparation for receiving other side's data packet header information, packet header
In generally comprise data type (order or data), the information such as data packet length.
During carrying out data transmission, CP directly transmits data packet head, after CP has sent control sequence, waits AP hairs
Send one to receive request signal GPIO_RxReq rising edges to interrupt to CP, followed by the effective packet of transmission；AP has received control
Sequence processed, and configured according to header packet information from controller, it is ready for the reception of effective data packets；AP passes through GPIO_RxReq
Rising edge interrupt notification CP starts to send effective data packets；CP configures master controller, and is again started up sending effective data packets；AP
Received data packet, until packet is sent.
In addition, after packet is sent, specifically, after AP is received, will lead to from the reception of controller
Road is configured to the state that initialization prepares received data packet head, and GPIO_RxReq outputs are configured into low level, prepares next
The reception of secondary packet.
Fifth embodiment of the invention is related to a kind of communication party based on Double Data Rate synchronous DRAM interface
Method, comprise the steps of：
The write control signal of the ahb bus of master controller realizes that receiving state of a control machine starts working and send state of a control
Machine does not work；CS# is arranged to low level, WE# is arranged to high level；
It is low level from monitoring control devices to CS# and after WE# is high level, controls the transmission shift register from controller
Data are got on DQ signal wires by turn, data change with the double edge synchronizations of DQS；
DQS_RD is produced, as main control by 1/4 phase delay after DLL modules inside DQS signal arrival master controller
The control signal of the reception shift register of device, sample the DQ data of input；And shift LD will be received by internal ahb bus
The data of device are got in the reception FIFO of master controller.
Sixth embodiment of the invention is related to a kind of communication party based on Double Data Rate synchronous DRAM interface
Method.6th embodiment has done further improvement on the basis of the 5th embodiment, mainly thes improvement is that：Implement the 6th
In mode, baseband communication processor CP realizes that data communicate with application processor AP by master controller and from controller；Master control
Device processed is located in CP, is located at from controller in AP；By being respectively used to baseband communication processor by master controller and from controller
(CP) time overhead of cumbersome command access and application processor (AP), is eliminated, improves effective transmission bandwidth of interface.
Specifically, AP sides send AT orders and give CP sides, as shown in fig. 7, before carrying out data transmission, AP and CP according to
The data packet head size that both sides make an appointment configures respective receiving channel, carries out the preparation for receiving other side's data packet header information,
Wherein, header packet information includes：Data type, data packet length.
During carrying out data transmission, the side with DMA or CPU write is got well and prepared to the data configuration that AP will be sent first
Formula is sent to CP, and the rising edge by sending request signal GPIO_TxReq is interrupted to notify CP to be ready for data receiver；
After master controller is configured and started by CP, trigger AP by tetra- control signals of WE#, CS#, CK and CK# and start to send data,
After the reception of data packet header information is completed, WE#, CS#, tetra- signals of CK and CK# revert to disarmed state again, and AP has been sent
Also GPIO_TxReq pins are dragged down with idle condition after header packet information.
After CP parses the type of data packet to be received and length according to the header packet information received, main control has been configured
Device, wait AP to send GPIO_TxReq rising edge again and interrupt；CP is after the rising edge for receiving GPIO_TxReq interrupts, again
AP is triggered by tetra- control signals of WE#, CS#, CK and CK# and carries out data transmission, and starts reception significant figure in a manner of DMA
According to bag, until data receiver finishes.
In addition, after data receiver finishes, specifically, after CP is received, the receiving channel of master controller is matched somebody with somebody
It is set to the state that initialization prepares received data packet head；GPIO_TxReq outputs are then configured to low level by AP after having sent, accurate
The transmission of standby packet next time.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific embodiment of the present invention,
And in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (11)
1. a kind of communication system based on Double Data Rate synchronous DRAM interface, it is characterised in that include：Main control
Device and from controller；The master controller by simplify Double Data Rate synchronous DRAM SDDR interfaces with it is described from control
Device communication processed；
The SDDR interfaces only include 6 signal wires, respectively transmit chip selection signal CS#, positive clock signals CK, negative clock signal
CK#, read-write selection signal WE#, data-signal DQ and data strobes DQS；Wherein, described CS#, CK, CK#, WE# exist
Be output signal in the master controller, it is described be input signal from controller；Described DQ, DQS are input/output signal；
The DQS and CK carries out DQ data transfers simultaneously with frequency, and using the upper and lower bilateral edge of the DQS.
2. the communication system according to claim 1 based on Double Data Rate synchronous DRAM interface, its feature
It is, the CS# is a frame synchronizing signal, and when needing communication, the CS# is arranged to low level；
The WE# is used for controlling read-write to select, and when the WE# is high level, the communication system carries out read operation；When described
When WE# is low level, the communication system carries out write operation；
Wherein, when the communication system carries out read operation, the signal on the DQ and DQS signal line is passed by described from controller
It is sent to the master controller；
When the communication system carries out write operation, the signal on the DQ and DQS signal line is sent to by the master controller
It is described from controller.
3. the communication system according to claim 2 based on Double Data Rate synchronous DRAM interface, its feature
It is, the master controller includes：AHB interface module, FIFO is received, state of a control machine is received, receives shift register, delay
Phaselocked loop DLL, state of a control machine is sent, FIFO is sent, sends shift register, combinational logic and two directions' inputing output buffering
Device；
The bus clock signal BUSCLK of the AHB interface module is delayed rear as CK outputs, delayed anti-phase conduct afterwards
CK# is exported, and is exported after the DLL delay locks as DQS；The write control signal PWRITE of the AHB interface module is through institute
CS# and WE# outputs are produced after stating the state of a control machine that receives, the transmission state of a control machine, the combinational logic；The AHB connects
The write data signal PWDATA of mouth mold block makees after the transmission FIFO, transmission shift register, two directions' inputing output buffer
Exported for DQ；
DQS as input controls the reception shift register after the DLL delay locks；DQ as input is through institute
The AHB interface module is input to after stating two directions' inputing output buffer, reception shift register, the reception FIFO.
4. the communication system according to claim 3 based on Double Data Rate synchronous DRAM interface, its feature
Be, it is described controlled together from the input signal CS# and WE# of controller and select the transmission state machine from controller or
User equipment；The bilateral trigger signal along as the reception shift register latch data of the DQS, or the hair
Shift register is sent to write out the trigger signal of data.
5. the communication system based on Double Data Rate synchronous DRAM interface according to any one of Claims 1-4
System, it is characterised in that the master controller is located in baseband communication processor CP, described to be located at application processor AP from controller
In；By the master controller and described realize that the data between the CP and the AP communicate from controller；
The AP, which also has, to be sent request signal GPIO_TxReq and receives request signal GPIO_RxReq output ends, and the CP is also
With transmission interrupt signal GPIO_Tx and interrupt signal GPIO_Rx inputs are received, the GPIO_TxReq and GPIO_
Tx connections, the GPIO_RxReq are connected with the GPIO_Rx.
A kind of 6. communication of communication system as claimed in claim 1 based on Double Data Rate synchronous DRAM interface
Method, it is characterised in that comprise the steps of：
The write control signal control of the ahb bus of master controller sends state of a control machine and starts working and receive state of a control machine not
Work；
When monitoring that the transmission state machine of master controller is started working, check in the transmission FIFO of master controller whether there are data；
When there are data in the transmission FIFO of master controller, the chip selection signal CS# after combinational logic and read-write is controlled to select
Signal WE# is low level, and the transmission FIFO of master controller data are got to the hair of master controller by internal ahb bus
Send in shift register；
Control master controller sends bilateral edge of the shift register with primary signal DQS_WE inside master controller, synchronously will
Data are got on data DQ signal wires by turn, while letter of the DQS_WE signals after delay phase-locked loop DLL postpones 1/4 phase
Number, get on data strobe pulse DQS signal line；
From monitoring control devices to CS# and when WE# is low level, start the user equipment from controller and start working,
It is bilateral along alignment DQ data centers mode by DQS, the DQ data of synchronized sampling input, DQ data are stored in described from controller
Reception shift register in, and the data for receiving shift register are got to by reception from controller by internal ahb bus
In FIFO.
7. according to the method for claim 6, it is characterised in that baseband communication processor CP and application processor AP passes through institute
State master controller and it is described from controller realize data communicate；The master controller is located in the CP, described from controller position
In the AP；Comprise the steps of：
The data packet head size that the AP and CP makes an appointment according to both sides configures respective receiving channel, carries out reception pair
The preparation of square data packet header information, wherein, header packet information includes：Data type, data packet length；
The CP directly transmits data packet head, and after the CP has sent control sequence, waiting the AP to send a reception please
Signal GPIO_RxReq rising edges are asked to interrupt to the CP, followed by the effective packet of transmission；
The AP has received control sequence, and is configured according to header packet information from controller, is ready for connecing for effective data packets
Receive；
The AP starts to send effective data packets by CP described in GPIO_RxReq rising edge interrupt notifications；
The CP configures master controller, and is again started up sending effective data packets；
The AP received data packets, until packet is sent.
8. according to the method for claim 7, it is characterised in that after the packet is sent, also comprising following
Step：
After the AP is received, the shape of initialization preparation received data packet head will be configured to from the receiving channel of controller
State, and GPIO_RxReq outputs are configured to low level, prepare the reception of packet next time.
A kind of 9. communication of communication system as claimed in claim 1 based on Double Data Rate synchronous DRAM interface
Method, it is characterised in that comprise the steps of：
The write control signal of the ahb bus of master controller realizes that the reception state of a control machine of master controller is started working and sends control
State machine processed does not work；CS# is arranged to low level, WE# is arranged to high level；
It is low level from monitoring control devices to CS# and after WE# is high level, controls number from the transmission shift register of controller
According to getting to by turn on DQ signal wires, data change with the double edge synchronizations of DQS；
DQS_RD is produced, as master controller by 1/4 phase delay after DLL modules inside DQS signal arrival master controller
The control signal of shift register is received, samples the DQ data of input；And shift register will be received by internal ahb bus
Data, which are got to, to be received in FIFO.
10. according to the method for claim 9, it is characterised in that baseband communication processor CP passes through with application processor AP
The master controller and it is described from controller realize data communicate；The master controller is located in the CP, described from controller
In the AP；
Comprise the steps of：
The data packet head size that the AP and CP makes an appointment according to both sides configures respective receiving channel, carries out reception pair
The preparation of square data packet header information, wherein, header packet information includes：Data type, data packet length；
The data configuration that the AP will be sent is got well and prepares to be sent to the CP in a manner of DMA or CPU write, and passes through transmission
Request signal GPIO_TxReq rising edge is interrupted to notify the CP to be ready for data receiver；
After the master controller is configured and started by the CP, pass through tetra- control signals of WE#, CS#, CK and CK# and trigger institutes
State AP to start to send data, after the reception of data packet header information is completed, WE#, CS#, tetra- signals of CK and CK# revert to again
Disarmed state, the AP also drag down GPIO_TxReq pins with idle condition after having sent header packet information；
After the CP parses the type of data packet to be received and length according to the header packet information received, the good master is configured
Controller, wait the AP to send GPIO_TxReq rising edge again and interrupt；
The CP is after the rising edge for receiving GPIO_TxReq interrupts, again by tetra- control signals of WE#, CS#, CK and CK#
Trigger the AP and carry out data transmission, and start reception effective data packets in a manner of DMA, until data receiver finishes.
11. according to the method for claim 10, it is characterised in that after the data receiver finishes, also comprising following
Step：
After the CP is received, the receiving channel of master controller is configured to the state of initialization preparation received data packet head；
GPIO_TxReq outputs are then configured to low level by the AP after having sent, and prepare the transmission of packet next time.
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| CN106294224B (en) * | 2015-05-13 | 2019-10-25 | 瑞昱半导体股份有限公司 | Storage system and its memory entities interface circuit |
| KR102328014B1 (en) * | 2015-08-24 | 2021-11-18 | 삼성전자주식회사 | Device including single wire interface and data processing system having the same |
| CN108139993B (en) * | 2016-08-29 | 2020-06-16 | 华为技术有限公司 | Memory device, memory controller, data cache device and computer system |
| CN110958058B (en) * | 2019-11-25 | 2022-02-08 | 大唐半导体科技有限公司 | FPGA platform wireless communication baseband debugging method and device |
| CN112363962B (en) * | 2020-10-30 | 2024-06-25 | 深圳市汇顶科技股份有限公司 | Data communication method, system, electronic device and computer storage medium |
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| CN102231143A (en) * | 2011-07-04 | 2011-11-02 | 浙江大学 | Safe and reusable single program initiation (SPI) peripheral interface circuit |
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| CN102567261A (en) * | 2010-12-31 | 2012-07-11 | 联芯科技有限公司 | Enhanced SPI (serial peripheral interface) controller, communication system of enhanced SPI and data transmission method |
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| CN102347081A (en) * | 2010-07-30 | 2012-02-08 | 联芯科技有限公司 | Method for calibrating phase of DQS (bidirectional data strobe) delay for DDR (double data rate) controller and apparatus thereof |
| CN102567261A (en) * | 2010-12-31 | 2012-07-11 | 联芯科技有限公司 | Enhanced SPI (serial peripheral interface) controller, communication system of enhanced SPI and data transmission method |
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Application publication date: 20141022 Assignee: Shanghai Li Ke Semiconductor Technology Co., Ltd. Assignor: Leadcore Technology Co., Ltd. Contract record no.: 2018990000159 Denomination of invention: Communication system and method on basis of double-speed synchronous dynamic random access memory interface Granted publication date: 20171219 License type: Common License Record date: 20180615 |