CN104111902A - Communication system and method on basis of double-speed synchronous dynamic random access memory interface - Google Patents
Communication system and method on basis of double-speed synchronous dynamic random access memory interface Download PDFInfo
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Abstract
The invention relates to a mobile terminal and discloses a communication system and method on the basis of a double-speed synchronous dynamic random access memory interface. A master controller of the communication system is communicated with a slave controller through the simple double-speed synchronous dynamic random access memory interface. The double-speed synchronous dynamic random access memory interface comprises six signal lines, chip-selection signals (CS#), positive time clock signals (CK), negative clock signals (CK#), read-write selection signals (WE#) are output signals in the master controller and input signals in the slave controller, digital signals (DQ) and data strobe pulse signals (DQS) are input and output signals, the DQS and the CK are same in frequency, and the upper and lower edges of the DQS are used for data transmission. High-speed data transmission can be realized by only six signals lines, the master controller and the slave controller are respectively used for a baseband communication processor and an application processor, and the problems that a conventional UART (universal asynchronous receiver/transmitter) interface is low in transmission speed and USB (universal serial bus) software development and transplant are too complicated are solved.
Description
Technical field
The present invention relates to mobile terminal, particularly one realizes communication system and the method for simplification Double Data Rate synchronous DRAM (SDDR) interface of high speed data transfer between application processor (AP) and baseband communication processor (CP).
Background technology
Along with mobile communication technology develops rapidly, from 2G before 3G up till now, particularly following soon by commercial 4G LTE broadband wireless mechanics of communication, the up-downgoing transfer rate of wireless data is improved rapidly, the level of the requirement of downlink transfer speed from original several Mbps to Mbps up to a hundred, uplink speed has also reached the level of several Mbps to tens Mbps.And in the 2G epoch, traditional standard RS232 that utilizes is that the mechanics of communication that asynchronous serial communication interface (being called for short " UART ") carries out data transmission between baseband communication processor (CP) and application processor (AP) cannot meet the demands in speed.At present general USB interface technology or the UART technology of adopting be as the communication interface between its high speed CP and AP, but the defect of these two kinds of technology is very obvious in the 3G epoch, more seems awkward and arrived the 4G epoch.
Although USB interface technology obtains a wide range of applications on PC, but for mobile phone terminal, because complicacy and the software development workload estimate of its software transplanting are huge, often make an AP and the communication of CP data transmission slowly even delay because software issue makes launch plan, the software complexity of USB technology has caused huge obstacle for it as the communication interface between high speed CP and AP; Although the theoretical bandwidth of USB2.0high speed is up to 480Mbps in addition, due to the impact of protocol overhead and Design of System Software, its actual effective bandwidth is generally difficult to exceed 200Mbps conventionally.
UART interfacing is due to the ultimate principle of asynchronous transmission asynchronous-sampling, in order to ensure the stability of UART data transmission, its internal sample rate generally all requires to reach 16 times of left and right of the baud rate that interface can support, and be also merely able to accomplish 100M～200M left and right, so just cause the most desirable baud rate that can only accomplish about 10Mbps of UART interface rate because the clock sampling rate of chip internal controller is generally the highest.The speed of UART, also substantially enough for existing 3G technology, but arrived the 4G LTE epoch, when the communication speed between CP and AP requires to reach descending Mbps up to a hundred and tens Mbps when concurrent, this transmission technology will be helpless.
Summary of the invention
The object of the present invention is to provide a kind of communication system and method based on Double Data Rate synchronous DRAM SDDR interface, make only to use 6 signal wires to realize high speed data transfer, not only reduce the complexity of controller design, reduce design cost, and saved the time overhead of loaded down with trivial details command access, improve effective transmission bandwidth of interface.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of communication system based on Double Data Rate synchronous DRAM interface, comprise: master controller and from controller; Described master controller is communicated by letter from controller with described by simplifying Double Data Rate synchronous DRAM SDDR interface;
Described SDDR interface comprises 6 signal wires, is respectively transmission chip selection signal CS#, positive clock signal CK, negative clock signal CK#, read-write selection signal WE#, data-signal DQ and data strobe pulse signal DQS; Wherein, described CS#, CK, CK#, WE# are output signal in described master controller, described from controller, be input signal; Described DQ, DQS are input/output signal; Described DQS and described CK are frequently same, and utilize the upper and lower bilateral edge of described DQS to carry out DQ data transmission simultaneously.
Embodiments of the present invention also provide a kind of communication means based on Double Data Rate synchronous DRAM interface, comprise following steps:
The transmission state of a control machine of the write control signal control master controller of the ahb bus of master controller is started working and is received state of a control machine and do not work;
When the transmission state machine that monitors master controller is started working, check in the transmission FIFO of master controller whether have data;
Have data in the transmission FIFO of master controller time, chip selection signal CS# and the read-write controlled after combinational logic select signal WE# to be low level, and the data of the transmission FIFO of master controller are got in the transmission shift register of master controller by inner ahb bus;
Control the transmission shift register of master controller along with the bilateral edge of the inner original signal DQS_WE of master controller, synchronously data are got to by turn on data DQ signal wire, the signal of DQS_WE signal after delay phase-locked loop DLL postpones 1/4 phase place, gets on data strobe pulse DQS signal wire simultaneously;
Described from monitoring control devices to CS# and when WE# is low level, described in starting, start working from the accepting state machine of controller, bilateral along alignment DQ data center mode by DQS, the DQ data of synchronized sampling input, DQ data are deposited in described from the reception shift register of controller, and by inner ahb bus, the data that receive shift register are got to from the reception FIFO of controller.
Embodiments of the present invention also provide a kind of communication means based on Double Data Rate synchronous DRAM interface, comprise following steps:
The reception state of a control machine that the write control signal of the ahb bus of master controller is realized master controller is started working and is sent state of a control machine and do not work; CS# is set to low level, and WE# is set to high level;
From monitoring control devices to CS#, be after low level and WE# are high level, control and from the transmission shift register of controller, data are got to DQ signal wire by turn, data are along with the bilateral edge of DQS synchronously changes;
DQS signal arrives after the inner DLL module of master controller through 1/4 phase delay, produces DQS_RD, as the control signal of the reception shift register of master controller, the DQ data of sampling input; And by inner ahb bus, the data that receive shift register are got in the reception FIFO of master controller.
Embodiment of the present invention in terms of existing technologies, the master controller of communication system is by simplifying Double Data Rate synchronous DRAM interface and communicating by letter from controller, this interface comprises 6 signal wires, it is output signal that signal (WE#) is selected in chip selection signal (CS#), positive clock signal (CK), negative clock signal (CK#), read-write in master controller, being input signal from controller; Data-signal (DQ), data strobe pulse signal (DQS) are input/output signal; DQS and CK are frequently same, and utilize the upper and lower bilateral edge of DQS to carry out data transmission.Only use 6 signal wires can realize high speed data transfer, not only reduced the complexity of controller design, reduced design cost, and saved the time overhead of loaded down with trivial details command access, improved effective transmission bandwidth of interface.
In addition, described CS# is a frame synchronizing signal, and in the time that needs are communicated by letter, described CS# is set to low level;
Described WE# is used for controlling read-write and selects, and in the time that described WE# is high level, described communication system is carried out read operation; In the time that described WE# is low level, described communication system is carried out write operation;
Wherein, in the time that described communication system is carried out read operation, the signal on described DQ and DQS signal wire is sent to described master controller by described from controller;
In the time that described communication system is carried out write operation, the signal on described DQ and DQS signal wire is sent to described from controller by described master controller.
Only use 1 single data DQ and 1 DQS latch signal, can maximize and simplify delete interface signal, deleted address signal, command signal relevant with addressing in original ddr interface signal, only need to support read-write operation, be easy to corresponding hardware design.
In addition, described master controller comprises: AHB interface module, reception FIFO, reception state of a control machine, reception shift register, delay phase-locked loop DLL, transmission state of a control machine, transmission FIFO, transmission shift register, combinational logic and two-way inputoutput buffer;
The bus clock signal BUSCLK of described AHB interface module is delayed rear as CK output, delayed anti-phase afterwards as CK# output, after described DLL delay lock, exports as DQS; The write control signal PWRITE of described AHB interface module produces CS# and WE# output after described reception state of a control machine, described transmission state of a control machine, described combinational logic; The write data signal PWDATA of described AHB interface module exports as DQ after described transmission FIFO, transmission shift register, two-way inputoutput buffer;
After described DLL delay lock, control described reception shift register as the DQS inputting; DQ as input is input to described AHB interface module after described two-way inputoutput buffer, reception shift register, described reception FIFO.
In addition, the described input signal CS# from controller controls and selects described from the transmission state machine from controller or accepting state machine together with WE#; The bilateral edge of described DQS is as the trigger pip of described reception shift register latch data, or described transmission shift register writes out the trigger pip of data.
In addition, described master controller is arranged in baseband communication processor CP, is describedly arranged in application processor AP from controller; By described master controller with describedly realize the data communication between described CP and described AP from controller;
Described AP also has the signal of sending request GPIO_TxReq and receives request signal GPIO_RxReq output terminal, described CP also has the look-at-me GPIO_Tx of transmission and receive interruption signal GPIO_Rx input end, described GPIO_TxReq is connected with described GPIO_Tx, and described GPIO_RxReq is connected with described GPIO_Rx.
Be respectively used to baseband communication processor (CP) and application processor (AP) by master controller with from controller, solve and between CP and AP, adopted traditional UART interface transfer rate deficiency, or adopted USB software development to transplant too complicated problem.
In addition, the flow process that application processor AP and baseband communication processor CP carry out data communication by SDDR interface is as follows:
First carry out initialization: the data packet head size configure that application processor AP and baseband communication processor CP make an appointment according to both sides receiving cable separately, carry out the preparation that receives the other side's data packet head information, wherein, header packet information comprises: data type, data packet length; Described CP and described AP are by described master controller and describedly realize data communication from controller; Described master controller is arranged in Communication processor CP, is describedly arranged in application processor AP from controller;
CP sends data to AP: described CP directly sends data packet head, when described CP sends after control sequence, waits for that described AP sends a GPIO_RxReq rising edge and interrupts to described CP, more then sends active data bag;
Described AP receives control sequence, and configures from controller according to header packet information, prepares to carry out the reception of effective data packets;
Described AP starts to send effective data packets by CP described in GPIO_RxReq rising edge interrupt notification;
Described CP configuration master controller, and again start transmission effective data packets;
Described AP receives packet, until Packet Generation is complete.
AP sends AT order to CP: the data configuration that described AP will send get well and the mode of preparing to write with DMA or CPU sends to described CP, and interrupts notifying described CP preparation to carry out data receiver by the rising edge of GPIO_TxReq;
After described CP configures described master controller and starts, pass through WE#, CS#, tetra-control signals of CK and CK# trigger described AP and start to send data, complete after the reception of data packet head information WE#, CS#, tetra-signals of CK and CK# revert to disarmed state again, and described AP sends and also GPIO_TxReq pin dragged down after header packet information with in idle condition;
When described CP parses after the type of data packet and length that will receive according to the header packet information of receiving, configure described master controller, wait for that described AP sends the rising edge interruption of GPIO_TxReq again;
Described CP has no progeny in the rising edge of receiving GPIO_TxReq, again by WE#, and CS#, tetra-control signals of CK and CK# trigger described AP and carry out data transmission, and start reception effective data packets in the mode of DMA, until data receiver is complete.
By being respectively used to baseband communication processor (CP) and application processor (AP) by master controller with from controller, save the time overhead of loaded down with trivial details command access, improve effective transmission bandwidth of interface.
Brief description of the drawings
Fig. 1 is according to the structural representation of the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention;
Fig. 2 is the inner structure schematic diagram of master controller in the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention;
Fig. 3 is the write operation sequential chart of the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention;
Fig. 4 is the read operation sequential chart of the communication system based on Double Data Rate synchronous DRAM interface of first embodiment of the invention;
Fig. 5 is the schematic diagram that the communication system based on Double Data Rate synchronous DRAM interface of second embodiment of the invention realizes CP and AP connection communication;
Fig. 6 is the process flow diagram that the communication means based on Double Data Rate synchronous DRAM interface of four embodiment of the invention is realized CP and send data to AP;
Fig. 7 is the process flow diagram that the communication means based on Double Data Rate synchronous DRAM interface of sixth embodiment of the invention is realized AP and send data to CP.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in the each embodiment of the present invention, in order to make reader understand the application better, many ins and outs are proposed.But, even without these ins and outs and the many variations based on following embodiment and amendment, also can realize the each claim of the application technical scheme required for protection.
The first embodiment of the present invention relates to a kind of communication system based on Double Data Rate synchronous DRAM interface, and as shown in Figure 1, this system comprises: master controller and from controller; Master controller is by simplifying Double Data Rate synchronous DRAM SDDR interface and communicating by letter from controller.SDDR interface comprises 6 signal wires, is respectively transmission chip selection signal (CS#), positive clock signal (CK), negative clock signal (CK#), read-write selection signal (WE#), data-signal (DQ) and data strobe pulse signal (DQS); Wherein, CS#, CK, CK#, WE# are output signal in master controller, being input signal from controller; DQ, DQS are input/output signal; DQS and CK are frequently same, and utilize the upper and lower bilateral edge of DQS to carry out DQ data transmission simultaneously.
About the physical interface signal of SDDR, with reference to existing Double Data Rate synchronous DRAM interface standard (Double Data Rate (DDR) SDRAM Standard, be called for short " ddr interface ") basis on, employing is similar to the Mechanism of command of SPI interface without addressing, so deleted the address signal A0～An relevant with addressing (n such as be 12 or 13), BA0/BA1 and command signal RAS, CAS in ddr interface signal; All there is FIFO separately due to master controller (MASTER side) with from controller (SLAVE side), and only use the data line DQ of 1bit, so delete numerous data-signal DQ1～DQ15, LDM, UDM, DQS1 simultaneously; Mechanism of command only needs to support read-write operation, so remove without the signal CKE using again.Finally, SDDR interface 6 signal wires altogether: sheet selects CS#, positive and negative clock CK and CK#, read-write to select WE#, 1 single data DQ and 1 single data strobe pulse DQS.Because SDDR will only need 6 signal wires, can be easier to hardware design, be especially convenient to PCB layout design.In addition, abandon traditional addressing mode and numerous loaded down with trivial details Mechanism of command, only used read write command mechanism, not only reduced the complexity of controller design, also reduced design cost.
Each signal function of SDDR interface is described as follows:
(1) chip selection signal CS# is a frame synchronizing signal, and in the time that needs are communicated by letter, CS# is set to low level; That is to say, while needing communication, this signal will drag down.
(2) differential clocks is to CK and CK#, during due to data, trigger with the edge up and down of DQS frequently at CK, cause transmission cycle to shorten half, therefore, in order to ensure the stable of transmission cycle and to guarantee the correct transmission of data, this just requires the accurate control that will have along spacing up and down of CK.But due to the change of the environmental factors such as temperature by cause CK up and down along the variation of spacing, therefore introduce anti-phase CK# and can play the effect of correction.
(3) read-write selects signal WE# to be used for controlling read-write selection, and in the time that WE# is high level, communication system is carried out read operation; In the time that WE# is low level, communication system is carried out write operation.
(4) only use 1 single data DQ and 1 DQS latch signal, maximize and simplify delete interface signal.Wherein DQS and clock CK be with frequently, and utilize the upper and lower bilateral edge of DQS to carry out DQ data transmission simultaneously, makes data transmission rate reach 2 times of Bus Clock Rate.In the time that communication system is carried out read operation, the signal on DQ and DQS signal wire is by being sent to master controller from controller; In the time that communication system is carried out write operation, the signal on DQ and DQS signal wire is sent to from controller by master controller.
Refer to shown in Fig. 2, be that block diagram is realized in the one inside of realizing master controller, master controller comprises: AHB interface module, reception FIFO, reception state of a control machine, reception shift register, delay phase-locked loop DLL, transmission state of a control machine, transmission FIFO, transmission shift register, combinational logic and two-way inputoutput buffer; Wherein, send state machine and accepting state machine separate, sending and receiving is independently controlled.
The bus clock signal BUSCLK of AHB interface module is delayed rear as CK output, delayed anti-phase afterwards as CK# output, after DLL delay lock, exports as DQS; The write control signal PWRITE of AHB interface module produces CS# and WE# output after receiving state of a control machine, sending state of a control machine, combinational logic; The write data signal PWDATA of AHB interface module exports as DQ after sending FIFO, sending shift register, two-way inputoutput buffer., after DLL delay lock, control and receive shift register as the DQS inputting; DQ as input is input to AHB main interface module after two-way inputoutput buffer, reception shift register, reception FIFO.
MASTER side SDDR controller (being master controller) specific works procedure declaration is as follows: in the time that MASTER will carry out write operation to SLAVE, its essence is the transmission FIFO of SDDR controller is carried out to write operation.Now, the write control signal of ahb bus is realized and is sent state of a control machine and start working and receive state of a control machine and do not work; Start working once send state machine, check whether send FIFO has data.If there are data, the CS# after combinational logic drags down sheet choosing effectively and WE# drags down with effect, and by inner ahb bus, the data that send FIFO is got in transmission shift register; And then control and send shift register along with the bilateral edge of the inner original signal DQS_WE of MASTER controller, synchronously data are got on DQ signal wire by turn, and the signal of DQS_WE signal after DLL postpones about 1/4 phase place got on DQS signal wire.SLAVE end (from controller) monitor the low and WE# of CS# low, start and start working from the accepting state machine of controller, and bilateral along alignment DQ data center mode, the DQ data of synchronized sampling input by DQS.Interface signal is specifically write sequential, reference as shown in Figure 3, the original DQS_WE signal of MASTER side produces DQS after about 1/4 phase delay of DLL, make DQ data by DQS synchronized sampling, i.e. dotted line shown in figure--DQS approximately adopts near the central point of DQ valid data window, guarantees the correctness of SLAVE side sampled data.
Similarly, in the time that MASTER will carry out read operation to SLAVE, essence is that the reception FIFO of master controller is carried out to read operation.Now the reception state of a control machine of master controller is started working and is sent state of a control machine and do not work, SLAVE end is monitoring after the low and WE# height of CS#, data from the transmission FIFO of controller are got on DQ signal wire by turn, and data are along with the bilateral edge of DQS synchronously changes; And DQS signal arrives after the inner DLL module of master controller through about 1/4 phase delay, the DQS_RD of generation is as the control signal of the reception shift register of MASTER, the DQ data of sampling input.Interface signal is specifically read sequential, reference as shown in Figure 4, DQ data are along with DQS synchronously changes, the cycle cut-point of i.e. dotted line shown in figure--DQ aligns with the bilateral edge of DQS, the DQS DQS_RE after about 1/4 phase delay of the inner DLL of MASTER side more like this, guarantees the correctness of MASTER sampled data.External interface read-write sequence figure does not embody internal signal DQS_WE and the DQS_RD that controller DLL is relevant.
SDDR controller (from controller) realization mechanism and the MASTER side of SLAVE side are similar, CS#, and WE#, tetra-signals of CK and CK# become input signal, and CS# works in coordination with to control it and sends state machine or the work of accepting state machine together with WE#.Save DLL module, and the trigger pip of data is write out on the bilateral edge of DQS as the trigger pip of receiving cable shift register latch data and sendaisle shift register, specifically, the bilateral trigger pip along the reception shift register latch data as from controller of DQS, or transmission shift register writes out the trigger pip of data.
In order to improve transfer efficiency, it is 32bit that the FIFO degree of depth of SDDR interface specification suggestion MASTER and SLAVE end is all set to 16, FIFO width, and Frame length is 32bit.SDDR reference class can be up to 200MHz than the CK clock frequency of ddr interface, supposes that when MASTER end is controlled each data input and data output, the time interval between two adjacent Frames is that 1CK is equivalent to 1*2=2bit.According to illustrated read-write sequence waveform, secured transmission of payload data 32bit in time in the frame dragging down at CS#, and all having taken 1.5CK, invalid data is equivalent to 1.5*2=3bit, based on DQS bilateral along sample mode p.s. reception or send transmission effective bandwidth be 200M*2*32bit/ (32+2+3)=346Mbps, such transfer efficiency also exceeds much than the effective transmission speed of USB2.0High Speed.Can find out by data the SDDR interface that the present invention proposes, its transmission bandwidth can meet current 4G 5G mobile communication high speed requirement even in the future well.
Compared with prior art, the master controller of communication system of the present invention is by simplifying Double Data Rate synchronous DRAM interface and communicating by letter from controller, this interface comprises 6 signal wires, it is output signal that signal (WE#) is selected in chip selection signal (CS#), positive clock signal (CK), negative clock signal (CK#), read-write in master controller, being input signal from controller; Data-signal (DQ), data strobe pulse signal (DQS) are input/output signal; DQS and CK are frequently same, and utilize the upper and lower bilateral edge of DQS to carry out data transmission.Only use 6 signal wires can realize high speed data transfer, not only reduced the complexity of controller design, reduced design cost, and saved the time overhead of loaded down with trivial details command access, improved effective transmission bandwidth of interface.
The second embodiment of the present invention relates to a kind of communication system based on Double Data Rate synchronous DRAM interface.The second embodiment has done further improvement on the first embodiment basis, and main improvements are: in second embodiment of the invention, master controller is arranged in baseband communication processor CP, is arranged in application processor AP from controller; Realize the data communication between CP and AP by master controller with from controller, as shown in Figure 5.
In addition, AP also has the signal of sending request GPIO_TxReq and receives request signal GPIO_RxReq output terminal, CP also has the look-at-me GPIO_Tx of transmission and receive interruption signal GPIO_Rx input end, and GPIO_TxReq is connected with GPIO_Tx, and GPIO_RxReq is connected with GPIO_Rx.
In the time that AP will send AT order to CP, be equivalent to communication system and carry out read operation, AP notifies CP to prepare to carry out read operation by GPIO_TxReq, the master controller of CP passes through WE#, CS#, tetra-control signals triggering AP of CK and CK# start to send data from controller, and CP receives data, until data receiver is complete.In the time that CP will send data to AP, be equivalent to communication system and carry out write operation, the master controller of CP passes through WE#, CS#, tetra-control signals of CK and CK# trigger AP and prepare to receive data, treat AP after controller is ready to, notify CP to carry out data transmission by GPIO_RxReq, AP receives data, until data receiver is complete.
Be respectively used to baseband communication processor (CP) and application processor (AP) by master controller with from controller, can meet preferably in 4G LTE intelligent platform scheme, baseband communication processor CP and application processor AP high speed data transfer require (up 75Mbps and descending 150Mbps), solve and between CP and AP, adopted traditional UART interface transfer rate deficiency, or adopted USB software development to transplant too complicated problem.
Third embodiment of the invention relates to a kind of communication means based on Double Data Rate synchronous DRAM interface, comprises following steps:
The write control signal control of the ahb bus of master controller sends state of a control machine and starts working and receive state of a control machine and do not work;
When the transmission state machine that monitors master controller is started working, check in the transmission FIFO of master controller whether have data;
Have data in the transmission FIFO of master controller time, chip selection signal CS# and the read-write controlled after combinational logic select signal WE# to be low level, and the data of the transmission FIFO of master controller are got in the transmission shift register of master controller by inner ahb bus;
Control the transmission shift register of master controller along with the bilateral edge of the inner original signal DQS_WE of master controller, synchronously data are got to by turn on data DQ signal wire, the signal of DQS_WE signal after DLL postpones 1/4 phase place, gets on data strobe pulse DQS signal wire simultaneously;
From monitoring control devices to CS# and when WE# is low level, start and start working from the accepting state machine of controller, bilateral along alignment DQ data center mode by DQS, the DQ data of synchronized sampling input, DQ data are deposited in from the reception shift register of controller, and by inner ahb bus, the data that receive shift register are got to from the reception FIFO of controller.
Four embodiment of the invention relates to a kind of communication means based on Double Data Rate synchronous DRAM interface.The 4th embodiment has done further improvement on the 3rd embodiment basis, and main improvements are: in the 4th embodiment, baseband communication processor CP and application processor AP realize data communication by master controller with from controller; Master controller is arranged in CP, is arranged in AP from controller.That is to say, application processor AP and Communication processor CP carry out data communication by SDDR interface standard, and CP side is MASTER, and AP side is SLAVE, and application SDDR realizes the high-speed data communications between AP and CP.By being respectively used to baseband communication processor (CP) and application processor (AP) by master controller with from controller, save the time overhead of loaded down with trivial details command access, improve effective transmission bandwidth of interface.
Specifically, CP sends data to AP, as shown in Figure 6, before carrying out data transmission, the data packet head size configure that AP and CP make an appointment according to both sides receiving cable separately, carry out the preparation that receives the other side's data packet head information, wherein, header packet information comprises: data type, data packet length.That is to say, when initialization, the reception SDDR passage of its side of data packet head size configure that AP side and CP side are all made an appointment according to both sides, carry out for the preparation that receives the other side's data packet head information, in packet header, generally comprise data type (order or data), the information such as data packet length.
Carrying out in data transmission procedure, CP directly sends data packet head, when CP sends after control sequence, waits for that AP sends one and receives request signal GPIO_RxReq rising edge and interrupt to CP, more then sends active data bag; AP receives control sequence, and configures from controller according to header packet information, prepares to carry out the reception of effective data packets; AP starts to send effective data packets by GPIO_RxReq rising edge interrupt notification CP; CP configures master controller, and again starts transmission effective data packets; AP receives packet, until Packet Generation is complete.
In addition, after Packet Generation is complete, specifically, after AP receives, prepare to receive the state of data packet head by be configured to initialization from the receiving cable of controller, and GPIO_RxReq output is configured to low level, prepare the reception of packet next time.
Fifth embodiment of the invention relates to a kind of communication means based on Double Data Rate synchronous DRAM interface, comprises following steps:
The write control signal of the ahb bus of master controller is realized and is received state of a control machine and start working and send state of a control machine and do not work; CS# is set to low level, and WE# is set to high level;
From monitoring control devices to CS#, be after low level and WE# are high level, control and from the transmission shift register of controller, data are got to DQ signal wire by turn, data are along with the bilateral edge of DQS synchronously changes;
DQS signal arrives after the inner DLL module of master controller through 1/4 phase delay, produces DQS_RD, as the control signal of the reception shift register of master controller, the DQ data of sampling input; And by inner ahb bus, the data that receive shift register are got in the reception FIFO of master controller.
Sixth embodiment of the invention relates to a kind of communication means based on Double Data Rate synchronous DRAM interface.The 6th embodiment has done further improvement on the 5th embodiment basis, and main improvements are: in the 6th embodiment, baseband communication processor CP and application processor AP realize data communication by master controller with from controller; Master controller is arranged in CP, is arranged in AP from controller; By being respectively used to baseband communication processor (CP) and application processor (AP) by master controller with from controller, save the time overhead of loaded down with trivial details command access, improve effective transmission bandwidth of interface.
Specifically, AP side sends AT order to CP side, as shown in Figure 7, before carrying out data transmission, the data packet head size configure that AP and CP make an appointment according to both sides receiving cable separately, carry out the preparation that receives the other side's data packet head information, wherein, header packet information comprises: data type, data packet length.
Carrying out in data transmission procedure, the data configuration that first AP will send is got well and the mode preparing to write with DMA or CPU sends to CP, and interrupts notifying CP to prepare to carry out data receiver by sending request the rising edge of signal GPIO_TxReq; After CP configures master controller and starts, pass through WE#, CS#, tetra-control signals of CK and CK# trigger AP and start to send data, complete after the reception of data packet head information WE#, CS#, tetra-signals of CK and CK# revert to disarmed state again, and AP sends and also GPIO_TxReq pin dragged down after header packet information with in idle condition.
When CP parses after the type of data packet and length that will receive according to the header packet information of receiving, configure master controller, wait for that AP sends the rising edge interruption of GPIO_TxReq again; CP has no progeny in the rising edge of receiving GPIO_TxReq, again by WE#, and CS#, tetra-control signals of CK and CK# trigger AP and carry out data transmission, and start reception effective data packets in the mode of DMA, until data receiver is complete.
In addition,, after data receiver is complete, specifically, after CP receives, the receiving cable of master controller is configured to the state of initialization preparation reception data packet head; After AP sends, GPIO_TxReq output is configured to low level, prepares the transmission of packet next time.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiments of the invention, and in actual applications, can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (11)
1. the communication system based on Double Data Rate synchronous DRAM interface, is characterized in that, comprises: master controller and from controller; Described master controller is communicated by letter from controller with described by simplifying Double Data Rate synchronous DRAM SDDR interface;
Described SDDR interface comprises 6 signal wires, is respectively transmission chip selection signal CS#, positive clock signal CK, negative clock signal CK#, read-write selection signal WE#, data-signal DQ and data strobe pulse signal DQS; Wherein, described CS#, CK, CK#, WE# are output signal in described master controller, described from controller, be input signal; Described DQ, DQS are input/output signal; Described DQS and described CK are frequently same, and utilize the upper and lower bilateral edge of described DQS to carry out DQ data transmission simultaneously.
2. the communication system based on Double Data Rate synchronous DRAM interface according to claim 1, is characterized in that, described CS# is a frame synchronizing signal, and in the time that needs are communicated by letter, described CS# is set to low level;
Described WE# is used for controlling read-write and selects, and in the time that described WE# is high level, described communication system is carried out read operation; In the time that described WE# is low level, described communication system is carried out write operation;
Wherein, in the time that described communication system is carried out read operation, the signal on described DQ and DQS signal wire is sent to described master controller by described from controller;
In the time that described communication system is carried out write operation, the signal on described DQ and DQS signal wire is sent to described from controller by described master controller.
3. the communication system based on Double Data Rate synchronous DRAM interface according to claim 2, it is characterized in that, described master controller comprises: AHB interface module, reception FIFO, reception state of a control machine, reception shift register, delay phase-locked loop DLL, transmission state of a control machine, transmission FIFO, transmission shift register, combinational logic and two-way inputoutput buffer;
The bus clock signal BUSCLK of described AHB interface module is delayed rear as CK output, delayed anti-phase afterwards as CK# output, after described DLL delay lock, exports as DQS; The write control signal PWRITE of described AHB interface module produces CS# and WE# output after described reception state of a control machine, described transmission state of a control machine, described combinational logic; The write data signal PWDATA of described AHB interface module exports as DQ after described transmission FIFO, transmission shift register, two-way inputoutput buffer;
After described DLL delay lock, control described reception shift register as the DQS inputting; DQ as input is input to described AHB interface module after described two-way inputoutput buffer, reception shift register, described reception FIFO.
4. the communication system based on Double Data Rate synchronous DRAM interface according to claim 2, it is characterized in that, the described input signal CS# from controller controls and selects described transmission state machine or accepting state machine from controller together with WE#; The bilateral edge of described DQS is as the trigger pip of described reception shift register latch data, or described transmission shift register writes out the trigger pip of data.
5. according to the communication system based on Double Data Rate synchronous DRAM interface described in claim 1 to 4 any one, it is characterized in that, described master controller is arranged in baseband communication processor CP, is describedly arranged in application processor AP from controller; By described master controller with describedly realize the data communication between described CP and described AP from controller;
Described AP also has the signal of sending request GPIO_TxReq and receives request signal GPIO_RxReq output terminal, described CP also has the look-at-me GPIO_Tx of transmission and receive interruption signal GPIO_Rx input end, described GPIO_TxReq is connected with described GPIO_Tx, and described GPIO_RxReq is connected with described GPIO_Rx.
6. the communication means based on Double Data Rate synchronous DRAM interface, is characterized in that, comprises following steps:
The write control signal control of the ahb bus of master controller sends state of a control machine and starts working and receive state of a control machine and do not work;
When the transmission state machine that monitors master controller is started working, check in the transmission FIFO of master controller whether have data;
Have data in the transmission FIFO of master controller time, chip selection signal CS# and the read-write controlled after combinational logic select signal WE# to be low level, and the data of the transmission FIFO of master controller are got in the transmission shift register of master controller by inner ahb bus;
Control the transmission shift register of master controller along with the bilateral edge of the inner original signal DQS_WE of master controller, synchronously data are got to by turn on data DQ signal wire, the signal of DQS_WE signal after delay phase-locked loop DLL postpones 1/4 phase place, gets on data strobe pulse DQS signal wire simultaneously;
Described from monitoring control devices to CS# and when WE# is low level, described in starting, start working from the accepting state machine of controller, bilateral along alignment DQ data center mode by DQS, the DQ data of synchronized sampling input, DQ data are deposited in described from the reception shift register of controller, and by inner ahb bus, the data that receive shift register are got to from the reception FIFO of controller.
7. the communication means based on Double Data Rate synchronous DRAM interface according to claim 6, is characterized in that, baseband communication processor CP and application processor AP are by described master controller and describedly realize data communication from controller; Described master controller is arranged in described CP, is describedly arranged in described AP from controller; Comprise following steps:
The data packet head size configure that described AP and described CP make an appointment according to both sides receiving cable separately, carries out the preparation that receives the other side's data packet head information, and wherein, header packet information comprises: data type, data packet length;
Described CP directly sends data packet head, when described CP sends after control sequence, waits for that described AP sends a reception request signal GPIO_RxReq rising edge and interrupts to described CP, more then sends active data bag;
Described AP receives control sequence, and configures from controller according to header packet information, prepares to carry out the reception of effective data packets;
Described AP starts to send effective data packets by CP described in GPIO_RxReq rising edge interrupt notification;
Described CP configuration master controller, and again start transmission effective data packets;
Described AP receives packet, until Packet Generation is complete.
8. the communication means based on Double Data Rate synchronous DRAM interface according to claim 7, is characterized in that, after described Packet Generation is complete, also comprises following steps:
After described AP receives, prepare to receive the state of data packet head by be configured to initialization from the receiving cable of controller, and GPIO_RxReq output is configured to low level, prepare the reception of packet next time.
9. the communication means based on Double Data Rate synchronous DRAM interface, is characterized in that, comprises following steps:
The reception state of a control machine that the write control signal of the ahb bus of master controller is realized master controller is started working and is sent state of a control machine and do not work; CS# is set to low level, and WE# is set to high level;
From monitoring control devices to CS#, be after low level and WE# are high level, control and from the transmission shift register of controller, data are got to DQ signal wire by turn, data are along with the bilateral edge of DQS synchronously changes;
DQS signal arrives after the inner DLL module of master controller through 1/4 phase delay, produces DQS_RD, as the control signal of the reception shift register of master controller, the DQ data of sampling input; And by inner ahb bus, the data that receive shift register are got to and received in FIFO.
10. the communication means based on Double Data Rate synchronous DRAM interface according to claim 9, is characterized in that, baseband communication processor CP and application processor AP are by described master controller and describedly realize data communication from controller; Described master controller is arranged in described CP, is describedly arranged in described AP from controller;
Comprise following steps:
The data packet head size configure that described AP and described CP make an appointment according to both sides receiving cable separately, carries out the preparation that receives the other side's data packet head information, and wherein, header packet information comprises: data type, data packet length;
The data configuration that described AP will send is got well and the mode of preparing to write with DMA or CPU sends to described CP, and interrupts notifying described CP to prepare to carry out data receiver by sending request the rising edge of signal GPIO_TxReq;
After described CP configures described master controller and starts, pass through WE#, CS#, tetra-control signals of CK and CK# trigger described AP and start to send data, complete after the reception of data packet head information WE#, CS#, tetra-signals of CK and CK# revert to disarmed state again, and described AP sends and also GPIO_TxReq pin dragged down after header packet information with in idle condition;
When described CP parses after the type of data packet and length that will receive according to the header packet information of receiving, configure described master controller, wait for that described AP sends the rising edge interruption of GPIO_TxReq again;
Described CP has no progeny in the rising edge of receiving GPIO_TxReq, again by WE#, and CS#, tetra-control signals of CK and CK# trigger described AP and carry out data transmission, and start reception effective data packets in the mode of DMA, until data receiver is complete.
11. communication meanss based on Double Data Rate synchronous DRAM interface according to claim 10, is characterized in that, after described data receiver is complete, also comprise following steps:
After described CP receives, the receiving cable of master controller is configured to the state of initialization preparation reception data packet head;
After described AP sends, GPIO_TxReq output is configured to low level, prepares the transmission of packet next time.
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