CN109800192B - Electronic equipment, FPGA chip and interface circuit thereof - Google Patents
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- CN109800192B CN109800192B CN201910044803.XA CN201910044803A CN109800192B CN 109800192 B CN109800192 B CN 109800192B CN 201910044803 A CN201910044803 A CN 201910044803A CN 109800192 B CN109800192 B CN 109800192B
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Abstract
The invention belongs to the technical field of integrated circuits, and provides electronic equipment, an FPGA chip and an interface circuit thereof. In the invention, by adopting the interface circuit comprising the clock module, the initialization module, the data channel module, the command/address control channel module and the input/output logic module, each module in the interface circuit is matched to finish data reading and writing between the FPGA and the DDR SDRAM, so that the interface circuit is used as a data bridge between the FPGA and the DDR SDRAM, the FPGA and the DDR SDRAM can be effectively combined, and the applicability of the combination of the FPGA and the DDR SDRAM is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to electronic equipment, an FPGA chip and an interface circuit thereof.
Background
At present, with the development of integrated circuits, on one hand, a Field-programmable gate Array (FPGA) is used as a semi-custom circuit in the Field of application-specific integrated circuits, and is widely applied to various fields due to the characteristics of reconfigurable performance, abundant logic resources, flexible input/output interfaces, and the like. On the other hand, a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is also widely used in many fields due to its high data transmission rate. Based on the characteristics of the FPGA and the DDR SDRAM, the combination of the FPGA and the DDR SDRAM can be widely applied to a plurality of fields such as an image video time sequence control system, an industrial control system and the like.
Because the DDR SDRAM has strict timing requirements, its logic control is complex, and further the DDR SDRAM needs a special interface circuit to implement data read/write operation, that is, signals such as command, address, data and the like transmitted by the memory controller of the FPGA need to be sent to the DDR SDRAM according to the format and electrical characteristics specified by the DDR, and receive read data of the DDR SDRAM.
At present, in order to ensure accurate and stable read-write operation of DDR SDRAM, the prior art is mainly implemented by using data selection pulse DQS hardcores in FPGA. However, although the DQS hardmac may adjust the clock phase, so that the DQS signal edge is in the middle of the DDR SDRAM data to ensure stable data transmission, for some FPGA devices without an embedded DQS hardmac, it is impossible to generate signal synchronization and sampling signals with offset phases, so that the FPGA and DDR SDRAM cannot be effectively combined, and the applicability of the combination of the FPGA and DDR SDRAM is reduced.
Therefore, it is necessary to provide a technical solution to solve the above technical problems.
Disclosure of Invention
In view of this, embodiments of the present invention provide an electronic device, an FPGA chip, and an interface circuit thereof, which are used as a data bridge between an FPGA and a DDR SDRAM, so that the FPGA and the DDR SDRAM are effectively combined, and the applicability of the combination of the FPGA and the DDR SDRAM is improved.
A first aspect of an embodiment of the present invention provides an interface circuit, configured to provide a communication interface between an FPGA chip and an external double-rate memory, where the interface circuit includes:
the clock module is used for generating a high-speed writing offset clock signal, a high-speed reading offset clock signal and a low-speed clock signal;
the initialization module is connected with the clock module and the double-rate memory and is used for working under the action of the low-speed clock signal and performing initialization setting on the double-rate memory after the double-rate memory is electrified;
the data path module is connected with the clock module, the memory controller in the FPGA chip and the input/output logic module, and is used for working under the action of the low-speed clock signal, receiving write data and a data enable signal sent by the memory controller in the FPGA chip when the memory controller in the FPGA chip carries out write data operation on the double-rate memory, and sending the write data and the data enable signal to the input/output logic module; when the memory controller in the FPGA chip performs data reading operation on the double-rate memory, the data path module receives data read out from the double-rate memory by the input-output logic module and sends the read data to the memory controller in the FPGA chip;
the command/address control access module is connected with the clock module, the memory controller in the FPGA chip and the input/output logic module, and is used for working under the action of the low-speed clock signal, receiving a read/write command and an address signal sent by the memory controller in the FPGA chip and sending the read/write command and the address signal to the input/output logic module;
the input/output logic module is connected with the clock module and the double-rate memory, and is configured to operate under the action of the low-speed clock signal, write data sent by a memory controller in the FPGA chip into the double-rate memory according to the data enable signal, the write command and the address signal under the action of the high-speed write offset clock signal, and read data stored in the double-rate memory according to the read command and the address signal under the action of the high-speed read offset clock signal.
A second aspect of the embodiments of the present invention provides an FPGA chip, which includes the above interface circuit.
A third aspect of the embodiments of the present invention provides an electronic device, which includes the FPGA chip.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: according to the invention, by adopting the interface circuit comprising the clock module, the initialization module, the data channel module, the command/address control channel module and the input/output logic module, each module in the interface circuit is matched to complete data reading and writing between the FPGA and the DDR SDRAM, so that the interface circuit is used as a data bridge between the FPGA and the DDR SDRAM, the FPGA and the DDR SDRAM can be effectively combined, and the applicability of the combination of the FPGA and the DDR SDRAM is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic block diagram of an interface circuit according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of an interface circuit according to another embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to illustrate the technical solution of the present invention, the following is illustrated by specific examples:
fig. 1 shows a module structure of an interface circuit 1 according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment are shown, which are detailed as follows:
as shown in fig. 1, an interface circuit 1 provided in the embodiment of the present invention is used for providing a communication interface between an FPGA chip 4 and an external double data rate memory DDR SDRAM 2, and the interface circuit 1 includes: a clock module 10, an initialization module 11, a data path module 12, a command/address control path module 13, and an input output logic module 14.
The clock module 10 is configured to generate a high-speed write offset clock signal, a high-speed read offset clock signal, and a low-speed clock signal;
the initialization module 11 is connected with the clock module 12 and the double-rate memory 2, and is used for working under the action of a low-speed clock signal and performing initialization setting on the double-rate memory 2 after the double-rate memory 2 is powered on;
the data path module 12 is connected with the clock module 10, the memory controller 3 in the FPGA chip 4 and the input/output logic module 14, and is configured to operate under the action of a low-speed clock signal, and when the memory controller 3 in the FPGA chip 4 performs a data writing operation on the double-rate memory 2, receive a data writing and data enabling signal sent by the memory controller 3 in the FPGA chip 4, and send the data writing and data enabling signal to the input/output logic module 14; when the memory controller 3 in the FPGA chip 4 reads data from the double-rate memory 2, the data path module 12 receives data read from the double-rate memory 2 by the input/output logic module 14, and sends the read data to the memory controller 3 in the FPGA chip 4;
the command/address control access module 13 is connected with the clock module 10, the memory controller 3 in the FPGA chip 4 and the input/output logic module 14, and is used for working under the action of a low-speed clock signal, receiving a read/write command and an address signal sent by the controller 3 in the FPGA chip 4, and sending the read/write command and the address signal to the input/output logic module 14;
and the input/output logic module 14 is connected with the clock module 10 and the double-rate memory 2, and is used for working under the action of a low-speed clock signal, writing write data sent by the memory controller 3 in the FPGA chip 4 into the double-rate memory 2 according to a data enable signal, a write command and an address signal under the action of a high-speed write offset clock signal, and reading data stored in the double-rate memory 2 according to a read command and the address signal under the action of a high-speed read offset clock signal.
In specific implementation, the write data, the read data, various commands, signals and the like sent by the memory controller 3 in the FPGA chip 4 are all carried out according to the requirements when the FPGA chip 4 is correspondingly set according to user design, that is, the write data, the read data, the various commands and signals sent by the memory controller 3 in the FPGA chip 4 are carried out according to the functions specifically realized by the FPGA chip 4; in addition, in this embodiment, the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14 in the interface circuit 1 are connected to each other two by two, and only a part of the connection relationship is illustrated in fig. 1.
It should be noted that, in the embodiment of the present invention, the DDR SDRAM is developed based on a Synchronous Dynamic Random Access Memory (SDRAM). Specifically, the SDRAM transfers data only once in one clock cycle and transfers data in a rising period of the clock, and the DDR SDRAM transfers data twice in one clock cycle and transfers data once in each of the rising period and the falling period of the clock, and thus is called a double data rate SDRAM.
In this embodiment, the interface circuit 1 including the clock module 10, the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14 is adopted, so that the interface circuit 1 can correctly receive the command of the memory controller 3 in the FPGA chip 4, and provide signals meeting the requirements of timing sequence and sequence to the DDR SDRAM, thereby realizing data read-write between the FPGA chip and the DDR SDRAM, solving the problem that the DDR SDRAM can still be used on an FPGA device without a DQS hard core, reducing design scale, lowering cost, facilitating production and debugging, and effectively improving market competitiveness of FPGA products in multiple fields.
Further, as an embodiment of the present invention, as shown in fig. 2, the clock module 10 includes a phase locked loop 100, a frequency divider 101, and a clock start/stop device 102.
The phase-locked loop 100 is connected to the input/output logic module 14, and is configured to generate a high-speed read offset clock signal and a high-speed write offset clock signal;
a frequency divider 101, connected to the phase-locked loop 100, the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14, for generating a corresponding low-speed clock signal according to the high-speed read offset clock signal or the high-speed write offset clock signal;
and the clock start-stop device 102 is connected with the frequency divider 101 and is used for controlling the time when the frequency divider 101 outputs the low-speed clock signal.
In specific implementation, the phase-locked loop 100 generates a high-speed clock signal according to an original low-speed clock signal provided by an external providing device, the frequency divider 101 divides the high-speed clock signal into low-speed clock signals in the same clock domain, and sends the low-speed clock signals to the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14, so that the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14 perform synchronous operations, while the clock start/stop 102 is responsible for accurate clock release time under the control of an external synchronization module or synchronizer and is further used for synchronizing the system, and other sub-modules also use the low-speed clock as a clock signal to ensure the synchronization of the system.
It should be noted that, in the embodiment of the present invention, when the interface circuit 1 operates in the write data mode, the phase-locked loop 100 generates a high-speed write offset clock signal according to an original low-speed clock signal provided by an external providing device, and the frequency divider 101 divides the high-speed write offset clock signal into a first low-speed clock signal of a same clock domain; when the interface circuit 1 operates in the read data mode, the phase locked loop 100 generates a high-speed read offset clock signal according to an original low-speed clock signal provided by an external providing device, and the frequency divider 101 divides the high-speed read offset clock signal into a second low-speed clock signal of the same clock domain.
In this embodiment, the clock module 10 including the phase-locked loop 100, the frequency divider 101, and the clock start/stop device 102 is adopted, so that the phase-locked loop 100 can generate a high-speed clock signal during data reading and writing, and the frequency divider 101 generates a clock signal for controlling the initialization module 11, the data path module 12, the command/address control path module 13, and the input/output logic module 14 to synchronously operate according to the high-speed clock signal, so that each module in the interface circuit 1 can synchronously operate, and it is avoided that the interface circuit 1 cannot perform correct data reading and writing due to asynchronous operation of its internal modules.
Further, the initialization module 11 performs initialization setting on the double rate memory 2, which includes but is not limited to setting of reset, clock enable, and register configuration.
Further, as an embodiment of the present invention, the interface circuit 1 provided in this embodiment may also perform read calibration before reading data, that is, the input/output logic module 14 writes fixed data into a preset address of the double-rate memory 2 according to a write command under the action of a high-speed write offset clock signal, reads the fixed data according to a read command under the action of a high-speed read offset clock signal, and performs read calibration on the double-rate memory 2 according to the written fixed data and the read fixed data; it should be noted that the preset address and the fixed data may be set according to a user design, and are not limited specifically here.
In specific implementation, before the data in the double-speed-rate memory 2 is read out, the input/output logic module 14 writes the fixed data B into the address a of the double-speed memory 2 according to the write command under the action of the high-speed write offset clock signal, and reads the fixed data B according to the read command under the action of the high-speed read offset clock signal. After reading the fixed data B, the input/output logic module 14 compares the read fixed data B with the written fixed data B, if the read fixed data B and the written fixed data B are the same, it indicates that the data reading process is correct, and if the read fixed data B and the written fixed data B are deviated, a corresponding message is output, so as to implement the calibration of the data reading process.
In this embodiment, the interface circuit 1 provided by the present invention can know in advance whether a failure occurs in the data reading process through the reading calibration before reading the data, and can further make a corresponding rescue measure in time, thereby avoiding that the FPGA chip and the double-rate memory cannot be effectively combined due to the problem in the data reading process.
Further, as an embodiment of the present invention, the input/output logic module 14 includes a serial-to-parallel converter, a high-speed clock port of the serial-to-parallel converter is connected to the clock module 10, and when the input/output logic module 14 reads out the data stored in the double-speed memory 2, the serial-to-parallel converter performs center point sampling on the read data, so as to ensure the accuracy of sampling during data reading, thereby ensuring that the data is accurately read out.
Further, as an embodiment of the present invention, the input/output logic module 14 includes a parallel-to-serial converter, a high-speed clock port of the parallel-to-serial converter is connected to the clock module 10, and when the input/output logic module 14 writes write data sent by the memory controller 3 in the FPGA chip 4 into the double data rate memory 2, the parallel-to-serial converter performs synchronous processing on the written data and the high-speed write offset clock signal.
It should be noted that, in this embodiment, the serial-to-parallel converter and the parallel-to-serial converter are respectively the same as the circuit structure and the operation principle of the existing serial-to-parallel converter and parallel-to-serial converter, and reference may be made to the prior art specifically, and details are not described here.
Further, as an embodiment of the present invention, the data path module 12 is further configured to receive a write delay parameter sent by the memory controller 3 in the FPGA chip 4 when the memory controller 3 in the FPGA chip 4 performs a write data operation on the double-rate memory 2, and perform a cache processing on the write data according to the write delay parameter.
Further, as an embodiment of the present invention, the data path module 12 is further configured to receive a read delay parameter sent by the input/output logic module 14 when the memory controller 3 in the FPGA chip 4 performs a data reading operation on the double data rate memory 2, and perform a cache processing on the read data according to the read delay parameter.
The operation principle of the interface circuit 1 provided by the present invention is specifically described below by taking the circuit shown in fig. 2 as an example, and the following details are described below:
as shown in fig. 2, when data read-write communication with the dual-speed multiplying factor memory 2 is required in an FPGA chip in a certain application scenario, the phase locked loop 100 in the clock module 10 generates a high speed clock signal of a high speed read offset clock signal and a high speed write offset clock signal from an externally input clock signal, the high speed clock signal is divided by the frequency divider 101 in the clock module 10, to generate a corresponding low speed clock signal and send the low speed clock signal to the initialization module 11, the data path module 12, the command/address control path module 13 and the input output logic module 14, so that the initialization module 11, the data path module 12, the command/address control path module 13 and the input/output logic module 14 operate synchronously according to the low-speed clock signal, the high speed read offset clock signal and the high speed write offset clock signal are sent to the input output logic module 14 at the same time.
When the initialization module 11 operates under the action of the low-speed clock signal provided by the clock module 10, the main function of the initialization module 11 is to perform initialization configuration on the dual-speed-magnification memory 2. When the memory controller in the FPGA chip 4 needs to write data into the double-rate memory 2 according to a command designed by a user in a specific application scenario, the memory controller 3 in the FPGA chip 4 sends corresponding write data and write data enable signals to the data path module 12, and the data path module 12 sends the write data and write data enable signals to the input/output logic module 14; meanwhile, the memory controller 3 in the FPGA chip 4 sends a corresponding write command and data write address signal to the command/address control path module 13, and the command/address control path module 13 sends the write command and data write address signal to the input/output logic module 14; when the input/output logic module 14 operates under the low-speed clock signal sent by the clock module 10, the input/output logic module 14 writes the write data sent by the memory controller 3 in the FPGA chip 4 into the corresponding address of the double-rate memory 2 under the action of the high-speed write offset clock signal according to the data enable signal, the write command and the data write address signal, so as to implement data write communication between the FPGA chip and the double-rate memory 2.
When a memory controller in the FPGA chip 4 needs to read data from the double-rate memory 2 according to a command designed by a user in a specific application scenario, the memory controller 3 in the FPGA chip 4 sends a corresponding read command and a data read address signal to the command/address control path module 13, the command/address control path module 13 sends the read command and the data read address signal to the input/output logic module 14, and the input/output logic module 14 reads data stored in a corresponding address in the double-rate memory 2 after receiving the read command and the data read address signal and sends the data read address signal to the memory controller 3 in the FPGA chip 4 through the data path module 12, so as to realize data read communication between the FPGA chip and the double-rate memory 2.
In this embodiment, the interface circuit 1 provided by the present invention provides a physical layer definition and an interface between the memory controller 3 of the FPGA chip 4 and the external DDR SDRAM 2, and by receiving a command from the memory controller 3 in the FPGA chip 4 and providing a signal satisfying the timing and sequence requirements to the DDR SDRAM 2, the FPGA device can be combined with the DDR SDRAM 2 without being limited by the model, and the purpose of high-speed transmission is achieved while the structure is simple, the cost is low, the logic scale is small, and the debugging is convenient, so that the combination of the FPGA chip and the DDR SDRAM can be applied to more occasions, thereby making the DDR SDRAM particles and the FPGA chip combined in the application scenario have obvious advantages.
Furthermore, the invention also provides an FPGA chip 4, and the FPGA chip 4 comprises an interface circuit 1 and a memory controller 3. It should be noted that, since the interface circuit 1 in the FPGA chip 4 provided in the embodiment of the present invention is the same as the interface circuit 1 in fig. 1 to 2, the specific working principle of the interface circuit 1 in the FPGA chip 4 provided in the embodiment of the present invention may refer to the foregoing detailed description about fig. 1 and 2, and is not repeated here.
Furthermore, the invention also provides electronic equipment which comprises the FPGA chip. It should be noted that, because the interface circuit included in the FPGA chip 4 in the electronic device provided in the embodiment of the present invention is the same as the interface circuit 1 shown in fig. 1 and fig. 2, the specific working principle of the FPGA chip 4 in the electronic device provided in the embodiment of the present invention may refer to the foregoing detailed description about fig. 1 and fig. 2, and is not described again here.
In the invention, by adopting the interface circuit comprising the clock module, the initialization module, the data channel module, the command/address control channel module and the input/output logic module, each module in the interface circuit is matched to finish data reading and writing between the FPGA and the DDR SDRAM, so that the interface circuit is used as a data bridge between the FPGA and the DDR SDRAM, the FPGA and the DDR SDRAM can be effectively combined, and the applicability of the combination of the FPGA and the DDR SDRAM is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An interface circuit for providing a communication interface between an FPGA chip and an external double rate memory, the interface circuit comprising:
the clock module is used for generating a high-speed writing offset clock signal, a high-speed reading offset clock signal and a low-speed clock signal;
the initialization module is connected with the clock module and the double-rate memory and is used for working under the action of the low-speed clock signal and performing initialization setting on the double-rate memory after the double-rate memory is electrified;
the data path module is connected with the clock module, the memory controller in the FPGA chip and the input/output logic module, and is used for working under the action of the low-speed clock signal, receiving write data and a data enable signal sent by the memory controller in the FPGA chip when the memory controller in the FPGA chip carries out write data operation on the double-rate memory, and sending the write data and the data enable signal to the input/output logic module; when the memory controller in the FPGA chip performs data reading operation on the double-rate memory, the data path module receives data read out from the double-rate memory by the input-output logic module and sends the read data to the memory controller in the FPGA chip;
the command/address control access module is connected with the clock module, the memory controller in the FPGA chip and the input/output logic module, and is used for working under the action of the low-speed clock signal, receiving a read/write command and an address signal sent by the memory controller in the FPGA chip and sending the read/write command and the address signal to the input/output logic module;
the input/output logic module is connected with the clock module and the double-rate memory, and is configured to operate under the action of the low-speed clock signal, write data sent by a memory controller in the FPGA chip into the double-rate memory according to the data enable signal, the write command and the address signal under the action of the high-speed write offset clock signal, and read data stored in the double-rate memory according to the read command and the address signal under the action of the high-speed read offset clock signal.
2. The interface circuit of claim 1, wherein the clock module comprises:
the phase-locked loop is connected with the input-output logic module and is used for generating the high-speed reading offset clock signal and the high-speed writing offset clock signal;
the frequency divider is connected with the phase-locked loop, the initialization module, the data path module, the command/address control path module and the input/output logic module and is used for generating a corresponding low-speed clock signal according to the high-speed read offset clock signal or the high-speed write offset clock signal;
and the clock start-stop device is connected with the frequency divider and is used for controlling the time of the frequency divider for outputting the low-speed clock signal.
3. The interface circuit of claim 1 or 2, wherein the initialization setting of the double rate memory by the initialization module comprises reset, clock enable, and register configuration.
4. The interface circuit of claim 3, wherein the input/output logic writes fixed data to a predetermined address of the double-rate memory according to the write command under the action of the high-speed write offset clock signal, reads the fixed data according to the read command under the action of the high-speed read offset clock signal, and performs read calibration on the double-rate memory according to the written fixed data and the read fixed data.
5. The interface circuit of claim 1, wherein the input/output logic module comprises a serial-to-parallel converter, a high-speed clock port of the serial-to-parallel converter is connected to the clock module, and when the input/output logic module reads out data stored in the double-speed memory, the serial-to-parallel converter performs center-point sampling on the read-out data.
6. The interface circuit according to claim 1, wherein the input/output logic module includes a parallel-to-serial converter, a high-speed clock port of the parallel-to-serial converter is connected to the clock module, and when the input/output logic module writes write data sent by a memory controller in the FPGA chip into the double-rate memory, the parallel-to-serial converter synchronizes the written data with the high-speed write offset clock signal.
7. The interface circuit of claim 1, wherein the data path module is further configured to receive a write delay parameter sent by a memory controller in the FPGA chip when the memory controller in the FPGA chip performs a write data operation on the double-rate memory, and perform a cache processing on the write data according to the write delay parameter.
8. The interface circuit of claim 1, wherein the data path module is further configured to receive a read delay parameter sent by the input/output logic module when a memory controller in the FPGA chip performs a read data operation on the double data rate memory, and perform a cache processing on read data according to the read delay parameter.
9. An FPGA chip comprising the interface circuit of any one of claims 1 to 8.
10. An electronic device, characterized in that it comprises an FPGA chip according to claim 9.
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| CN112017702B (en) * | 2019-05-31 | 2023-08-08 | 龙芯中科技术股份有限公司 | Memory interface circuit, PHY chip and processor |
| CN110347621B (en) * | 2019-06-24 | 2020-09-29 | 广东高云半导体科技股份有限公司 | FPGA connected with PSRAM memory and storage system |
| CN110727637B (en) * | 2019-12-18 | 2020-11-20 | 广东高云半导体科技股份有限公司 | FPGA chip and electronic equipment |
| CN114003526B (en) * | 2021-12-30 | 2022-04-01 | 中科声龙科技发展（北京）有限公司 | Method and circuit for accessing write data path of on-chip memory control unit |
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