CN108139992A

CN108139992A - Access the method and storage device of storage device

Info

Publication number: CN108139992A
Application number: CN201680057568.4A
Authority: CN
Inventors: 陈云; 宋昆鹏; 仇连根
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-08-09
Filing date: 2016-08-09
Publication date: 2018-06-08
Anticipated expiration: 2036-08-09
Also published as: CN108139992B; WO2018027535A1

Abstract

A kind of method and storage device for accessing storage device.The method includes：The first row instruction that the second access operation is carried out to the storage device is received, the first row instruction carries the first access address, which includes the first row address and the first read-write indicates information (S210)；According to the first read-write instruction information, it is read operation or write operation (S220) to determine first access operation；According to the first determining access operation, the preparation operation of the first determining access operation is carried out, preparation operation completes the read operation or the set-up procedure (S230) of the write operation for the storage device in preset time threshold；The row instruction that first access operation is carried out to the storage device is received, row instruction carries column address (S240)；According to first row address and the column address, the address space (S250) corresponding with the column address of first row address in the storage device is accessed.The storage device can identify access operation in advance, so as to extend the access response time.

Description

The method and storage equipment of access storage equipment

Technical field

This application involves computer fields, and more particularly, to the method and storage equipment of access storage equipment.

Background technique

Double Data Rate (Double Data Rate, DDR) technology has the characteristics that high bandwidth (reaching as high as 200Gbit/s), low latency (few tens of nano-seconds rank), the potentiality with bearing system interconnection.Since DDR bus is designed to directly access dynamic RAM (Dynamic Random Access Memory, DRAM) memory grain originally, therefore only needed for ten a few to tens of nanoseconds read and write access can be completed, time delay is very short.Central processing unit (Central Processing Unit, CPU the Memory Controller Hub in) is to develop joint conference (Joint Electron Device Engineering Council based on electronic engineering design, JEDEC Protocol Design and realization), the read-write delay that can be arranged are equally shorter.Therefore, in computer, there are under conditions of expansion equipment, for example: non-volatile memories (Non-volatile Memory, NVM) chip, field programmable gate array (Field-Programmable Gate Array, FPGA) chip, when CPU passes through these expansion equipments of DDR bus access, it may appear that accessing time sequence is unsatisfactory for DDR protocol requirement, causes expansion equipment can not be with CPU normal communication.For example, expansion equipment without replying correct data, causes CPU to collect the data of mistake, before the deadline so as to cause system mistake after CPU issues a read command.

The prior art proposes to utilize the command field retained in DDR bus protocol, expand read/write command in advance, when needing to initiate access request to expansion equipment, Memory Controller Hub first sends the read write command in advance of extension, retransmit conventional activated row instruction (Active, ACT) instruction and reading instruction or write command.Expansion equipment executes access and prepares operation, provide response further according to normal read write command according to the read/write command in advance received.It is written and read access every time in this way, requires Memory Controller Hub and issue read write command in advance in advance to cause bandwidth occupancy larger, CPU power consumption is higher followed by normal read write command.

Summary of the invention

The embodiment of the present application provides the method and storage equipment of a kind of access storage equipment, can reduce bandwidth occupancy.

In a first aspect, providing a kind of method of access storage equipment.This is deposited this method comprises: receiving The first row instruction that equipment carries out the first access operation is stored up, the first row instruction carries the first access address, which includes the first row address and the first read-write instruction information；According to the first read-write instruction information, determine that first access operation is read operation or write operation；According to the first determining access operation, the preparation operation of the first access operation of the determination is carried out, preparation operation completes the read operation or the preparation process of the write operation for the storage equipment in preset time threshold；It receives the column for carrying out first access operation to the storage equipment to instruct, column instruction carries column address；According to first row address and the column address, first row address address space corresponding with the column address in the storage equipment is accessed.

It stores equipment and receives the row instruction for carrying the first read-write instruction information and row address, determine that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and access the corresponding address space of row address and column address, so that the storage equipment identifies that access operation is read operation or write operation in advance, extend the response time that storage equipment is written and read, and then it can be communicated with CPU.That is, CPU, which is avoided, individually sends read write command before sending row instruction, it will be able to which the communication of realization and storage equipment reduces bandwidth occupancy.

With reference to first aspect, in some possible implementations, this is according to the first determining access operation, the operation for preparing for carrying out the access operation of the determination includes: the first access operation according to the determination, the data-interface transmission direction of the storage equipment is configured, which includes input direction and outbound course.

The first read-write instruction information that equipment is carried according to row instruction is stored, can identify that the access operation carried out to storage equipment is read operation or write operation, thus allows for the preparation operation of access operation in advance.Preparation operation can be the transmission direction of the data transceiver interface and configuration data transceiver interface of opening storage equipment.In this way, the storage equipment can identify in advance the read-write operation carried out to storage equipment receiving when row instruction, it is equivalent to and extends the response time that storage equipment is written and read, and then can be communicated with CPU.

With reference to first aspect, in some possible implementations, which includes at least one field；Wherein, this determines that first access operation is read operation or write operation includes: the value according at least one field, determines that first access operation is read operation or write operation according to the first read-write instruction information.

Read-write instruction information can be at least one field, and storage equipment can be pre-configured with the value of at least one field and the mapping relations of read-write operation, in this way storage equipment taking according at least one field Value can determine that the access operation carried out to storage equipment is read operation or write operation, storage equipment can be ready work in advance for determining access operation, it is equivalent to the response time for extending and accessing the storage equipment, so that the storage equipment can be with CPU normal communication.

With reference to first aspect, in some possible implementations, this method further include: receive the second row that the second access operation is carried out to the storage equipment and instruct, second row instruction carries the second access address, which includes the second row address and the second read-write instruction information；According to the second read-write instruction information, determine that second access operation is read operation or write operation；It is whether identical as the first access operation of the determination according to the second determining access operation, it is determined whether to modify the data-interface transmission direction of the storage equipment；If identical as the first access operation of the determination according to the second access operation of the determination, the data-interface transmission direction for not modifying the storage equipment is determined.

If store the access operation that equipment is determined according to the second read-write instruction information and the not identical access operation determined according to the first read-write instruction information, at this moment need to be adjusted the transmission direction of data-interface；If storage equipment is identical as the access operation for indicating that information determines according to the first read-write according to the access operation that the second read-write instruction information determines, the transmission direction of modification data-interface is not needed then, storage equipment in this way can be further reduced operating procedure, reduce power consumption.

Second aspect, this application provides a kind of storage equipment, which includes the module for executing the method in any possible implementation of first aspect or first aspect.

The third aspect, this application provides a kind of storage equipment, which includes command decoder and execution module, command address interface module, clock domain conversion circuit module, data interface module and data memory module；The command address interface module is instructed for receiving the first row for carrying out the first access operation to the storage equipment, and is received the column for carrying out first access operation to the storage equipment and instructed；The clock domain conversion circuit module, for converting the clock domain of the command address interface module received the first row instruction and column instruction；The command decoder and execution module, for to being instructed by the first row behind the clock domain conversion circuit module change over clock domain and column instruction decodes, identify that the first row instruction carries the first access address and column instruction carries column address, wherein, first access address includes the first row address and the first read-write instruction information, and determine that first access operation is read operation or write operation according to the first read-write instruction information, and it is operated according to the preparation that determining first access operation carries out the first access operation of the determination, preparation operation completes the read operation or the preparation process of the write operation for the storage equipment in preset time threshold；The data interface module, for receiving or sending data；The data memory module, first row address and the column address for being identified according to the command decoder and execution module, correspondingly with the column address to first row address by the received data storage of the data interface module Location space, or the data in first row address address space corresponding with the column address are sent by the data interface module.

In conjunction with the third aspect, in some possible implementations, the command decoder and execution module are specifically used for: according to the first access operation of the determination, configuring the transmission direction of the data interface module, the transmission direction of the data interface module includes input direction and outbound course.

In conjunction with the third aspect, in some possible implementations, which includes at least one field；The command decoder and execution module are specifically used for: according to the value of at least one field, determining that first access operation is the read operation or the write operation.

In conjunction with the third aspect, in some possible implementations, which is also used to receive the second row instruction that the second access operation is carried out to the storage equipment；The clock domain conversion circuit module is also used to convert the clock domain of received second row instruction of the command address interface module；The command decoder and execution module, it is also used to decode to by the second row instruction behind the clock domain conversion circuit module change over clock domain, identify that second row instruction carries the second access address, wherein, second access address includes the second row address and the second read-write instruction information, and determine that second access operation is the read operation or the write operation according to the second read-write instruction information, and it is whether identical as the first access operation of the determination according to the second determining access operation, determine whether to modify the transmission direction of the data interface module, in the second access operation of the determination and identical the first access operation of the determination, for determining the transmission direction for not modifying the data interface module.

Fourth aspect provides a kind of system of access storage equipment, which includes: the storage equipment of CPU, communication interface and above-mentioned second aspect or the above-mentioned third aspect.CPU is connect with storage equipment and communication interface.Store equipment for storing instruction, CPU is for executing the instruction, and communication interface with other network elements for being communicated under the control of cpu.When the CPU executes the instruction of storage equipment storage, the execution is so that the CPU executes the method in any possible implementation of first aspect or first aspect.

5th aspect, provide a kind of computer storage medium, it is stored with program code in the computer storage medium, which is used to indicate the instruction of the method for the access storage equipment in any possible implementation for executing above-mentioned first aspect or first aspect.

Based on the above-mentioned technical proposal, it stores equipment and receives the row instruction for carrying the first read-write instruction information and row address, determine that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and accesses row address and column ground The corresponding address space in location, so that the storage equipment identifies that access operation is read operation or write operation in advance, extend the response time that storage equipment is written and read, and then it can be communicated with CPU, and avoid CPU and individually send read write command before sending row instruction, reduce bandwidth occupancy.

Detailed description of the invention

The drawings to be used in the description of the embodiments or prior art will be briefly described below.

Fig. 1 is the structural schematic diagram that the application stores equipment；

Fig. 2 is the schematic diagram of the method for the reading instruction access storage equipment of the prior art；

Fig. 3 a and Fig. 3 b are the schematic diagram of the method for the reading and writing instruction access storage equipment of the prior art respectively；

Fig. 4 is the schematic diagram of the method for the access storage equipment of the embodiment of the present application；

Fig. 5 a and Fig. 5 b are the schematic diagrames for the address space that the application stores equipment；

Fig. 6 is the schematic flow chart of the method for the access storage equipment of the embodiment of the present application；

Fig. 7 is the schematic block diagram of the storage equipment of the embodiment of the present application；

Fig. 8 is the schematic block diagram of the system of the embodiment of the present application；

Fig. 9 is the structural schematic diagram of the storage equipment of the embodiment of the present application.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present application, the technical scheme in the embodiment of the application is clearly and completely described.

In order to facilitate the embodiment of the present application is understood, following element is introduced before introducing the embodiment of the present application first.

Field programmable gate array (FPGA) has both high energy efficiency and the aspect of high flexibility two, the efficiency about between 10~100 times of general processor.In addition, FPGA is very suitable to do fine-grained acceleration.

Memory/NVM expansion technique is to can satisfy big data by memory expansion to handle the demand for calculating memory, improves calculated performance, reduces the processing delay of task；It is either extended by NVM, the capacity and access performance of data storage can be improved, meet mass memory demand.Since ddr interface has the characteristics that high bandwidth, low latency, and the design of its operating mode is exactly to access memory, is exented memory and the first choice of NVM.Wherein, NVM is the various new memory techniques occurred based on new semiconductor material, has the characteristic that data are not lost after stopping power supply.

Serial sensing existing for mould group (Serial Presence Detect, SPD), is by chip chamber IC bus (Inter-Integrated Circuit, IIC) electrically erasable read-only memory (the Electrically Erasable Programmable Read-Only Memory of serial line interface connection, EEPROM) to information check device existing for the mould group in memory bank, store the configuration information of memory modules, for assisting Memory Controller Hub end accurately to adjust physics/time sequence parameter of memory, to reach best use effect.

In the embodiment of the present application, the preparation operation of access operation refers to the preparation operation being able to carry out according to the memory space of row address and access instruction access storage equipment, all preparations operation that can be storage equipment can carry out in advance either partially needs time longer preparation operation etc., as long as the preparation operation of read-write operation is completed after enabling to storage equipment to receive column instruction in the time as defined in DDR agreement, all within the scope of the application protects, for convenience of description, the application is illustrated for the transmission direction by preparation operation for the configuration data transceiver interface taken a long time.

It should be understood that storage equipment can be storage equipment or other intimate storage equipment based on FPGA in the embodiment of the present application.For convenience, following embodiments are illustrated so that FPGA stores equipment as an example, but the application does not limit this.

Fig. 1 shows the structural schematic diagram of FPGA storage equipment.As shown in Figure 1, storage equipment 100 based on FPGA mainly has data interface module 101, clock domain conversion circuit module 102, command decoder (Dec) and a few part compositions such as execution module 103 and data memory module 104, command address interface module 105.

Wherein, data interface circuit module 101 further includes receiving portion and transmitting portion.The receiving portion of data interface circuit part 101 is mainly to sample to receive from high-speed serial signals such as data on high speed bus interface, and carry out serioparallel exchange, is converted into the relatively low parallel signal of speed；The transmitting portion of data interface circuit part 101 mainly from FPGA internal receipt data, carries out parallel-serial conversion, modulation etc., is subsequently sent on high speed bus interface.

The receiving portion of command address interface module 105 is mainly to sample the high-speed serial signals such as the address received from high speed bus interface and order, and carry out serioparallel exchange, is converted into the relatively low parallel signal of speed.

Because order or address are unidirectional FPGA internal flows past outside FPGA, so command address interface module 105 only has receiving portion, and data interface circuit module 101 is because data will be sended and received, it is two-way interface, it is also necessary to which directive control circuit send and receive the conversion in direction.

Clock domain conversion circuit module 102 be signal is converted to FPGA intra clock domain from interface circuit clock domain, or signal is transformed into interface circuit clock domain from FPGA intra clock domain because In hardware circuit, signal has to match with the clock signal of the part, otherwise will appear the generation of signal sampling mistake.

Command decoder and execution module 103, on command line order and address decode, to translate the command sequence of correct DDR, and corresponding order is executed according to internal state.

Storage section 104 inside storage equipment is used to store the data of read-write.

Command sequences in DDR access bus have the command sequences such as ACT, column instruction (Column Address Select, CAS).It specifically, is act command first, the row being used to open in some Rank/Bank Group/Bank order；Followed by CAS command, for selecting the column address in row, bi-directional data control pin (Bi-directional Data Strobe, the DQS)/BDB Bi-directional Data Bus (Bi-directional data bus, DQ) being finally only on data/address bus；After having accessed the row, the row is closed with PreCharge order；It must satisfy timing requirements as defined in DDR standard criterion between each order in DDR bus.

The definition of several temporal informations in DDR standard:

Row instruction is to column command time delay (time RAS-to-CAS Delay, tRCD): from act command to the time received column instruction；

CAS adds incubation period (Posted CAS Additive Latency, AL)；

Column address read command incubation period (Column Address Select Latency, CL): it is issued to this period that the first stroke data export from the internal CAS instruction for carrying read command, CL is only used at the time of reading；

Column address write order incubation period (CAS Write Latency, CWL): being CWL from the internal CAS instruction for carrying write order to the timing definition first visible data input.This is the newly-increased time sequence parameter of DDR3, is only used in write operation；

Read command incubation period (time of Read Latency, RL): when read command, the delay of first DQ on CAS command to data/address bus, general RL=AL+CL；

Write order incubation period (time of Write Latency, WL): when write order, the delay of first DQ on CAS command to data/address bus, general WL=AL+CWL.

Most of CPU does not support the case where AL is not equal to 0 at present.It in above-mentioned calculating, is illustrated by taking AL=0 as an example, but the application is not limited to this.

DDR is a kind of data transmission technology, relatively single the transmission rate of data to be made to double along sampling in rising edge failing edge all once data transmission of channel associated clock signal, at present extensively should be in memory field.Since DDR bus is designed to directly access DRAM memory grain originally, ten are only needed Read and write access can be completed in a few to tens of nanoseconds, and time delay is very short.Therefore, the effective range of key delay parameter CL/RL, CWL/WL specified in DDR agreement are all smaller.For example, the CL effective range in DDR4 agreement is 9~24 clock cycle (as shown in table 1 below), maximum value corresponds to 30ns.

Table 1

A6	A5	A4	A2	CAS Latency
0	0	0	0	9
0	0	0	1	10
0	0	1	0	11
0	0	1	1	12
0	1	0	0	13
0	1	0	1	14
0	1	1	0	15
0	1	1	1	16
1	0	0	0	18
1	0	0	1	20
1	0	1	0	22
1	0	1	1	24
1	1	0	0	Reserved
1	1	0	1	Reserved
1	1	1	0	Reserved
1	1	1	1	Reserved

Since the Memory Controller Hub in CPU is Protocol Design and realization based on JEDEC, the read-write delay that can be arranged is equally shorter.Therefore, being directly interconnected in memory side will appear accessing time sequence with the extension of memory/NVM access and is unsatisfactory for protocol requirement, cause expanding storage apparatus can not be with CPU normal communication.Such as, as shown in Figure 2, when CPU issues ACT instruction first, after issuing a read command (reading (READ) instruction in figure) again, the reaction time of expanding storage apparatus only has t=tCL, if DDR memory device cannot provide response (for example, output data (Dout)) before the deadline, it will result in CPU and collect the data of mistake, and then can not be communicated with expanding storage apparatus.

The prior art proposes to expand read/write in advance using the command field retained in DDR bus protocol It orders PR1/PW1, PR2/PW2 (as shown in table 2), when needing to initiate access request to expanding storage apparatus, Memory Controller Hub first provides the read/write command in advance of extension, then provides conventional ACT instruction and reading instruction or write command.Expanding storage apparatus executes read and write access, provides response further according to normal DDR read write command according to the read/write command in advance received.

Table 2

Therefore, as shown in Figure 3a and Figure 3b shows, in the prior art, when being written and read access every time, require the instruction that Memory Controller Hub issues PR1/PW1, PR2/PW2 in advance, followed by normal ACT instruction, reading instruction (RD) or write command (WR), the operation of extra PR1/PW1, PR2/PW2 instruction needs to occupy biggish DDR access bandwidth.

Fig. 4 shows the schematic diagram of the method 200 of the access storage equipment according to the application one embodiment, and this method 200 can be executed by storage equipment.This method 200 includes:

S210 receives the first row for carrying out the first access operation to the storage equipment and instructs, and the first row instruction carries the first access address, which includes the first row address and the first read-write instruction information；

S220 determines that first access operation is read operation or write operation according to the first read-write instruction information；

S230 carries out the preparation operation of the first access operation of the determination according to the first determining access operation, and preparation operation completes the read operation or the preparation process of the write operation for the storage equipment in preset time threshold；

S240 receives the column for carrying out first access operation to the storage equipment and instructs, and column instruction carries column address；

S250 accesses first row address address space corresponding with the column address in the storage equipment according to first row address and the column address.

Specifically, storage equipment receives ACT instruction, ACT is instructed for activating certain data line in DDR.ACT instruction carries the first access address, first access address includes the first row address and the first read-write instruction information, storage equipment determines that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and accesses the corresponding address space of row address and column address.

When storage equipment determines that access operation to storage equipment progress is read operation (i.e. access instruction is reading instruction) according to the first read-write instruction information, carry out sending data into required preparation operation；When storage equipment determines that access operation to storage equipment progress is write operation (i.e. access instruction is write command) according to the first read-write instruction information, preparation needed for the memory space that the data storage will receive is arrived is operated.In this way, the storage equipment can identify in advance to carry out read operation or write operation to the access operation that storage equipment carries out.In other words, storage equipment can know that access instruction is reading instruction or write command according to the first read-write instruction information in advance, the time that equipment is able to extend the response of access operation is stored in this way, meet read operation or write operation that DDR protocol requirement completes data before the deadline, so that the storage equipment can be with CPU normal communication.

As shown in Figure 2, in the prior art, after CPU issues read command (read-write that i.e. CAS instruction carries indicates information), storing reaction time of equipment only has t=tCL from receiving CAS instruction timing, as shown in Table 1, the period of CL≤20, but the general delay of the storage equipment of extension is all bigger, for example, FPGA device is under the rate of 1600MT/s, RL needs 28-30 cycle, is unable to satisfy the time delay of the DDR agreement of standard.At different rates, RL time delay is different, as shown in table 3 specific corresponding to relationship for FPGA device.

Table 3

DDR4 rate (MT/s)	RL length of delay (period)
1333	26~28
1600	28~30
1866	32
2133	38

The embodiment of the present invention is illustrated so that the rate of FPGA storage equipment is 1600MT/s as an example, CPU by ACT instruct in carry first read-write instruction information know in advance access operation be read operation (or write operation) when, storage device access operation reaction time can be extended to ACT instruction and CAS refers to Time and CAS instruction between order appear in bus the sum of the time of (or data are stored into address space), i.e. t=tRCD+tCL (tCWL) to data.

Table 4

For example, the rate of the DDR4 of Double Data Rate is 1600MT/s when the RCD=10 period as shown in table 4, actual speed rate 1600/2=800MT/s, i.e. period are 1/800=1.25ns, that is to say, that tCL=10*1.25=12.5ns.The minimum value of RCD is 12.5ns (i.e. 10 periods), without maximum value.So the period of RL=RCD+CL > 30 enables CPU to store equipment with FPGA and is communicated so as to meet the requirement in 28-30 period.

It should be understood that " order " and " instruction " without distinguishing, that is, the meaning described is consistent in the embodiment of the present application." access instruction " and " access address " in the embodiment of the present application is " access instruction " and " memory access address " usually described, and the embodiment of the present application is to this also without distinguishing.

Therefore, the method of the access storage equipment of the embodiment of the present application, the row instruction of the first read-write instruction information and row address is carried by receiving, determine that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and access the corresponding address space of row address and column address, so that the storage equipment identifies that access operation is read operation or write operation in advance, extend the response time that storage equipment is written and read, and then it can be communicated with CPU.In addition, the embodiment of the present application, which avoids CPU, individually sends read write command before sending row instruction, reduce bandwidth occupancy.

Optionally, which includes at least one field；Wherein, this determines that first access operation is read operation or write operation includes: the value according at least one field, determines that first access operation is read operation or write operation according to the first read-write instruction information.

The first read-write instruction information can be at least one field, and storage equipment can determine that the access operation carried out to the storage equipment is read operation or write operation according at least one field.At least one field can be the high order field of access address, and storage equipment can be reading instruction or write command by the different determinations of the high-word segment value extended in access address, for example, if access address is removed comprising row address also Including a field, the value of the field is that 0 expression access instruction is write command；The value of the field is that 1 expression access instruction is reading instruction.

It should be understood that when at least one field is multiple fields, storage equipment can configure in advance the value of multiple field respectively with the mapping relations of access instruction.

It should also be understood that read-write instruction information can also be that other can be used in distinguishing the instruction information that access instruction is reading instruction or write command, the application is to this without limiting.

Optionally, storage equipment can also be read operation or write operation to the access operation of the storage equipment according to whether the value of the first read-write instruction information belongs to the address space determination of the storage equipment.For example, the byte space (i.e. the memory space of necessary being) reserved in serial sensing existing for mould group (Serial Presence Detect, SPD) information is determined as write address space by storage equipment.When first read-write instruction information is at least one field, whether storage equipment belongs to the address range in write address space according to the value of at least one field, determines that access operation is read operation or write operation.If the value of at least one field belongs to the address range in write address space, it is determined that the access instruction is write command；If the value of at least one field is not belonging to write address space, it is determined that the access instruction is reading instruction.

It should be understood that the byte space reserved in SPD information can also be determined as read address space by storage equipment, storage equipment determines that access operation is read operation or write operation according to whether the value of at least one field belongs to read address space.If access address belongs to read address space, determines that access operation is read operation, be otherwise write operation.

It should be noted that whether belonging to the address space of the storage equipment with the value that low order address (i.e. row address) is maximum value calculation at least one field when at least one field is address high.

Optionally, when the first read-write instruction information is indicated by least one field, storage equipment can also determine a virtual address space according to the value of at least one field, and storage equipment further includes that reserved byte space (i.e. the memory space of necessary being) is stored in SPD information.In this way, storage equipment includes two address spaces, read address space and write address space can be regarded as respectively.

It should be noted that at least one field can be with address high, with low order address (i.e. row address) for maximum value, according to the determining practical space for being Virtual space, being not the storage equipment is truly present of address space of at least one field.

It is then considered as write order (write operation is carried out to storage equipment) when storage equipment determines that the access address belongs to write address space according to the value of at least one field.As shown in Figure 5 a, the actual memory space of FPGA is 0x00000000~0x0000FFFF.By the mapping to memory space, when so that CPU starting, it is seen that memory space it is as shown in Figure 5 b, write address space is 0x00000000~0x0000FFFF, read address space are 0x00010000~0x0001FFFF.

Specifically, 2 Rank/Bank Group/Bank address spaces can be set in FPGA storage equipment, read address space is the address Rank0/Bank Group0/Bank0, and write address space is the address Rank1/Bank Group1/Bank1.When basic input/output (Basic Input/Output System, the BIOS) starting of CPU, this two sector addresses space reflection to specific address space section.Assuming that the address space size inside FPGA storage equipment is 0x10000, reading instruction or write command are distinguished by the difference of address values range.For example, read address space is 0x00100000~0x0010ffff, write address space is 0x00110000~0x0011ffff.Optionally, the difference in both read address space and write address space can be only that a high position for address.

Again for example, assuming that true address space (i.e. write address space) is 0~10, the corresponding address space of read address (i.e. virtual address space) is 10~20, when row address is 5 in the memory access address that ACT instruction carries, the value of at least one field is 10, i.e., access address is 15, and address therein, which is greater than 10, indicates that the memory access order is read command, and real read address or 15-10=5, it integrates and exactly reads data from the address space that address is 5；If row address is 5, the value of at least one field is 0, then it represents that is write order, stores data into the address space that address is 5.

After command interface circuit inside FPGA receives the command/address serial data of high speed from command address bus, it is first converted into the parallel signal of low speed, after clock domain conversion circuit, into command decoder circuit, translates the order of DDR；Execution unit judges whether it is act command, if act command, then the first read-write instruction information carried according to act command, judgement is read command or write order.In this way, storage equipment can determine that access instruction is reading instruction or write command according to the first read-write instruction information in advance.The column instruction for carrying column address is received again, and access the corresponding address space of row address and column address, so that storage equipment is able to extend from identifying that access instruction to the time for providing response, that is, meets DDR protocol requirement, so that the storage equipment can be with CPU normal communication.

Optionally, in the application one embodiment, this is according to the first determining access operation, the operation for preparing for carrying out the access operation of the determination includes: the first access operation according to the determination, the data-interface transmission direction of the storage equipment is configured, which includes input direction and outbound course.

Specifically, the first read-write instruction information that storage equipment is carried according to ACT instruction, can determine the access operation carried out to the storage equipment, and carry out the preparation operation of the access operation in advance.Preparation operation can be opening data transceiver interface, and the data transfer direction etc. of adjustment data transceiver interface.Specifically, if storage equipment determines that the access operation of the storage equipment be read operation according to the first read-write instruction information, storing equipment adjustment data transceiver interface is transmission state.If store equipment according to The first read-write instruction information determines that the access operation of the storage equipment be write operation, then storing equipment adjustment data transceiver interface is reception state.

Optionally, in the application one embodiment, this method further include: receive the second row that the second access operation is carried out to the storage equipment and instruct, second row instruction carries the second access address, which includes the second row address and the second read-write instruction information；According to the second read-write instruction information, determine that second access operation is read operation or write operation；Whether the second access operation determined according to the second read-write instruction information and the first access operation that the first read-write instruction information determines are identical, it is determined whether modify the data-interface transmission direction of the storage equipment；If the second access operation determined according to the second read-write instruction information is identical as the first access operation that the first read-write instruction information determines, the data-interface transmission direction for not modifying the storage equipment is determined.

Specifically, after storage equipment completes an access operation (being expressed as the first access operation), will record that the first access operation finally executes is read operation or write operation.Storage equipment receive it is next to the storage equipment access operation (being expressed as the second access operation) the second row instruction, second row instruction is similar with the first row instruction to carry the second access address, and second access address includes the second row address and the second read-write instruction information, storage equipment determines that second access operation is read operation also write operation according to the second read-write instruction information.At this point, whether the second access operation that storage equipment can be determined according to the second read-write instruction information is identical as the first access operation of storage, it is determined whether need to modify the transmission direction of storage device data interface.

If storage equipment is identical as the access operation for indicating that information determines according to the first read-write according to the access operation that the second read-write instruction information determines, the transmission direction of modification data-interface is not needed；If at this time just needing to be adjusted the transmission direction of data-interface when the access operation that the second read-write instruction information determines and the not identical access operation that the first read-write instruction information determines.In this way, storage equipment can be further reduced operating procedure, reduce power consumption when if the access operation that the second read-write instruction information determines is identical as the access operation that the first read-write instruction information determines.

Optionally, in the application one embodiment, after storage equipment receives the ACT instruction for carrying row address and the first read-write instruction information, CAS instruction (i.e. column instruction) can also be received, and the CAS instruction can also carry read-write instruction information (being expressed as third read-write instruction information), third read-write instruction information is for determining that the access operation carried out to storage equipment is read operation or write operation.Therefore, whether storage equipment, can identical according to the access instruction that the first read-write instruction information determines and the access instruction determined according to the second read-write instruction information, it is determined whether be able to access that the address space of storage equipment after receiving CAS instruction.If the access operation and third read-write instruction information that are determined according to the first read-write instruction information Determining access operation is identical, then the corresponding memory space of column address that the row address and CAS that storage device access ACT is carried carry.The embodiment of the present application storage equipment can identify read write command in advance, and pre-cooling read and write access operation improves bus transfer efficiency and CPU treatment effeciency.

Optionally, in the application one embodiment, if storing the access operation that equipment is determined according to the first read-write instruction information that ACT instruction carries, when the access operation determined with the second read-write instruction information carried according to subsequent CAS instruction is inconsistent, then store the information that equipment provides this DDR access exception, CPU is notified by error correcting code (Error Correction Code, ECC) or Alert_n pin information.

CPU judges whether the memory space of access meets the characteristic of access when receiving the error indication of ECC error or Alert_n, continues to access after being modified.

Fig. 6 shows the interaction diagrams of the method for the access storage equipment according to the application one embodiment.The meaning of various terms in the embodiment of the present application is identical as foregoing embodiments.

It should be noted that this is intended merely to that those skilled in the art is helped to more fully understand the embodiment of the present application, rather than limit the range of the embodiment of the present application.

310, CPU carry the first access address in the first ACT instruction, which includes the first row address and the first read-write instruction information.

320, CPU send the first ACT instruction to storage equipment.

330, storage equipment is according to the first read-write instruction information, the transmission direction of configuration data transceiver interface.

It stores equipment and information is indicated according to the first read-write, determine that the first access operation is read operation or write operation, and configure according to the first determining access operation the transmission direction of corresponding data transceiver interface.If the first access operation is read operation, storing equipment adjustment data transceiver interface is transmission state.If the first access operation is write operation, storing equipment adjustment data transceiver interface is reception state.

340, CPU send the first CAS instruction to storage equipment, which carries the first column address.

After storage equipment receives the first ACT instruction for carrying the first read-write instruction information, the first CAS instruction can be also received, and first CAS instruction carries column address.

350, storage equipment accesses the first row address and the corresponding address space of the first column address according to the first row address and the first column address.

360, CPU carry the second access address in the 2nd ACT instruction, which includes the second row address and the second read-write instruction information.

370, CPU send the 2nd ACT instruction to storage equipment.

380, whether the access operation that storage equipment is determined according to the first read-write instruction information and the access operation that the second read-write instruction information determines are identical, it is determined whether modify the transmission direction of data-interface.

If it is different, then needing to configure the transmission direction of suitable data-interface, if they are the same, then the transmission direction of modification data-interface is not needed, storage equipment can be further reduced operating procedure, reduce power consumption.

390, CPU send the second CAS instruction to storage equipment, which carries the second column address.

400, CPU, according to the second row address and the second column address, access the second row address and the corresponding address space of the second column address.

It should be understood that the specific indicating mode of above-mentioned corresponding information can refer to foregoing embodiments, for sake of simplicity, details are not described herein.

It should be understood that, in the various embodiments of the application, magnitude of the sequence numbers of the above procedures are not meant that the order of the execution order, and the execution sequence of each process should be determined by its function and internal logic, and the implementation process without coping with the embodiment of the present application constitutes any restriction.

The method that the access storage equipment according to the embodiment of the present application has been described in detail above, will retouch below State the storage equipment according to the embodiment of the present application.

Fig. 7 shows the schematic block diagram of the storage equipment 500 according to the embodiment of the present application.As shown in fig. 7, the storage equipment 500 includes:

First receiving module 510, for receiving the first row instruction for carrying out the first access operation to the storage equipment, the first row instruction carries the first access address, which includes the first row address and the first read-write instruction information；

First determining module 520, for determining that first access operation is read operation or write operation according to the first read-write instruction information；

First processing module 530, the first access operation for being determined according to first determining module 520, the preparation operation of the first access operation of the determination is carried out, preparation operation completes the read operation or the preparation process of the write operation for the storage equipment in preset time threshold；

Second receiving module 540, for receiving the column instruction for carrying out first access operation to the storage equipment, column instruction carries column address；

Second processing module 550, for accessing first row address address space corresponding with the column address in the storage equipment according to first row address and the column address.

Therefore, storage equipment provided by the embodiments of the present application, the row instruction of the first read-write instruction information and row address is carried by receiving, determine that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and access the corresponding address space of row address and column address, so that the storage equipment identifies that access operation is read operation or write operation in advance, extend the response time that storage equipment is written and read, and then it can be communicated with CPU.In addition, the embodiment of the present application, which avoids CPU, individually sends read write command before sending row instruction, reduce bandwidth occupancy.

Optionally, in the application one embodiment, which is specifically used for: according to the first access operation of the determination, configuring the data-interface transmission direction of the storage equipment, which includes input direction and outbound course.

Optionally, in the application one embodiment, which includes at least one field；First determining module 520 is specifically used for: according to the value of at least one field, determining that first access operation is read operation or write operation.

Optionally, in the application one embodiment, the storage equipment 500 further include: third receiving module, for receiving the second row instruction for carrying out the second access operation to the storage equipment, second row instruction The second access address is carried, which includes the second row address and the second read-write instruction information；Second determining module, for determining that second access operation is read operation or write operation according to the second read-write instruction information；Third determining module, for whether identical as the first access operation of the determination according to the second determining access operation, it is determined whether modify the interface transmission direction of the storage equipment；Third processing module, if identical as the first access operation of the determination according to the second access operation of the determination, for determining the interface transmission direction for not modifying the storage equipment.

It can correspond to the storage equipment of the method for the access storage equipment according to the embodiment of the present application according to the storage equipment 500 of the embodiment of the present application, and above and other operation and/or functions of the modules in equipment 500 is stored respectively to realize the corresponding process of aforementioned each method, for sake of simplicity, details are not described herein.

Fig. 8 shows the system 700 of the access storage equipment of the application, the system 700 includes: the storage equipment 500 of CPU702, the embodiment of the present application, at least one network interface 705 or other communication interfaces and at least one communication bus 703, for realizing the connection communication between each equipment.The communication connection between at least one other network element is realized by least one network interface (can be wired or wireless).

It should be understood that, in the embodiment of the present application, the processor 702 can also be other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit) either other programmable logic device, discrete gate or transistor logic, discrete hardware components etc..General processor can be microprocessor or the processor is also possible to any read-write and postpones shorter processor etc..

The communication bus 703 is in addition to including data/address bus, it can also include power bus, control bus and status signal bus in addition etc., this 702 and the storage equipment 500 can also be communicated by other kinds of bus, such as, optical fiber or optical waveguide etc., it, will be various total in figure but for the sake of clear explanation Line is all designated as communication bus 703.

The embodiment of the present application also provides a kind of computer storage medium, which can store the program instruction for being used to indicate any of the above-described kind of method.

Optionally, which is specifically as follows storage equipment 500.

As shown in figure 9, the storage equipment 800 is the hardware device for storing the methodological function of equipment for executing above-mentioned access the embodiment of the present application also provides a kind of storage equipment 800.

The storage equipment 800 includes interface module 801, at least one clock domain conversion circuit module 802, command decoder and execution module 803 and data memory module 804.Interface module 101 further includes data interface module and command address interface module, and wherein data interface module further includes receiving portion and transmitting portion.The receiving portion of data interface module is mainly to sample to receive from high-speed serial signals such as data on high speed bus interface, and carry out serioparallel exchange, is converted into the relatively low parallel signal of speed；The transmitting portion of data interface module mainly from FPGA internal receipt data, carries out parallel-serial conversion, modulation etc., is subsequently sent on high speed bus interface.The receiving portion of command address interface module is mainly to sample the high-speed serial signals such as the address received from high speed bus interface and order data, and carry out serioparallel exchange, is converted into the relatively low parallel signal of speed.Clock domain conversion circuit 102 is that signal is converted to FPGA intra clock domain from interface circuit clock domain, or signal is transformed into interface circuit clock domain from FPGA intra clock domain, because in hardware circuit, its signal has to match with the clock signal of the part, otherwise will appear the generation of signal sampling mistake.Command decoder and execution module 803 on command line order and address decode, to translate the command sequence of correct DDR, and corresponding order is executed according to internal state.Data memory module 804 is used to store the data of read-write.

The storage equipment 800 is instructed by the first row that command address interface carries out the first access operation to the storage equipment, and command decoder and execution module 803 are transferred to by clock domain conversion circuit 802, command decoder and execution module 803 translate the first row instruction and carry the first access address, first access address includes the first row address and the first read-write instruction information, and according to the first read-write instruction information, determine that first access operation is read operation or write operation, and according to the first determining access operation, carry out the preparation operation of first access operation, it is instructed by the column that command address interface carries out the first access operation to the storage equipment, and command decoder and execution module 803 are transferred to by clock domain conversion circuit 802, command decoder and execution module 803 are turned over It translates first row instruction and carries column address, data memory module 804 deposits the corresponding address space of the first row address and column address in equipment according to first row address and column address access.For example, storing data into the corresponding address space of the first row address and column address, or the data in the corresponding address space of the first row address and column address are sent out It goes.

Optionally, the transmission direction that operation includes configuration 801 data of interface module is prepared to access operation as one embodiment, command decoder and execution module 803,

Optionally, as one embodiment, which includes at least one field, and command decoder and execution module 803 are also used to the value according at least one field, determine that first access operation is read operation or write operation.

Optionally, as one embodiment, the storage equipment 800 is instructed by the second row that command address interface carries out the second access operation to the storage equipment, second row instruction carries the second access address, and command decoder and execution module 803 are transferred to by clock domain conversion circuit 802, it includes the second row address and the second read-write instruction information that command decoder and execution module 803, which translate second access address, and according to the second read-write instruction information, determine that second access operation is read operation or write operation, and it is whether identical as the first access operation of the determination according to the second determining access operation, determine whether the transmission direction of modification 801 data of interface module, if identical as the first access operation of the determination according to the second access operation of the determination, determine the data for not modifying the storage equipment Interface transmission direction.

It can be seen that from above technical scheme provided by the embodiments of the present application, store the row instruction that equipment carries the first read-write instruction information and row address by receiving, determine that the access operation is read operation or write operation according to the first read-write instruction information, and the preparation for the access operation for according to determining access operation carrying out that the storage equipment is enabled to complete the determination in preset time threshold operates, the column instruction for carrying column address is received again, and access the corresponding address space of row address and column address, so that the storage equipment identifies that access operation is read operation or write operation in advance, extend the response time that storage equipment is written and read, and then it can be communicated with CPU.In addition, the embodiment of the present application, which avoids CPU, individually sends read write command before sending row instruction, reduce bandwidth occupancy.

It should be understood that the specific example in the application is intended merely to that those skilled in the art is helped to more fully understand the embodiment of the present application, rather than limit the range of the embodiment of the present application.

It should be understood that the terms "and/or", only a kind of incidence relation for describing affiliated partner, indicates may exist three kinds of relationships, for example, A and/or B, can indicate: individualism A exists simultaneously A and B, these three situations of individualism B.In addition, character "/" herein, typicallys represent the relationship that forward-backward correlation object is a kind of "or".

Those of ordinary skill in the art may be aware that unit described in conjunction with the examples disclosed in the embodiments of the present disclosure and algorithm steps, can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Professional technician can use different methods to achieve the described function each specific application, but this realization is it is not considered that exceed scope of the present application.

It is apparent to those skilled in the art that for convenience and simplicity of description, system, the specific work process of device and unit of foregoing description can refer to corresponding processes in the foregoing method embodiment, details are not described herein.

In several embodiments provided herein, it should be understood that disclosed systems, devices and methods may be implemented in other ways.Such as, the apparatus embodiments described above are merely exemplary, such as, the division of the unit, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of device or unit, can be electrical property, mechanical or other forms.

The unit as illustrated by the separation member may or may not be physically separated, and component shown as a unit may or may not be physical unit, it can and it is in one place, or may be distributed over multiple network units.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.

In addition, each functional unit in each embodiment of the application can integrate in one processing unit, it is also possible to each unit and physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated unit both can take the form of hardware realization, can also realize in the form of software functional units.

If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product, can store in a computer readable storage medium.Based on this understanding, substantially the part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products the technical solution of the application in other words, the computer software product is stored in a storage medium, it uses including some instructions so that a computer equipment (can be personal computer, server or the network equipment etc.) execute each embodiment the method for the application all or part of the steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or light The various media that can store program code such as disk.

It is described above; the only specific embodiment of the application, but the protection scope of the application is not limited thereto, and anyone skilled in the art is within the technical scope of the present application; it can easily think of the change or the replacement, should all cover within the scope of protection of this application.Therefore, the protection scope of the application should be subject to the scope of protection of the claims.

Claims

A method of access storage equipment characterized by comprising

It receives the first row for carrying out the first access operation to the storage equipment to instruct, the first row instruction carries the first access address, and first access address includes the first row address and the first read-write instruction information；

According to the first read-write instruction information, determine that first access operation is read operation or write operation；

According to the first determining access operation, the preparation operation of the first access operation of the determination, the preparation process for preparing operation and completing the read operation or the write operation in preset time threshold for the storage equipment are carried out；

It receives the column for carrying out first access operation to the storage equipment to instruct, the column instruction carries column address；

According to first row address and the column address, the first row address and the corresponding address space of the column address described in the storage equipment are accessed.
The method according to claim 1, wherein described according to the first determining access operation, the preparation operation for carrying out the access operation of the determination includes:

According to the first access operation of the determination, the data-interface transmission direction of the storage equipment is configured, the data-interface transmission direction includes input direction and outbound course.
Method according to claim 1 or 2, which is characterized in that the first read-write instruction information includes at least one field；

Wherein, described according to the first read-write instruction information, determine that first access operation is read operation or write operation includes:

According to the value of at least one field, determine that first access operation is the read operation or the write operation.
According to the method in any one of claims 1 to 3, which is characterized in that the method also includes:

It receives the second row for carrying out the second access operation to the storage equipment to instruct, the second row instruction carries the second access address, and second access address includes the second row address and the second read-write instruction information；

According to the second read-write instruction information, determine that second access operation is the read operation or the write operation；

It is whether identical as the first access operation of the determination according to the second determining access operation, it is determined whether the data-interface transmission direction of the modification storage equipment；

In the second access operation of the determination and identical the first access operation of the determination, the data-interface transmission direction for not modifying the storage equipment is determined.
A kind of storage equipment characterized by comprising

First receiving module, for receiving the first row instruction for carrying out the first access operation to the storage equipment, the first row instruction carries the first access address, and first access address includes the first row address and the first read-write instruction information；

First determining module, for determining that first access operation is read operation or write operation according to the first read-write instruction information；

First processing module, the first access operation for being determined according to first determining module, carry out the preparation operation of the first access operation of the determination, the preparation process for preparing operation and completing the read operation or the write operation in preset time threshold for the storage equipment；

Second receiving module, for receiving the column instruction for carrying out first access operation to the storage equipment, the column instruction carries column address；

Second processing module, for accessing the first row address and the corresponding address space of the column address described in the storage equipment according to first row address and the column address.
Storage equipment according to claim 5, which is characterized in that the first processing module is specifically used for:

According to the first access operation of the determination, the data-interface transmission direction of the storage equipment is configured, the data-interface transmission direction includes input direction and outbound course.
Storage equipment according to claim 5 or 6, which is characterized in that the first read-write instruction information includes at least one field；

First determining module is specifically used for:

According to the value of at least one field, determine that first access operation is the read operation or the write operation.
Storage equipment according to any one of claims 5 to 7, which is characterized in that the storage equipment further include:

Third receiving module, for receiving the second row instruction for carrying out the second access operation to the storage equipment, the second row instruction carries the second access address, and second access address includes the second row address and the second read-write instruction information；

Second determining module, for determining that second access operation is the read operation or the write operation according to the second read-write instruction information；

Third determining module, for whether identical as the first access operation of the determination according to the second determining access operation, it is determined whether the data-interface transmission direction of the modification storage equipment；

Third processing module, in the second access operation of the determination and identical the first access operation of the determination, for determining the data-interface transmission direction for not modifying the storage equipment.
A kind of storage equipment characterized by comprising command decoder and execution module, command address interface module, clock domain conversion circuit module, data interface module and data memory module；

The command address interface module is instructed for receiving the first row for carrying out the first access operation to the storage equipment, and is received the column for carrying out first access operation to the storage equipment and instructed；

The clock domain conversion circuit module, for converting the clock domain of the command address interface module received the first row instruction and the column instruction；

The command decoder and execution module, for to being instructed by the first row behind the clock domain conversion circuit module change over clock domain and column instruction decodes, identify that the first row instruction carries the first access address and column instruction carries column address, wherein, first access address includes the first row address and the first read-write instruction information, and determine that first access operation is read operation or write operation according to the first read-write instruction information, and it is operated according to the preparation that determining first access operation carries out the first access operation of the determination, the preparation process for preparing operation and completing the read operation or the write operation in preset time threshold for the storage equipment；

The data interface module, for receiving or sending data；

The data memory module, first row address and the column address for being identified according to the command decoder and execution module, the received data storage of the data interface module is sent into the data in first row address and the corresponding address space of the column address to first row address and the corresponding address space of the column address, or by the data interface module.
Storage equipment according to claim 9, which is characterized in that the command decoder and execution module are specifically used for:

According to the first access operation of the determination, the transmission direction of the data interface module is configured, the transmission direction of the data interface module includes input direction and outbound course.
Storage equipment according to claim 9 or 10, which is characterized in that the first read-write instruction information includes at least one field；

The command decoder and execution module are specifically used for:

According to the value of at least one field, determine that first access operation is the read operation or the write operation.
The storage equipment according to any one of claim 9 to 11, which is characterized in that the command address interface module is also used to receive the second row instruction that the second access operation is carried out to the storage equipment；

The clock domain conversion circuit module is also used to convert the clock domain of the received second row instruction of the command address interface module；

The command decoder and execution module, it is also used to decode to by the second row instruction behind the clock domain conversion circuit module change over clock domain, identify that the second row instruction carries the second access address, wherein, second access address includes the second row address and the second read-write instruction information, and determine that second access operation is the read operation or the write operation according to the second read-write instruction information, and it is whether identical as the first access operation of the determination according to the second determining access operation, determine whether to modify the transmission direction of the data interface module, in the second access operation of the determination and identical the first access operation of the determination, for determining the transmission direction for not modifying the data interface module.