CN108139992B

CN108139992B - Method for accessing storage device and storage device

Info

Publication number: CN108139992B
Application number: CN201680057568.4A
Authority: CN
Inventors: 陈云; 宋昆鹏; 仇连根
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-08-09
Filing date: 2016-08-09
Publication date: 2020-06-16
Anticipated expiration: 2036-08-09
Also published as: CN108139992A; WO2018027535A1

Abstract

A method for accessing a storage device and a storage device. The method comprises the following steps: receiving a first row of instructions for performing a second access operation on the storage device, wherein the first row of instructions carries a first access address, and the first access address comprises a first row of addresses and first read-write indication information (S210); determining whether the first access operation is a read operation or a write operation according to the first read-write indication information (S220); performing a preparation operation of the determined first access operation according to the determined first access operation, wherein the preparation operation is used for the storage device to complete a preparation process of the read operation or the write operation within a preset time threshold (S230); receiving a column command for performing the first access operation on the storage device, wherein the column command carries a column address (S240); according to the first row address and the column address, an address space in the memory device corresponding to the first row address and the column address is accessed (S250). The storage device can recognize the access operation in advance, thereby prolonging the access response time.

Description

Method for accessing storage device and storage device

Technical Field

The present application relates to the field of computers, and more particularly, to a method of accessing a storage device and a storage device.

Background

Double Data Rate (DDR) technology has the characteristics of high bandwidth (up to 200Gbit/s) and low delay (tens of nanoseconds), and has the potential of carrying system interconnection. Since the DDR bus is originally designed to directly Access a Dynamic Random Access Memory (DRAM) Memory cell, read-write Access can be completed only by tens of nanoseconds, and the time delay is very short. A memory controller in a Central Processing Unit (CPU) is designed and implemented based on a protocol of Joint Electronic Device Engineering Council (JEDEC), and a read-write delay that can be set is also short. Therefore, in the case of a computer with expansion devices, for example: when a CPU accesses these expansion devices through a DDR bus, an access timing may not meet requirements of a DDR protocol, which may cause the expansion devices to fail to normally communicate with the CPU. For example, when the CPU issues a read command, the expansion device does not reply with correct data within a specified time, causing the CPU to collect incorrect data, thereby causing a system error.

In the prior art, a command field reserved in a DDR bus protocol is used to expand a read-ahead/write command, and when an access request needs to be initiated to an expansion device, a memory controller first sends an expanded read-ahead command and then sends a conventional Active (ACT) instruction and a read instruction or a write instruction. The expansion equipment executes access preparation operation according to the received read/write command in advance and then gives a response according to the normal read/write command. Therefore, each time read-write access is carried out, the memory controller is required to send out a read-write command in advance, and then the read-write command is normal, so that the bandwidth occupation is large, and the CPU power consumption is high.

Disclosure of Invention

The embodiment of the application provides a method for accessing a storage device and the storage device, which can reduce bandwidth occupation.

In a first aspect, a method of accessing a storage device is provided. The method comprises the following steps: receiving a first row of instructions for performing a first access operation on the storage device, wherein the first row of instructions carries a first access address, and the first access address comprises a first row of addresses and first read-write indication information; determining whether the first access operation is a read operation or a write operation according to the first read-write indication information; according to the determined first access operation, carrying out preparation operation of the determined first access operation, wherein the preparation operation is used for completing the preparation process of the read operation or the write operation of the storage device within a preset time threshold; receiving a column instruction for performing the first access operation on the storage device, wherein the column instruction carries a column address; and accessing an address space corresponding to the first row address and the column address in the memory device according to the first row address and the column address.

The storage device receives a row instruction carrying first read-write instruction information and a row address, determines whether the access operation is a read operation or a write operation according to the first read-write instruction information, performs a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receives a column instruction carrying a column address, and accesses an address space corresponding to the row address and the column address, so that the storage device recognizes the access operation as the read operation or the write operation in advance, response time of the storage device in performing the read-write operation is prolonged, and communication with a CPU is further achieved. That is, the CPU avoids sending a read-write command separately before sending a line command, and can realize communication with the storage device, reducing bandwidth occupation.

With reference to the first aspect, in some possible implementations, the performing, according to the determined first access operation, a preparation operation of the determined access operation includes: and configuring a data interface transmission direction of the storage device according to the determined first access operation, wherein the data interface transmission direction comprises an input direction and an output direction.

The storage device can identify whether the access operation performed on the storage device is a read operation or a write operation in advance according to the first read-write indication information carried by the row instruction, so that the preparation operation of the access operation can be performed. The preparing operation may be to open the data transceiving interface of the storage device and to configure a transmission direction of the data transceiving interface. Therefore, the storage device can recognize the read-write operation on the storage device in advance when receiving the line command, which is equivalent to prolonging the response time of the read-write operation on the storage device, and further can communicate with the CPU.

With reference to the first aspect, in some possible implementations, the first read-write instruction information includes at least one field; wherein the determining that the first access operation is a read operation or a write operation according to the first read-write indication information includes: and determining that the first access operation is a read operation or a write operation according to the value of the at least one field.

The read-write indication information may be at least one field, and the storage device may pre-configure a mapping relationship between a value of the at least one field and a read-write operation, so that the storage device may determine whether an access operation performed on the storage device is a read operation or a write operation according to a value of the at least one field, and the storage device may prepare for the determined access operation in advance, which is equivalent to prolonging a response time for accessing the storage device, so that the storage device may communicate with the CPU normally.

With reference to the first aspect, in some possible implementations, the method further includes: receiving a second row instruction for performing a second access operation on the storage device, wherein the second row instruction carries a second access address, and the second access address comprises a second row address and second read-write indication information; determining whether the second access operation is a read operation or a write operation according to the second read-write indication information; determining whether to modify the transmission direction of the data interface of the storage device according to whether the determined second access operation is the same as the determined first access operation; and if the determined second access operation is the same as the determined first access operation, determining not to modify the transmission direction of the data interface of the storage device.

If the access operation determined by the storage device according to the second read-write instruction information is different from the access operation determined according to the first read-write instruction information, the transmission direction of the data interface needs to be adjusted; if the access operation determined by the storage device according to the second read-write instruction information is the same as the access operation determined according to the first read-write instruction information, the transmission direction of the data interface does not need to be modified, so that the storage device can further reduce the operation steps and reduce the power consumption.

In a second aspect, the present application provides a storage device comprising means for performing the method of the first aspect or any possible implementation manner of the first aspect.

In a third aspect, the present application provides a memory device, which includes a command decoding and executing module, a command address interface module, a clock domain converting circuit module, a data interface module, and a data storage module; the command address interface module is used for receiving a first row instruction for performing a first access operation on the storage device and receiving a column instruction for performing the first access operation on the storage device; the clock domain conversion circuit module is used for converting the clock domains of the first row instruction and the column instruction received by the command address interface module; the command decoding and executing module is configured to decode a first row of instructions and a column of instructions after the clock domain conversion by the clock domain conversion circuit module, recognize that the first row of instructions carries a first access address and the column of instructions carries a column address, where the first access address includes the first row of addresses and first read-write instruction information, determine, according to the first read-write instruction information, that the first access operation is a read operation or a write operation, and perform, according to the determined first access operation, a preparation operation of the determined first access operation, where the preparation operation is used for the memory device to complete a preparation process of the read operation or the write operation within a preset time threshold; the data interface module is used for receiving or sending data; the data storage module is used for storing the data received by the data interface module into the address space corresponding to the first row address and the column address according to the first row address and the column address identified by the command decoding and executing module, or sending the data in the address space corresponding to the first row address and the column address through the data interface module.

With reference to the third aspect, in some possible implementations, the command decoding and executing module is specifically configured to: and configuring the transmission direction of the data interface module according to the determined first access operation, wherein the transmission direction of the data interface module comprises an input direction and an output direction.

With reference to the third aspect, in some possible implementations, the first read-write instruction information includes at least one field; the command decoding and executing module is specifically configured to: and determining that the first access operation is the read operation or the write operation according to the value of the at least one field.

With reference to the third aspect, in some possible implementations, the command address interface module is further configured to receive a second row instruction for performing a second access operation on the storage device; the clock domain conversion circuit module is also used for converting the clock domain of the second row of instructions received by the command address interface module; the command decoding and executing module is further configured to decode a second row of instructions after the clock domain is converted by the clock domain converting circuit module, recognize that the second row of instructions carries a second access address, where the second access address includes a second row address and second read/write indication information, determine, according to the second read/write indication information, whether the second access operation is the read operation or the write operation, determine, according to whether the determined second access operation is the same as the determined first access operation, whether to modify the transmission direction of the data interface module, and determine, when the determined second access operation is the same as the determined first access operation, not to modify the transmission direction of the data interface module.

In a fourth aspect, a system for accessing a storage device is provided, the system comprising: a CPU, a communication interface, and the storage device of the second aspect or the third aspect. The CPU is connected with the storage device and the communication interface. The storage device is used for storing instructions, the CPU is used for executing the instructions, and the communication interface is used for communicating with other network elements under the control of the CPU. When the CPU executes the instructions stored by the storage device, the execution causes the CPU to perform the method of the first aspect or any possible implementation manner of the first aspect.

In a fifth aspect, a computer storage medium is provided, in which a program code is stored, where the program code is used to instruct execution of instructions of the method for accessing a storage device in the first aspect or any one of the possible implementation manners of the first aspect.

Based on the technical scheme, the storage device receives a row instruction carrying first read-write instruction information and a row address, determines whether the access operation is a read operation or a write operation according to the first read-write instruction information, performs a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receives a column instruction carrying a column address, and accesses an address space corresponding to the row address and the column address, so that the storage device identifies whether the access operation is the read operation or the write operation in advance, response time of the storage device in performing the read-write operation is prolonged, communication with the CPU is further achieved, the CPU is prevented from independently sending the read-write instruction before sending the row instruction, and bandwidth occupation is reduced.

Drawings

Reference will now be made in brief to the drawings that are needed in describing embodiments or prior art.

FIG. 1 is a schematic diagram of the structure of a memory device of the present application;

FIG. 2 is a schematic diagram of a prior art method of accessing a memory device by a read instruction;

FIGS. 3a and 3b are schematic diagrams of a prior art method of accessing a memory device by read and write instructions, respectively;

FIG. 4 is a schematic diagram of a method of accessing a storage device according to an embodiment of the present application;

FIGS. 5a and 5b are schematic diagrams of the address space of the memory device of the present application;

FIG. 6 is a schematic flow chart diagram of a method of accessing a storage device according to an embodiment of the present application;

FIG. 7 is a schematic block diagram of a storage device of an embodiment of the present application;

FIG. 8 is a schematic block diagram of a system of an embodiment of the present application;

fig. 9 is a schematic structural diagram of a storage device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

To facilitate understanding of the embodiments of the present application, the following elements are first introduced before describing the embodiments of the present application.

The Field Programmable Gate Array (FPGA) has two aspects of high energy efficiency and high flexibility, and the efficiency is about 10-100 times that of a general processor. In addition, FPGAs are well suited for fine-grained acceleration.

The memory/NVM expansion technology can meet the requirement of large data processing on memory calculation through memory expansion, improve the calculation performance and reduce the processing time delay of tasks; or the capacity and the access performance of data storage can be improved through NVM expansion, and the requirement of mass storage is met. Because the DDR interface has the characteristics of high bandwidth and low delay, and the design of the working mode is just for accessing the memory, the DDR interface is the first choice for expanding the memory and the NVM. NVM is a new class of memory technology that appears based on new semiconductor materials, and has the property that data is not lost after power supply is stopped.

The Serial Presence Detect (SPD) of the module is an information check device for checking the Presence of the module in a Memory slot through an electrically erasable Read-Only Memory (EEPROM) connected with an Inter-Integrated Circuit (IIC) Serial interface, which stores configuration information of the Memory module, and is used for assisting a Memory controller end to accurately adjust physical/timing parameters of a Memory so as to achieve the best use effect.

In the embodiment of the present application, the preparation operation of the access operation refers to a preparation operation that can be performed according to a row address and an access instruction to access a storage space of the storage device, and may be all preparation operations that can be performed by the storage device in advance or a part of preparation operations that require a long time.

It should be understood that in the embodiments of the present application, the storage device may be an FPGA-based storage device, or another storage device with similar functions. For convenience of description, the following embodiments take the FPGA storage device as an example for illustration, but the present application does not limit this.

Fig. 1 shows a schematic structural diagram of an FPGA storage device. As shown in fig. 1, the FPGA-based memory device 100 mainly includes a data interface module 101, a clock domain conversion circuit module 102, a command decoding (Dec) and execution module 103, a data storage module 104, and a command address interface module 105.

The data interface circuit module 101 further includes a receiving portion and a transmitting portion. The receiving part of the data interface circuit part 101 is mainly used for sampling and receiving high-speed serial signals such as data on a high-speed bus interface, performing serial-to-parallel conversion and converting the signals into parallel signals with relatively low speed; the transmitting part of the data interface circuit part 101 mainly receives data from the inside of the FPGA, performs parallel-serial conversion, modulation, and the like, and then transmits to the high-speed bus interface.

The receiving part of the command address interface module 105 is mainly to sample and receive high-speed serial signals such as addresses and commands from the high-speed bus interface, and to perform serial-to-parallel conversion and convert the signals into parallel signals with relatively low speed.

Because the command or address flows from the exterior of the FPGA to the interior of the FPGA in a unidirectional manner, the command address interface module 105 has only a receiving part, and the data interface circuit module 101 is a bidirectional interface for receiving and transmitting data, and needs a directional control circuit to convert the transmitting and receiving directions.

The clock domain conversion circuit module 102 is used to convert the signal from the interface circuit clock domain to the FPGA internal clock domain, or vice versa, because in the hardware circuit, the signal must match with the clock signal of the part, otherwise, a signal sampling error occurs.

The command decoding and executing module 103 decodes the command and address on the command bus to translate the correct command sequence of the DDR and executes the corresponding command according to the internal state.

The storage portion 104 inside the storage device is used to store data that is read and written.

The command sequence on the DDR access bus is a command sequence such as ACT, Column instruction (CAS), and the like. Specifically, the ACT command is first used to open a row within a certain Rank/Bank Group/Bank command; then a CAS command is used for selecting the row address in the row, and finally the row address is a Bi-directional Data control pin (DQS)/Bi-directional Data bus (Bi-directional Data bus, DQ) on the Data bus; after the line is visited, closing the line by using a PreCharge command; the timing requirements specified by the DDR standard specification must be met between commands on the DDR bus.

Definition of several time information in DDR standard:

row to column instruction latency (time RAS-to-CAS Delay, tRCD): the time from the ACT command to the receipt of the column command;

CAS Additive Latency (AL);

column Address read command Latency (Column Address Select Latency, CL): CL is only used during reading when the CAS command carrying the read command inside is sent out to the first data output;

column address Write command Latency (CAS Write Latency, CWL): the time from the CAS instruction carrying the write command internally to the first visible data input is defined as the CWL. This is a new timing parameter for DDR3, and is only used during write operations;

read command Latency (time of Read Latency, RL): in a read command, the latency from the CAS command to the first DQ on the data bus, typically RL + CL;

write command Latency (time of Write Latency, WL): in a write command, the CAS command delays the first DQ on the data bus, typically WL ═ AL + CWL.

Most CPUs do not support the case where AL is not equal to 0. In the above calculation, AL is 0 as an example, but the present application is not limited thereto.

DDR is a data transmission technology, data transmission is carried out once on rising edges and falling edges of associated clock signals, the data transmission rate can be doubled compared with single-edge sampling, and the DDR is widely applied to the field of memories at present. Because the DDR bus is originally designed to directly access DRAM memory particles, the read-write access can be completed only by dozens of nanoseconds, and the time delay is very short. Therefore, the effective ranges of the critical delay parameters CL/RL and CWL/WL specified in the DDR protocol are small. For example, the effective CL range in the DDR4 protocol is 9-24 clock cycles (as shown in Table 1 below), and the maximum value corresponds to 30 ns.

TABLE 1

A6	A5	A4	A2	CAS Latency
					0	0	0	0	9
0	0	0	1	10
					0	0	1	0	11
0	0	1	1	12
					0	1	0	0	13
0	1	0	1	14
					0	1	1	0	15
0	1	1	1	16
					1	0	0	0	18
1	0	0	1	20
					1	0	1	0	22
1	0	1	1	24
					1	1	0	0	Reserved
1	1	0	1	Reserved
					1	1	1	0	Reserved
1	1	1	1	Reserved

Because the memory controller in the CPU is designed and realized based on the JEDEC protocol, the read-write delay which can be set is also shorter. Therefore, when the memory side is directly interconnected and the memory/NVM access is extended, the access timing does not meet the protocol requirement, so that the extended storage device cannot normally communicate with the CPU. For example, as shown in fig. 2, when the CPU first issues an ACT instruction and then issues a READ command (READ instruction in the figure), the reaction time of the extended memory device is only t ═ tCL, and if the DDR memory device fails to give a response (e.g., output data (Dout)) within a specified time, the CPU may collect incorrect data and may fail to communicate with the extended memory device.

The prior art proposes to use the reserved command field in the DDR bus protocol to extend the read/write ahead commands PR1/PW1, PR2/PW2 (as shown in table 2), and when an access request needs to be issued to the extended storage device, the memory controller first gives the extended read/write ahead command and then gives the conventional ACT command and read or write command. And the extended storage equipment executes read-write access according to the received read-write command in advance and then gives a response according to the normal DDR read-write command.

TABLE 2

Therefore, as shown in fig. 3a and fig. 3b, in the prior art, each time a read access and a write access are performed, the memory controller is required to issue PR1/PW1, PR2/PW2 ahead of time, and then to issue normal ACT, Read (RD) or Write (WR), and the redundant PR1/PW1, PR2/PW2 instructions are required to occupy a larger DDR access bandwidth.

FIG. 4 illustrates a schematic diagram of a method 200 of accessing a storage device, the method 200 being executable by the storage device, according to one embodiment of the present application. The method 200 comprises:

s210, receiving a first row of instructions for performing a first access operation on the storage device, wherein the first row of instructions carries a first access address, and the first access address comprises a first row of addresses and first read-write indication information;

s220, determining that the first access operation is a read operation or a write operation according to the first read-write indication information;

s230, according to the determined first access operation, performing preparation operation of the determined first access operation, wherein the preparation operation is used for completing the preparation process of the read operation or the write operation of the storage device within a preset time threshold;

s240, receiving a column instruction for performing the first access operation on the storage device, wherein the column instruction carries a column address;

and S250, accessing an address space corresponding to the first row address and the column address in the storage device according to the first row address and the column address.

Specifically, the memory device receives an ACT command, which is used to activate a certain row of data in the DDR. The ACT instruction carries a first access address, the first access address comprises a first row address and first read-write instruction information, the storage device determines whether the access operation is a read operation or a write operation according to the first read-write instruction information, performs a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receives a column instruction carrying a column address, and accesses an address space corresponding to the row address and the column address.

When the storage device determines that the access operation performed on the storage device is a read operation (namely, the access instruction is a read instruction) according to the first read-write indication information, performing a preparation operation required for sending out data; when the storage device determines that the access operation performed on the storage device is a write operation (that is, the access instruction is a write instruction) according to the first read-write instruction information, the storage device performs a preparation operation required for storing the received data in the storage space. In this way, the storage device can recognize in advance whether an access operation to be performed on the storage device is to be read or written. In other words, the memory device can know in advance that the access instruction is a read instruction or a write instruction according to the first read-write indication information, so that the memory device can prolong the response time of the access operation, that is, the DDR protocol requirement is met to complete the read operation or the write operation of data within a specified time, and the memory device can normally communicate with the CPU.

As shown in fig. 2, in the prior art, after a CPU issues a read command (i.e., read-write instruction information carried by a CAS instruction), the response time of a memory device, i.e., only t ═ tCL from the time when the CAS instruction is received, as can be seen from table 1, CL ≦ 20 cycles, but the general latency of the extended memory device is relatively large, for example, at a rate of 1600MT/s, RL requires about 28-30 cycles, and cannot meet the latency of the standard DDR protocol. The specific correspondence relationship between the different RL delays of the FPGA devices at different rates is shown in table 3.

TABLE 3

DDR4 rate (MT/s)	RL delay value (period)
		1333	26～28
1600	28～30
		1866	32
2133	38

In the embodiment of the present invention, the speed of the FPGA storage device is 1600MT/s, for example, when the CPU knows in advance that the access operation is a read operation (or a write operation) through the first read-write instruction information carried in the ACT instruction, the reaction time of the access operation of the storage device can be expanded to a sum of a time between the ACT instruction and the CAS instruction and a time from the CAS instruction to the occurrence of data on the bus (or from the CAS instruction to the address space), that is, t ═ tRCD + tcl (tcwl).

TABLE 4

For example, as shown in table 4, when RCD is 10 cycles, the rate of DDR4 with double data rate is 1600MT/s, the actual rate is 1600/2 MT/s, that is, the cycle is 1/800 ns-1.25 ns, that is, tCL is 10 ns-1.25 ns-12.5 ns. The minimum value of RCD is 12.5ns (i.e., 10 cycles), with no maximum. Therefore, RL is RCD + CL > 30 cycles, thereby being capable of meeting the requirement of 28-30 cycles, and enabling the CPU to communicate with the FPGA storage device.

It should be understood that in the embodiments of the present application, no distinction is made between "command" and "instruction", i.e., the description is intended to be consistent. The "access instruction" and the "access address" in the embodiment of the present application are commonly described as a "memory access instruction" and a "memory access address", which are not distinguished in the embodiment of the present application.

Therefore, according to the method for accessing the storage device in the embodiment of the application, by receiving the row instruction carrying the first read-write instruction information and the row address, determining whether the access operation is a read operation or a write operation according to the first read-write instruction information, performing a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receiving the column instruction carrying the column address, and accessing the address space corresponding to the row address and the column address, the storage device is enabled to recognize whether the access operation is a read operation or a write operation in advance, response time of the storage device for performing the read-write operation is prolonged, and further communication with the CPU is enabled. In addition, the embodiment of the application avoids that the CPU sends the read-write command before sending the line command, and reduces the bandwidth occupation.

Optionally, the first read-write instruction information includes at least one field; wherein the determining that the first access operation is a read operation or a write operation according to the first read-write indication information includes: and determining that the first access operation is a read operation or a write operation according to the value of the at least one field.

The first read-write indication information may be at least one field, and the storage device may determine whether an access operation performed on the storage device is a read operation or a write operation according to the at least one field. The at least one field may be an upper field of an access address, and the storage device may determine whether the access instruction is a read instruction or a write instruction by a difference in an upper field value of an extension of the access address, for example, if the access address includes a field in addition to the row address, a value of 0 in the field indicates that the access instruction is a write instruction; a value of 1 in this field indicates that the access instruction is a read instruction.

It should be understood that when the at least one field is a plurality of fields, the storage device may configure the mapping relationship between the values of the plurality of fields and the access instruction in advance.

It should also be understood that the read/write indication information may also be other indication information that can be used to distinguish the access instruction as a read instruction or a write instruction, which is not limited in this application.

Optionally, the storage device may further determine whether an access operation to the storage device is a read operation or a write operation according to whether the value of the first read-write indication information belongs to the address space of the storage device. For example, the storage device determines a byte space reserved in Serial Presence Detect (SPD) information of the Presence of the module (i.e., a storage space that actually exists) as a write address space. And when the first read-write indication information is at least one field, the storage device determines whether the access operation is a read operation or a write operation according to whether the value of the at least one field belongs to the address range of the write address space. If the value of the at least one field belongs to the address range of the write address space, determining that the access instruction is a write instruction; and if the value of at least one field does not belong to the write address space, determining that the access instruction is a read instruction.

It should be understood that the storage device may also determine the reserved byte space in the SPD information as a read address space, and the storage device determines whether the access operation is a read operation or a write operation according to whether the value of the at least one field belongs to the read address space. And if the access address belongs to the read address space, determining that the access operation is a read operation, and otherwise, determining that the access operation is a write operation.

It should be noted that, when the at least one field is an upper address, it is calculated whether the value of the at least one field belongs to the address space of the memory device by taking a lower address (i.e., a row address) as a maximum value.

Optionally, when the first read-write indication information is represented by at least one field, the storage device may further determine a virtual address space according to a value of the at least one field, and the storage device further includes a byte space (i.e., a storage space that exists actually) reserved in storage of the SPD information. Thus, the memory device comprises two address spaces, which can be considered as a read address space and a write address space, respectively.

It should be noted that the at least one field may be an upper address, and a lower address (i.e. a row address) is a maximum, and the address space determined by the at least one field is actually a virtual space and is not a real space of the storage device.

The storage device determines that the access address belongs to the write address space according to the value of the at least one field, and then the storage device is considered to be a write command (i.e., a write operation is performed on the storage device). As shown in FIG. 5a, the actual storage space of the FPGA is 0x00000000 ~ 0x0000 FFFF. By mapping the memory space, the memory space seen when the CPU is started is as shown in FIG. 5b, the write address space is 0x00000000 to 0x0000FFFF, and the read address space is 0x00010000 to 0x0001 FFFF.

Specifically, 2 Rank/Bank Group/Bank address spaces can be set in the FPGA storage device, the read address space is a Rank0/Bank Group0/Bank0 address, and the write address space is a Rank1/Bank Group1/Bank1 address. When the Basic Input/Output System (BIOS) of the CPU starts, these two address spaces are mapped to a specific address space section. Assuming that the size of an address space inside the FPGA storage device is 0x10000, the read instruction or the write instruction is distinguished through the difference of address value ranges. For example, the read address space is 0x00100000 to 0x0010ffff, and the write address space is 0x00110000 to 0x0011 ffff. Alternatively, both the read address space and the write address space may differ only in the upper bits of the address.

For another example, assuming that a real address space (i.e., a write address space) is 0 to 10, and an address space (i.e., a virtual address space) corresponding to a read address is 10 to 20, when a row address in an access address carried by an ACT instruction is 5, a value of at least one field is 10, that is, the access address is 15, where an address greater than 10 indicates that the access command is a read command, and a real read address is 15-10 ═ 5, and the data is read from the address space with the address of 5 in a comprehensive manner; if the row address is 5 and the value of at least one field is 0, indicated as a write command, the data is stored in the address space with address 5.

After receiving high-speed command/address serial data from a command address bus, a command interface circuit inside the FPGA converts the high-speed command/address serial data into low-speed parallel signals, and the low-speed parallel signals enter a command decoding circuit after passing through a clock domain conversion circuit to be translated into DDR commands; and the execution unit judges whether the command is an ACT command, and if the command is the ACT command, the execution unit judges whether the command is a read command or a write command according to first read-write instruction information carried by the ACT command. Therefore, the storage device can determine whether the access instruction is a read instruction or a write instruction in advance according to the first read-write indication information. And then receiving a column instruction carrying a column address, and accessing an address space corresponding to the row address and the column address, so that the memory device can prolong the time from the identification of the access instruction to the response, namely the memory device meets the requirement of a DDR protocol, and the memory device can normally communicate with a CPU.

Optionally, in an embodiment of the present application, the preparing operation for performing the determined access operation according to the determined first access operation includes: and configuring a data interface transmission direction of the storage device according to the determined first access operation, wherein the data interface transmission direction comprises an input direction and an output direction.

Specifically, the memory device may determine, in advance, an access operation to be performed on the memory device according to the first read-write instruction information carried by the ACT instruction, and perform a preparation operation for the access operation. The preparation operation may be to open the data transceiving interface, to adjust a data transmission direction of the data transceiving interface, and the like. Specifically, if the storage device determines that the access operation to the storage device is a read operation according to the first read-write indication information, the storage device adjusts the data transceiving interface to be in a sending state. And if the storage equipment determines that the access operation to the storage equipment is write operation according to the first read-write indication information, the storage equipment adjusts the data receiving and transmitting interface to be in a receiving state.

Optionally, in an embodiment of the present application, the method further includes: receiving a second row instruction for performing a second access operation on the storage device, wherein the second row instruction carries a second access address, and the second access address comprises a second row address and second read-write indication information; determining whether the second access operation is a read operation or a write operation according to the second read-write indication information; determining whether the transmission direction of the data interface of the storage device is modified or not according to whether a second access operation determined by the second read-write indication information is the same as a first access operation determined by the first read-write indication information or not; and if the second access operation determined according to the second read-write instruction information is the same as the first access operation determined by the first read-write instruction information, determining not to modify the transmission direction of the data interface of the storage device.

Specifically, after the storage device completes one access operation (denoted as a first access operation), it records whether the first access operation is finally performed as a read operation or a write operation. The storage device receives a second row instruction for performing a next access operation (denoted as a second access operation) on the storage device, the second row instruction carries a second access address similar to the first row instruction, the second access address includes a second row address and second read-write indication information, and the storage device determines that the second access operation is a read operation and a write operation according to the second read-write indication information. At this time, the storage device may determine whether the second access operation determined according to the second read/write indication information is the same as the stored first access operation, and whether the transmission direction of the data interface of the storage device needs to be modified.

If the access operation determined by the storage device according to the second read-write instruction information is the same as the access operation determined according to the first read-write instruction information, the transmission direction of the data interface does not need to be modified; if the access operation determined by the second read-write instruction information is different from the access operation determined by the first read-write instruction information, the transmission direction of the data interface needs to be adjusted at this time. Therefore, if the access operation determined by the second read-write instruction information is the same as the access operation determined by the first read-write instruction information, the operation steps of the storage device can be further reduced, and the power consumption is reduced.

Optionally, in an embodiment of the present application, after receiving the ACT instruction carrying the row address and the first read/write indication information, the storage device further receives a CAS instruction (i.e., a column instruction), where the CAS instruction also carries read/write indication information (denoted as third read/write indication information), and the third read/write indication information is used to determine whether an access operation performed on the storage device is a read operation or a write operation. Therefore, after receiving the CAS instruction, the storage device may determine whether the address space of the storage device can be accessed according to whether the access instruction determined by the first read/write indication information is the same as the access instruction determined by the second read/write indication information. And if the access operation determined according to the first read-write instruction information is the same as the access operation determined according to the third read-write instruction information, the storage device accesses a storage space corresponding to the row address carried by the ACT and the column address carried by the CAS. According to the storage device, the read-write instruction can be recognized in advance, the read-write access operation is started in advance, and the bus transmission efficiency and the CPU processing efficiency are improved.

Optionally, in an embodiment of the present application, if the access operation determined by the storage device according to the first read-write instruction information carried by the ACT instruction is inconsistent with the access operation determined according to the second read-write instruction information carried by the subsequent CAS instruction, the storage device gives information of the DDR access exception this time, and notifies the CPU through an Error Correction Code (ECC) or Alert _ n pin information.

When receiving an ECC error or an Alert _ n error indication, the CPU determines whether the accessed storage space meets the accessed characteristics, and then performs the subsequent access after correction.

FIG. 6 shows an interactive flow diagram of a method of accessing a storage device according to one embodiment of the present application. The meanings of various terms in the embodiments of the present application are the same as those of the previous embodiments.

It should be noted that this is only for helping the skilled person to better understand the embodiments of the present application, and does not limit the scope of the embodiments of the present application.

The CPU carries a first access address on the first ACT instruction, where the first access address includes a first row address and first read-write instruction information 310.

The CPU sends 320 a first ACT command to the memory device.

330, the storage device configures the transmission direction of the data transceiving interface according to the first read-write indication information.

And the storage equipment determines whether the first access operation is a read operation or a write operation according to the first read-write indication information, and configures the transmission direction of the corresponding data transceiving interface according to the determined first access operation. And if the first access operation is a read operation, the storage equipment adjusts the data receiving and transmitting interface to be in a transmitting state. And if the first access operation is write operation, the storage equipment adjusts the data transceiving interface to be in a receiving state.

340, the CPU sends a first CAS instruction to the memory device, the CAS instruction carrying a first column address.

After receiving a first ACT instruction carrying first read-write instruction information, the memory device also receives a first CAS instruction, and the first CAS instruction carries a column address.

350, the memory device accesses an address space corresponding to the first row address and the first column address according to the first row address and the first column address.

And 360, the CPU carries a second access address on the second ACT instruction, wherein the second access address comprises a second row address and second read-write indication information.

The CPU sends 370 a second ACT command to the memory device.

380, the storage device determines whether to modify the transmission direction of the data interface according to whether the access operation determined by the first read-write indication information is the same as the access operation determined by the second read-write indication information.

If the data interface is different from the data interface, the transmission direction of the data interface needs to be configured, and if the data interface is the same as the data interface, the transmission direction of the data interface does not need to be modified, so that the operation steps of the storage device can be further reduced, and the power consumption can be reduced.

390, the CPU sends a second CAS instruction to the storage device, the second CAS instruction carrying a second column address.

400, the CPU accesses the address space corresponding to the second row address and the second column address according to the second row address and the second column address.

It should be understood that, for the sake of brevity, detailed description is omitted here for specific indication manners of the corresponding information mentioned above with reference to the foregoing embodiments.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Having described the method of accessing a storage device according to an embodiment of the present application in detail above, a storage device according to an embodiment of the present application will be described below.

FIG. 7 shows a schematic block diagram of a storage device 500 according to an embodiment of the present application. As shown in fig. 7, the storage device 500 includes:

a first receiving module 510, configured to receive a first row of instructions for performing a first access operation on the storage device, where the first row of instructions carries a first access address, and the first access address includes a first row address and first read-write instruction information;

a first determining module 520, configured to determine, according to the first read-write instruction information, that the first access operation is a read operation or a write operation;

a first processing module 530, configured to perform a preparation operation of the determined first access operation according to the first access operation determined by the first determining module 520, where the preparation operation is used for the storage device to complete a preparation process of the read operation or the write operation within a preset time threshold;

a second receiving module 540, configured to receive a column instruction for performing the first access operation on the storage device, where the column instruction carries a column address;

the second processing module 550 is configured to access an address space corresponding to the first row address and the column address in the memory device according to the first row address and the column address.

Therefore, according to the storage device provided by the embodiment of the application, by receiving the row instruction carrying the first read-write instruction information and the row address, determining whether the access operation is a read operation or a write operation according to the first read-write instruction information, performing a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receiving the column instruction carrying the column address, and accessing the address space corresponding to the row address and the column address, the storage device is enabled to recognize whether the access operation is a read operation or a write operation in advance, response time of the storage device for performing the read-write operation is prolonged, and further communication with the CPU is enabled. In addition, the embodiment of the application avoids that the CPU sends the read-write command before sending the line command, and reduces the bandwidth occupation.

Optionally, in an embodiment of the present application, the first processing module 530 is specifically configured to: and configuring a data interface transmission direction of the storage device according to the determined first access operation, wherein the data interface transmission direction comprises an input direction and an output direction.

Optionally, in an embodiment of the present application, the first read-write instruction information includes at least one field; the first determining module 520 is specifically configured to: and determining that the first access operation is a read operation or a write operation according to the value of the at least one field.

Optionally, in an embodiment of the present application, the storage device 500 further includes: a third receiving module, configured to receive a second row instruction for performing a second access operation on the storage device, where the second row instruction carries a second access address, and the second access address includes a second row address and second read-write instruction information; a second determining module, configured to determine, according to the second read/write indication information, that the second access operation is a read operation or a write operation; a third determining module, configured to determine whether to modify an interface transmission direction of the storage device according to whether the determined second access operation is the same as the determined first access operation; and the third processing module is used for determining not to modify the interface transmission direction of the storage device if the determined second access operation is the same as the determined first access operation.

The storage device 500 according to the embodiment of the present application may correspond to a storage device of a method for accessing a storage device according to the embodiment of the present application, and the above and other operations and/or functions of each module in the storage device 500 are respectively to implement corresponding flows of the foregoing methods, and are not described herein again for brevity.

FIG. 8 illustrates a system 700 of the present application for accessing a storage device, the system 700 comprising: the CPU702, the storage device 500 according to the embodiment of the present application, at least one network interface 705 or other communication interfaces, and at least one communication bus 703 are used to implement connection communication between the devices. The communication connection with at least one other network element is realized through at least one network interface (which can be wired or wireless).

It should be appreciated that, in the embodiments of the present Application, the Processor 702 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application specific integrated circuits (Application specific integrated circuits), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general purpose processor may be a microprocessor or the processor may be any processor with a short read and write latency.

The communication bus 703 may include a power bus, a control bus, a status signal bus, etc. in addition to a data bus, and the 702 and the memory device 500 may communicate via other types of buses, such as optical fibers or optical waveguides, but for clarity of illustration, the various buses are labeled as communication bus 703.

Embodiments of the present application also provide a computer storage medium that can store program instructions for instructing any one of the methods described above.

Alternatively, the storage medium may be specifically the storage device 500.

As shown in fig. 9, an embodiment of the present application further provides a storage device 800, where the storage device 800 is a hardware device for executing the functions of the method for accessing a storage device.

The memory device 800 includes an interface module 801, at least one clock domain conversion circuit module 802, a command decode and execution module 803, and a data storage module 804. The interface module 101 further comprises a data interface module and a command address interface module, wherein the data interface module further comprises a receiving part and a transmitting part. The receiving part of the data interface module is mainly used for sampling and receiving high-speed serial signals such as data on a high-speed bus interface, performing serial-parallel conversion and converting the high-speed serial signals into parallel signals with relatively low speed; the sending part of the data interface module mainly receives data from the interior of the FPGA, performs parallel-serial conversion, modulation and the like, and then sends the data to the high-speed bus interface. The receiving part of the command address interface module is mainly used for sampling and receiving high-speed serial signals such as addresses, command data and the like from a high-speed bus interface, performing serial-to-parallel conversion and converting the signals into parallel signals with relatively low speed. The clock domain conversion circuit 102 is used to convert signals from the interface circuit clock domain to the FPGA internal clock domain, or vice versa, because in a hardware circuit, the signals must match the clock signal of the interface circuit, otherwise signal sampling errors occur. The command decoding and executing module 803 decodes the command and address on the command bus to translate the correct command sequence of the DDR and executes the corresponding command according to the internal state. The data storage module 804 is used for storing read and write data.

The memory device 800 receives a first row of instructions for performing a first access operation on the memory device through a command address interface, and transmits the first row of instructions to a command decoding and executing module 803 through a clock domain converting circuit 802, the command decoding and executing module 803 decodes the first row of instructions to carry a first access address, the first access address comprises a first row address and first read-write indicating information, determines whether the first access operation is a read operation or a write operation according to the first read-write indicating information, performs a preparation operation of the first access operation according to the determined first access operation, receives a column instruction for performing the first access operation on the memory device through the command address interface, and transmits the column instruction to the command decoding and executing module 803 through the clock domain converting circuit 802, the command decoding and executing module 803 decodes the column address carried by the first column instruction, and the data storage module 804 accesses the first row address and the column ground in the memory device according to the first row address and the column address Address space corresponding to the address. For example, data is stored in an address space corresponding to the first row address and the column address, or data in an address space corresponding to the first row address and the column address is sent out.

Alternatively, as an embodiment, the command decoding and execution module 803 prepares for the access operation by configuring the transmission direction of the data of the interface module 801,

optionally, as an embodiment, the first read-write indication information includes at least one field, and the command decoding and executing module 803 is further configured to determine that the first access operation is a read operation or a write operation according to a value of the at least one field.

Optionally, as an embodiment, the memory device 800 receives, through the command address interface, a second row of instructions for performing a second access operation on the memory device, where the second row of instructions carries a second access address, and is transmitted to the command decoding and executing module 803 through the clock domain converting circuit 802, and the command decoding and executing module 803 translates that the second access address includes the second row address and second read-write indication information, and determines, according to the second read-write indication information, whether the second access operation is a read operation or a write operation, and determines, according to whether the determined second access operation is the same as the determined first access operation, whether to modify the transmission direction of the data of the interface module 801, and if the determined second access operation is the same as the determined first access operation, determines not to modify the transmission direction of the data interface of the memory device.

As can be seen from the above technical solutions provided in the embodiments of the present application, a storage device determines whether an access operation is a read operation or a write operation according to a row instruction carrying first read-write instruction information and a row address, performs a preparation operation capable of enabling the storage device to complete the determined access operation within a preset time threshold according to the determined access operation, receives a column instruction carrying a column address, and accesses an address space corresponding to the row address and the column address, so that the storage device identifies in advance whether the access operation is the read operation or the write operation, prolongs a response time of the storage device in performing the read-write operation, and further can communicate with a CPU. In addition, the embodiment of the application avoids that the CPU sends the read-write command before sending the line command, and reduces the bandwidth occupation.

It should be understood that the specific examples are provided solely to assist those skilled in the art in better understanding the embodiments of the present application and are not intended to limit the scope of the embodiments of the present application.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the unit is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of accessing a storage device, comprising:

receiving a first row of instructions for performing a first access operation on the storage device, wherein the first row of instructions carries a first access address, and the first access address comprises a first row of addresses and first read-write indication information;

determining that the first access operation is a read operation or a write operation according to the first read-write indication information;

according to the determined first access operation, carrying out preparation operation of the determined first access operation, wherein the preparation operation is used for completing the preparation process of the read operation or the write operation of the storage device within a preset time threshold;

receiving a column instruction for performing the first access operation on the storage device, wherein the column instruction carries a column address;

and accessing an address space corresponding to the first row address and the column address in the storage device according to the first row address and the column address.

2. The method of claim 1, wherein the performing, in accordance with the determined first access operation, a preparation operation for the determined access operation comprises:

and configuring a data interface transmission direction of the storage device according to the determined first access operation, wherein the data interface transmission direction comprises an input direction and an output direction.

3. The method of claim 1, wherein the first read-write indication information comprises at least one field;

wherein the determining that the first access operation is a read operation or a write operation according to the first read-write indication information includes:

and determining that the first access operation is the read operation or the write operation according to the value of the at least one field.

4. The method according to any one of claims 1 to 3, further comprising:

receiving a second row instruction for performing a second access operation on the storage device, wherein the second row instruction carries a second access address, and the second access address comprises a second row address and second read-write indication information;

determining that the second access operation is the read operation or the write operation according to the second read-write indication information;

determining whether to modify the transmission direction of the data interface of the storage device according to whether the determined second access operation is the same as the determined first access operation;

determining not to modify a data interface transfer direction of the storage device when the determined second access operation is the same as the determined first access operation.

5. A storage device, comprising:

a first receiving module, configured to receive a first row of instructions for performing a first access operation on the storage device, where the first row of instructions carries a first access address, and the first access address includes a first row of addresses and first read-write indication information;

a first determining module, configured to determine, according to the first read-write indication information, that the first access operation is a read operation or a write operation;

the first processing module is used for performing preparation operation of the determined first access operation according to the first access operation determined by the first determining module, wherein the preparation operation is used for completing the preparation process of the read operation or the write operation of the storage device within a preset time threshold;

a second receiving module, configured to receive a column instruction for performing the first access operation on the storage device, where the column instruction carries a column address;

and the second processing module is used for accessing the address space corresponding to the first row address and the column address in the storage device according to the first row address and the column address.

6. The storage device of claim 5, wherein the first processing module is specifically configured to:

7. The storage device according to claim 5, wherein the first read-write indication information includes at least one field;

the first determining module is specifically configured to:

8. The storage device according to any one of claims 5 to 7, further comprising:

a third receiving module, configured to receive a second row instruction for performing a second access operation on the storage device, where the second row instruction carries a second access address, and the second access address includes a second row address and second read-write instruction information;

a second determining module, configured to determine, according to the second read/write indication information, that the second access operation is the read operation or the write operation;

a third determining module, configured to determine whether to modify a data interface transmission direction of the storage device according to whether the determined second access operation is the same as the determined first access operation;

and the third processing module is used for determining not to modify the transmission direction of the data interface of the storage device when the determined second access operation is the same as the determined first access operation.

9. A storage device, comprising: the device comprises a command decoding and executing module, a command address interface module, a clock domain conversion circuit module, a data interface module and a data storage module;

the command address interface module is configured to receive a first row instruction for performing a first access operation on the storage device, and receive a column instruction for performing the first access operation on the storage device;

the clock domain conversion circuit module is used for converting the clock domains of the first row instruction and the column instruction received by the command address interface module;

the command decoding and executing module is configured to decode a first row of instructions and a column of instructions after the clock domain conversion by the clock domain conversion circuit module, recognize that the first row of instructions carries a first access address and the column of instructions carries a column address, where the first access address includes the first row of addresses and first read-write instruction information, determine, according to the first read-write instruction information, that the first access operation is a read operation or a write operation, and perform, according to the determined first access operation, a preparation operation of the determined first access operation, where the preparation operation is used for the storage device to complete a preparation process of the read operation or the write operation within a preset time threshold;

the data interface module is used for receiving or sending data;

the data storage module is configured to store the data received by the data interface module into an address space corresponding to the first row address and the column address according to the first row address and the column address identified by the command decoding and executing module, or send the data in the address space corresponding to the first row address and the column address through the data interface module.

10. The storage device of claim 9, wherein the command decode and execution module is specifically configured to:

and configuring the transmission direction of the data interface module according to the determined first access operation, wherein the transmission direction of the data interface module comprises an input direction and an output direction.

11. The storage device according to claim 9, wherein the first read-write indication information includes at least one field;

the command decoding and execution module is specifically configured to:

12. The memory device of any of claims 9 to 11, wherein the command address interface module is further configured to receive a second row instruction for performing a second access operation on the memory device;

the clock domain conversion circuit module is further configured to convert the clock domain of the second row of instructions received by the command address interface module;

the command decoding and executing module is further configured to decode a second row of instructions after the clock domain is converted by the clock domain converting circuit module, recognize that the second row of instructions carries a second access address, determine, according to the second read/write indication information, whether the second access operation is the read operation or the write operation, determine, according to whether the determined second access operation is the same as the determined first access operation, whether to modify the transmission direction of the data interface module, and determine, when the determined second access operation is the same as the determined first access operation, not to modify the transmission direction of the data interface module.