WO2018027535A1 - Method for accessing storage device and storage device - Google Patents

Abstract

A method for accessing a storage device and the storage device. The method comprises: receiving a first row instruction for performing a first access operation with respect to the storage device, the first row instruction carrying a first access address, the first access address comprising a first row address and first read/write indication information (S210); determining, on the basis of the read/write indication information, whether the first access operation is a read operation or a write operation (S220); performing, on the basis of the determined first access operation, a preparatory operation for the determined first access operation, the preparatory operation being used as a preparation process for the storage device to complete the read operation or the write operation by a preset time threshold (S230); receiving a column instruction for performing the first access operation with respect to the storage device, the column instruction carrying a column address (S240); and accessing, on the basis of the row address and of the column address, an address space corresponding to the row address and to the column address in the storage device (S250). The storage device is capable of recognizing in advance an access operation, thus extending access response time.

Description

Method and storage device for accessing storage devices Technical field

The present application relates to the field of computers and, more particularly, to methods and storage devices for accessing storage devices.

Background technique

Double Data Rate (DDR) technology features high bandwidth (up to 200 Gbit/s) and low latency (tens of nanoseconds), with the potential to host system interconnects. Since the DDR bus was originally designed to directly access the dynamic random access memory (DRAM) memory particles, it takes only a few ten to several tens of nanoseconds to complete the read and write access, and the delay is short. The memory controller in the Central Processing Unit (CPU) is designed and implemented based on the protocol of the Joint Electron Device Engineering Council (JEDEC), and the read and write delays can be set to be shorter. Therefore, under the condition that the computer has an extension device, such as a non-volatile memory (NVM) chip or a Field-Programmable Gate Array (FPGA) chip, the CPU accesses these through the DDR bus. When the device is extended, the access timing does not meet the DDR protocol requirements, causing the expansion device to fail to communicate with the CPU. For example, when the CPU issues a read command, the extended device does not reply to the correct data within the specified time, causing the CPU to collect the wrong data, causing a system error.

The prior art proposes to use the command field reserved in the DDR bus protocol to extend the read/write command in advance. When an access request needs to be initiated to the extended device, the memory controller first sends an extended read/write command, and then sends a regular active line. Instruction (Active, ACT) instruction and read or write instruction. The extension device performs an access preparation operation according to the received advance read/write command, and then gives a response according to the normal read/write command. In this way, each time the read and write access is performed, the memory controller needs to issue an advance read/write instruction in advance, and then the normal read/write instruction, resulting in a large bandwidth occupation and high CPU power consumption.

Summary of the invention

The embodiment of the present application provides a method and a storage device for accessing a storage device, which can reduce bandwidth occupation.

In a first aspect, a method of accessing a storage device is provided. The method includes: receiving the deposit And storing, by the storage device, a first row of instructions, where the first row of instructions carries a first access address, where the first access address includes a first row address and first read/write indication information; Determining that the first access operation is a read operation or a write operation; performing a preparation operation of the determined first access operation according to the determined first access operation, the preparing operation for the storage device to complete the preset time threshold a read operation or a preparation process of the write operation; receiving a column instruction for performing the first access operation on the storage device, the column instruction carrying a column address; accessing the storage device according to the first row address and the column address A row address and an address space corresponding to the column address.

The storage device receives a row instruction that carries the first read/write indication information and the row address, determines whether the access operation is a read operation or a write operation according to the first read/write indication information, and performs the storage device according to the determined access operation. Setting a time threshold to complete the preparation operation of the determined access operation, receiving a column instruction carrying the column address, and accessing the address space corresponding to the row address and the column address, so that the storage device recognizes in advance whether the access operation is a read operation or a write operation. It extends the response time of the storage device for reading and writing operations, and thus can communicate with the CPU. That is to say, the CPU avoids sending the read and write instructions separately before sending the line instruction, thereby enabling communication with the storage device and reducing bandwidth occupation.

With reference to the first aspect, in some possible implementations, the preparing operation for performing the determined access operation according to the determined first access operation comprises: configuring a data interface transmission of the storage device according to the determined first access operation Direction, the data interface transmission direction includes input direction and output direction.

The storage device can recognize in advance whether the access operation performed on the storage device is a read operation or a write operation according to the first read/write indication information carried by the row instruction, so that the preparation operation of the access operation can be performed. The preparation operation may be to open a data transceiving interface of the storage device and configure a transmission direction of the data transceiving interface. In this way, the storage device can recognize the read and write operations on the storage device in advance when receiving the row instruction, which is equivalent to extending the response time of the storage device to perform the read and write operations, thereby enabling communication with the CPU.

With reference to the first aspect, in some possible implementations, the first read/write indication information includes at least one field, where the determining, according to the first read/write indication information, that the first access operation is a read operation or a write operation comprises: And determining, according to the value of the at least one field, that the first access operation is a read operation or a write operation.

The read/write indication information may be at least one field, and the storage device may pre-configure a mapping relationship between the value of the at least one field and the read/write operation, so that the storage device obtains according to the at least one field. The value can determine whether the access operation performed on the storage device is a read operation or a write operation, and the storage device can prepare for the determined access operation in advance, which is equivalent to extending the response time of accessing the storage device, so that the storage device can be combined with the CPU. Normal communication.

With reference to the first aspect, in some possible implementations, the method further includes: receiving a second row of instructions for performing a second access operation on the storage device, the second row of instructions carrying a second access address, the second access address Included in the second row address and the second read/write indication information; determining, according to the second read/write indication information, that the second access operation is a read operation or a write operation; according to the determined second access operation and the determined first access operation Whether it is the same, determining whether to modify the data interface transmission direction of the storage device; if the determined second access operation is the same as the determined first access operation, determining that the data interface transmission direction of the storage device is not modified.

If the access operation determined by the storage device according to the second read/write indication information is different from the access operation determined according to the first read/write indication information, then the transmission direction of the data interface needs to be adjusted; if the storage device is in accordance with the second read/write indication When the access operation determined by the information is the same as the access operation determined according to the first read/write indication information, the transmission direction of the data interface does not need to be modified, so that the storage device can further reduce the operation steps and reduce the power consumption.

In a second aspect, the present application provides a storage device comprising means for performing the method of the first aspect or any possible implementation of the first aspect.

In a third aspect, the application provides a storage device, including a command decoding and execution module, a command address interface module, a clock domain conversion circuit module, a data interface module, and a data storage module; Receiving a first row of instructions for performing a first access operation on the storage device, and receiving a column instruction for performing the first access operation on the storage device; the clock domain conversion circuit module for converting the command address interface module to receive The first row instruction and the clock domain of the column instruction; the command decoding and execution module is configured to decode the first row instruction and the column instruction after converting the clock domain by the clock domain conversion circuit module, and identify the The first row of instructions carries the first access address and the column instruction carries the column address, wherein the first access address includes the first row address and the first read/write indication information, and determines the first according to the first read/write indication information. The access operation is a read operation or a write operation, and a preparation operation of the determined first access operation according to the determined first access operation The preparation operation is performed by the storage device to complete the read operation or the preparation process of the write operation within a preset time threshold; the data interface module is configured to receive or send data; and the data storage module is configured to translate according to the command And the first row address and the column address identified by the code and the execution module, and storing the data received by the data interface module to the first row address and the corresponding location of the column address The address space, or the data in the address space corresponding to the first row address and the column address is sent by the data interface module.

With reference to the third aspect, in some possible implementations, the command decoding and execution module is specifically configured to: configure a transmission direction of the data interface module according to the determined first access operation, where the transmission direction of the data interface module includes Input direction and output direction.

With reference to the third aspect, in some possible implementations, the first read/write indication information includes at least one field; the command decoding and execution module is specifically configured to: determine the first access according to the value of the at least one field The operation is the read operation or the write operation.

With reference to the third aspect, in some possible implementations, the command address interface module is further configured to receive a second row of instructions for performing a second access operation on the storage device; the clock domain conversion circuit module is further configured to convert the The clock domain of the second row instruction received by the command address interface module; the command decoding and execution module is further configured to decode the second row instruction after converting the clock domain by the clock domain conversion circuit module, and identify the The second row of instructions carries the second access address, where the second access address includes the second row address and the second read/write indication information, and determines, according to the second read/write indication information, that the second access operation is the read operation or Determining whether to modify the transmission direction of the data interface module according to the determined second access operation and whether the determined first access operation is the same, the determined second access operation and the determined first access operation When the same, it is used to determine not to modify the transmission direction of the data interface module.

In a fourth aspect, a system for accessing a storage device is provided, the system comprising: a CPU, a communication interface, and the storage device of the second aspect or the third aspect above. The CPU is connected to the storage device and the communication interface. The storage device is used to store instructions, the CPU is used to execute the instructions, and the communication interface is used to communicate with other network elements under the control of the CPU. When the CPU executes an instruction stored by the storage device, the execution causes the CPU to perform the method of the first aspect or any possible implementation of the first aspect.

In a fifth aspect, a computer storage medium is provided, the program storage code storing program code for indicating access to the storage device in any one of the possible implementation manners of the first aspect or the first aspect The instructions of the method.

The storage device receives the line instruction carrying the first read/write indication information and the row address, and determines whether the access operation is a read operation or a write operation according to the first read/write indication information, and can perform according to the determined access operation. The storage device completes the preparation operation of the determined access operation within a preset time threshold, receives the column instruction carrying the column address, and accesses the row address and the column address. The address space corresponding to the address enables the storage device to recognize in advance whether the access operation is a read operation or a write operation, which prolongs the response time of the storage device for reading and writing operations, thereby enabling communication with the CPU and avoiding the CPU before sending the line instruction. Sending read and write instructions separately reduces bandwidth usage.

DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The drawings to be used in the embodiments or the description of the prior art will be briefly described below.

1 is a schematic structural diagram of a storage device of the present application;

2 is a schematic diagram of a prior art read command accessing a storage device;

3a and 3b are schematic diagrams of a method for accessing a storage device by reading and writing instructions in the prior art;

4 is a schematic diagram of a method for accessing a storage device according to an embodiment of the present application;

5a and 5b are schematic diagrams showing an address space of a storage device of the present application;

FIG. 6 is a schematic flowchart of a method for accessing a storage device according to an embodiment of the present application; FIG.

7 is a schematic block diagram of a storage device according to an embodiment of the present application;

Figure 8 is a schematic block diagram of a system in accordance with an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a storage device according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the accompanying drawings in the embodiments.

In order to facilitate the understanding of the embodiments of the present application, the following elements are first introduced before the introduction of the embodiments of the present application.

Field Programmable Gate Array (FPGA) combines energy efficiency with high flexibility, which is approximately 10 to 100 times more efficient than general purpose processors. In addition, FPGAs are ideal for fine-grained acceleration.

The memory/NVM extension technology can meet the requirements of big data processing for memory computing through memory expansion, improve computing performance, and reduce the processing delay of tasks; or increase the capacity and access performance of data storage through NVM expansion to meet mass storage. demand. Because the DDR interface has high bandwidth and low latency, and its working mode is designed to access memory, it is the first choice for expanding memory and NVM. Among them, NVM is a new type of memory technology based on new semiconductor materials, which has the characteristics of not losing data after power supply is stopped.

The Serial Presence Detect (SPD) of the module exists through the chip. An integrated circuit (Inter-Integrated Circuit (IIC) serial interface-connected Electrically Erasable Read-Only Memory (EEPROM) device for storing information in a memory slot, storing memory The configuration information of the module is used to assist the memory controller to accurately adjust the physical/timing parameters of the memory to achieve the best use effect.

In the embodiment of the present application, the preparation operation of the access operation refers to the preparation operation that can be performed by accessing the storage space of the storage device according to the row address and the access instruction, and may be all preparation operations that the storage device can perform in advance or partially take a long time. The preparation operation, etc., as long as the storage device can complete the preparation operation of the read/write operation within the time specified by the DDR protocol after receiving the column command, is within the scope of the protection of the present application, and the preparation operation is The transmission direction of the configuration data transceiver interface that takes a long time is taken as an example for description.

It should be understood that, in the embodiment of the present application, the storage device may be an FPGA-based storage device or other storage device with similar functions. For the convenience of description, the following embodiments are described by taking an FPGA storage device as an example, but the present application is not limited thereto.

FIG. 1 shows a schematic structural diagram of an FPGA storage device. As shown in FIG. 1, the FPGA-based storage device 100 mainly includes a data interface module 101, a clock domain conversion circuit module 102, a command decoding (Dec) and an execution module 103, and a data storage module 104, a command address interface module 105, and the like. Part of the composition.

The data interface circuit module 101 further includes a receiving part and a transmitting part. The receiving portion of the data interface circuit portion 101 mainly samples and receives high-speed serial signals such as data from the high-speed bus interface, and performs serial-to-parallel conversion to convert into parallel signals of relatively low speed; the transmitting portion of the data interface circuit portion 101 is mainly Receive data from the FPGA, perform parallel-to-serial conversion, modulation, etc., and then send it to the high-speed bus interface.

The receiving portion of the command address interface module 105 mainly samples and receives high-speed serial signals such as addresses and commands on the high-speed bus interface, and performs serial-to-parallel conversion to convert into parallel signals of relatively low speed.

Since the command or address is unidirectional from the outside of the FPGA to the inside of the FPGA, the command address interface module 105 has only the receiving portion, and the data interface circuit module 101 is a bidirectional interface because of the need to receive and transmit data, and also needs to have a direction. The control circuit performs the conversion of the transmission and reception directions.

The clock domain conversion circuit module 102 converts the signal from the interface circuit clock domain to the FPGA internal clock domain, or converts the signal from the FPGA internal clock domain to the interface circuit clock domain because In the hardware circuit, the signal must match the clock signal of the part, otherwise a signal sampling error will occur.

The command decode and execute module 103 decodes the command and address on the command bus to translate the correct DDR command sequence and execute the corresponding command based on the internal state.

The storage portion 104 inside the storage device is used to store read and write data.

The command sequence on the DDR access bus has command sequences such as ACT and Column Address Select (CAS). Specifically, the first is the ACT command, which is used to open a row in a Rank/Bank Group/Bank command; then the CAS command is used to select the column address in the row, and finally the bidirectional data control pin on the data bus ( Bi-directional Data Strobe (DQS)/Bi-directional data bus (DQ); after accessing the line, use the PreCharge command to close the line; the commands on the DDR bus must meet the DDR standard specification. Timing requirements.

Definition of several time information in the DDR standard:

Time RAS-to-CAS Delay (tRCD): The time between the ACT command and the receipt of a column instruction;

Postal Attachment Latency (AL);

Column Address Select Latency (CL): The time from when the CAS command carrying the read command is internally sent to the first data output, CL is only used during reading;

Column Write Write Latency (CWL): The time between the CAS instruction carrying the write command internally and the first visible data input is defined as CWL. This is a new timing parameter for DDR3 and is only used during write operations;

Time of Read Latency (RL): The delay of the first DQ on the data bus from the CAS command when reading the command, generally RL=AL+CL;

Time of Write Latency (WL): The delay of the first DQ on the data bus from the CAS command when writing a command, typically WL=AL+CWL.

Most current CPUs do not support the case where AL is not equal to zero. In the above calculation, AL=0 is taken as an example, but the present application is not limited thereto.

DDR is a data transmission technology that has a data transmission on the falling edge of the rising edge of the associated clock signal. Compared with single edge sampling, the data transmission rate can be doubled. It is widely used in the memory field. Since the DDR bus was originally designed to directly access DRAM memory particles, only ten Read and write access can be completed in a few to a few nanoseconds with a very short delay. Therefore, the effective delay ranges of the critical delay parameters CL/RL and CWL/WL specified in the DDR protocol are small. For example, the CL valid range in the DDR4 protocol is 9 to 24 clock cycles (as shown in Table 1 below), and the maximum value corresponds to 30 ns.

Table 1

A6	A5	A4	A2	CAS Latency
0	0	0	0	9
0	0	0	1	10
0	0	1	0	11
0	0	1	1	12
0	1	0	0	13
0	1	0	1	14
0	1	1	0	15
0	1	1	1	16
1	0	0	0	18
1	0	0	1	20
1	0	1	0	twenty two
1	0	1	1	twenty four
1	1	0	0	Reserved
1	1	0	1	Reserved
1	1	1	0	Reserved
1	1	1	1	Reserved

Since the memory controller in the CPU is designed and implemented based on the JEDEC protocol, the read and write latency that can be set is also short. Therefore, the expansion of the interconnect and memory/NVM access directly on the memory side may result in an access timing that does not meet the protocol requirements, resulting in the extended storage device being unable to communicate with the CPU. For example, as shown in Figure 2, when the CPU first issues an ACT command and then issues a read command (read (READ) command), the response time of the extended storage device is only t = tCL, if the DDR storage device cannot be specified. Giving a response within the time (for example, output data (Dout)) causes the CPU to collect the wrong data and thus cannot communicate with the extended storage device.

The prior art proposes to use the command field reserved in the DDR bus protocol to extend the read/write in advance. The commands PR1/PW1, PR2/PW2 (as shown in Table 2), when an access request needs to be initiated to the extended storage device, the memory controller first gives an extended read/write command, and then gives a regular ACT command and read. Instruction or write instruction. The extended storage device performs read and write access according to the received early read/write command, and then responds according to the normal DDR read/write command.

Table 2

Therefore, as shown in FIG. 3a and FIG. 3b, in the prior art, each time the read/write access is performed, the memory controller needs to issue the PR1/PW1, PR2/PW2 instructions in advance, and then the normal ACT command, Read command (RD) or write command (WR), the operation of redundant PR1/PW1, PR2/PW2 instructions requires a large DDR access bandwidth.

4 shows a schematic diagram of a method 200 of accessing a storage device, which may be performed by a storage device, in accordance with one embodiment of the present application. The method 200 includes:

S210, receiving a first row of instructions for performing a first access operation on the storage device, where the first row of instructions carries a first access address, where the first access address includes a first row address and first read/write indication information;

S220. Determine, according to the first read/write indication information, that the first access operation is a read operation or a write operation;

S230. Perform a preparation operation of the determined first access operation according to the determined first access operation, where the preparation operation is used by the storage device to complete the read operation or the preparation process of the write operation within a preset time threshold.

S240. Receive a column instruction for performing the first access operation on the storage device, where the column instruction carries a column address.

S250. Access the first row address and the address space corresponding to the column address in the storage device according to the first row address and the column address.

Specifically, the storage device receives an ACT command, and the ACT command is used to activate a certain row of data in the DDR. The ACT command carries a first access address, where the first access address includes a first row address and first read/write indication information, and the storage device determines, according to the first read/write indication information, whether the access operation is a read operation or a write operation, and according to the The determining the access operation is performed to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address.

The storage device determines, according to the first read/write indication information, that the access operation performed on the storage device is a read operation (that is, the access command is a read command), and performs a preparation operation required to send the data; the storage device reads and writes according to the first read/write The indication information determines that the access operation performed on the storage device is a write operation (ie, the access instruction is a write command), and a preparation operation required to store the received data into the storage space. In this way, the storage device can recognize in advance whether a read operation or a write operation is to be performed on the access operation performed by the storage device. In other words, the storage device can know in advance that the access instruction is a read command or a write command according to the first read/write indication information, so that the storage device can extend the response time of the access operation, that is, the DDR protocol is required to complete the data within the specified time. A read operation or a write operation so that the storage device can communicate normally with the CPU.

As shown in FIG. 2, in the prior art, when the CPU issues a read command (ie, the read/write indication information carried by the CAS command), the response time of the storage device is only t=tCL from the receipt of the CAS command, and is shown in Table 1. It can be seen that CL ≤ 20 cycles, but the extended storage device generally has a relatively large delay. For example, in an FPGA device at a rate of 1600 MT/s, the RL needs about 28-30 cycles, which cannot meet the delay of the standard DDR protocol. The FPGA device has different RL delays at different rates. The specific correspondence is shown in Table 3.

table 3

DDR4 rate (MT/s)	RL delay value (cycle)
1333	26~28
1600	28~30
1866	32
2133	38

The embodiment of the present invention takes the rate of the FPGA storage device as 1600MT/s as an example. The CPU uses the first read/write indication information carried in the ACT command to know in advance that the access operation is a read operation (or a write operation), and the storage device access operation is performed. Reaction time can be extended to ACT instructions and CAS instructions The time between the command and the time when the CAS instruction to the data appears on the bus (or the data is stored in the address space), that is, t = tRCD + tCL (tCWL).

Table 4

For example, as shown in Table 4, when RCD=10 cycles, the double data rate DDR4 rate is 1600MT/s, and the actual rate is 1600/2=800MT/s, that is, the period is 1/800=1.25ns, that is, , tCL = 10 * 1.25 = 12.5 ns. The minimum value of RCD is 12.5 ns (ie 10 cycles) with no maximum. So RL = RCD + CL > 30 cycles, so that the requirements of 28-30 cycles can be met, enabling the CPU to communicate with the FPGA storage device.

It should be understood that, in the embodiment of the present application, the “command” and the “instruction” are not distinguished, that is, the meanings of the description are consistent. The "access command" and the "access address" in the embodiment of the present application are the "fetching instruction" and the "fetch address" which are generally described, and the embodiment of the present application does not distinguish this.

Therefore, the method for accessing the storage device in the embodiment of the present application determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction carrying the first read/write indication information and the row address, and according to the Determining the access operation to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address, so that the storage The device recognizes in advance whether the access operation is a read operation or a write operation, and prolongs the response time of the storage device for reading and writing operations, thereby enabling communication with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

Optionally, the first read/write indication information includes at least one field, where the determining, according to the first read/write indication information, that the first access operation is a read operation or a write operation comprises: determining, according to the value of the at least one field Determining whether the first access operation is a read operation or a write operation.

The first read/write indication information may be at least one field, and the storage device may determine, according to the at least one field, whether the access operation performed on the storage device is a read operation or a write operation. The at least one field may be a high-order field of the access address, and the storage device may determine whether to be a read command or a write command by a difference in the value of the high-order field of the access address extension, for example, if the access address includes a row address A field is included, the value of which is 0 indicates that the access instruction is a write instruction; the value of this field indicates that the access instruction is a read instruction.

It should be understood that, when the at least one field is a plurality of fields, the storage device may configure, in advance, a mapping relationship between the values of the multiple fields and the access instruction.

It should also be understood that the read/write indication information may also be other indication information that can be used to distinguish the access instruction from a read command or a write command, which is not limited in this application.

Optionally, the storage device may further determine whether the access operation of the storage device is a read operation or a write operation according to whether the value of the first read/write indication information belongs to an address space of the storage device. For example, the storage device determines the byte space reserved in the Serial Presence Detect (SPD) information of the module (that is, the real storage space) as the write address space. When the first read/write indication information is at least one field, the storage device determines whether the access operation is a read operation or a write operation according to whether the value of the at least one field belongs to an address range of the write address space. If the value of the at least one field belongs to the address range of the write address space, determining that the access instruction is a write instruction; if the value of the at least one field does not belong to the write address space, determining that the access instruction is a read instruction.

It should be understood that the storage device may also determine the byte space reserved in the SPD information as the read address space, and the storage device determines whether the access operation is a read operation or a write operation according to whether the value of the at least one field belongs to the read address space. If the access address belongs to the read address space, it is determined that the access operation is a read operation, otherwise it is a write operation.

It should be noted that, when the at least one field is the address high bit, the lower address (ie, the row address) is used as the maximum value to calculate whether the value of the at least one field belongs to the address space of the storage device.

Optionally, when the first read/write indication information is represented by the at least one field, the storage device may further determine a virtual address space according to the value of the at least one field, where the storage device further includes the reserved byte in the SPD information. Space (that is, the real storage space). Thus, the storage device includes two address spaces, which can be regarded as a read address space and a write address space, respectively.

It should be noted that the at least one field may be a high address, and the lower address (ie, the row address) is a maximum value, and the address space determined according to the at least one field is actually a virtual space, and is not a space where the storage device actually exists.

When the storage device determines that the access address belongs to the write address space according to the value of the at least one field, it is considered to be a write command (ie, a write operation to the storage device). As shown in Figure 5a, the actual storage space of the FPGA is 0x00000000~0x0000FFFF. Through the mapping of the storage space, when the CPU starts, the storage space seen is as shown in FIG. 5b, and the write address space is 0x00000000~0x0000FFFF, the read address space is 0x00010000~0x0001FFFF.

Specifically, two Rank/Bank Group/Bank address spaces can be set in the FPGA storage device, the read address space is the Rank0/Bank Group0/Bank0 address, and the write address space is the Rank1/Bank Group1/Bank1 address. When the CPU's Basic Input/Output System (BIOS) is started, the two address spaces are mapped to a specific address space segment. Assume that the size of the address space inside the FPGA storage device is 0x10000, and distinguish whether it is a read command or a write command by the difference of the address range. For example, the read address space is 0x00100000 to 0x0010ffff, and the write address space is 0x00110000 to 0x0011ffff. Alternatively, the difference between the read address space and the write address space may be only the upper bits of the address.

For example, if the real address space (ie, the write address space) is 0 to 10, the address space corresponding to the read address (ie, the virtual address space) is 10 to 20, and the row address of the memory address carried by the ACT command is 5, The value of at least one field is 10, that is, the access address is 15, wherein the address greater than 10 indicates that the memory access command is a read command, and the real read address is still 15-10=5, which is a combination address address 5 address space. The data is read; if the row address is 5 and the value of at least one field is 0, it is represented as a write command, and the data is stored in the address space of address 5.

The command interface circuit inside the FPGA receives the high-speed command/address serial data from the command address bus, and then converts it into a low-speed parallel signal. After passing through the clock domain conversion circuit, it enters the command decoding circuit and translates the DDR command. The execution unit determines whether it is an ACT command. If it is an ACT command, it determines whether it is a read command or a write command according to the first read/write indication information carried in the ACT command. In this way, the storage device can determine in advance whether the access instruction is a read command or a write command according to the first read/write indication information. Receiving the column instruction carrying the column address and accessing the address space corresponding to the row address and the column address, so that the storage device can extend the time from the recognition of the access command to the response, that is, the DDR protocol requirement is met, so that the storage device can The CPU communicates normally.

Optionally, in an embodiment of the present application, the preparing operation of performing the determined access operation according to the determined first access operation includes: configuring a data interface transmission direction of the storage device according to the determined first access operation The data interface transmission direction includes an input direction and an output direction.

Specifically, the storage device may determine an access operation performed on the storage device in advance according to the first read/write indication information carried in the ACT command, and perform a preparation operation of the access operation. The preparation operation may be to open a data transceiving interface, and adjust a data transmission direction of the data transceiving interface. Specifically, if the storage device determines that the access operation to the storage device is a read operation according to the first read/write indication information, the storage device adjusts the data transceiving interface to a sending status. If the storage device is based on The first read/write indication information determines that the access operation to the storage device is a write operation, and the storage device adjusts the data transceiving interface to a receiving state.

Optionally, in an embodiment of the present application, the method further includes: receiving a second row of instructions for performing a second access operation on the storage device, where the second row of instructions carries a second access address, where the second access address includes The second row address and the second read/write indication information; determining, according to the second read/write indication information, that the second access operation is a read operation or a write operation; and the second access operation determined according to the second read/write indication information Whether the first access operation determined by the first read/write indication information is the same, determining whether to modify the data interface transmission direction of the storage device; and determining the second access operation and the first read/write indication information according to the second read/write indication information The determined first access operation is the same, and it is determined that the data interface transmission direction of the storage device is not modified.

Specifically, after the storage device completes an access operation (represented as the first access operation), it records whether the first access operation finally performs a read operation or a write operation. Receiving, by the storage device, a second row of instructions for performing an access operation (represented as a second access operation) to the storage device, the second row of instructions carrying a second access address similar to the first row of instructions, and the second access The address includes a second row address and a second read/write indication information, and the storage device determines, according to the second read/write indication information, that the second access operation is a read operation and a write operation. At this time, whether the second access operation determined by the storage device according to the second read/write indication information is the same as the stored first access operation, determining whether the transmission direction of the storage device data interface needs to be modified.

If the access operation determined by the storage device according to the second read/write indication information is the same as the access operation determined according to the first read/write indication information, the transmission direction of the data interface does not need to be modified; if the second read/write indication information determines the access operation When the access operation determined by the first read/write indication information is different, it is necessary to adjust the transmission direction of the data interface at this time. In this way, when the access operation determined by the second read/write indication information is the same as the access operation determined by the first read/write indication information, the storage device can further reduce the operation steps and reduce the power consumption.

Optionally, in an embodiment of the present application, after receiving the ACT command that carries the row address and the first read/write indication information, the storage device further receives the CAS command (ie, the column command), and the CAS command also carries The read/write indication information (represented as the third read/write indication information) is used to determine that the access operation performed on the storage device is a read operation or a write operation. Therefore, after receiving the CAS command, the storage device may determine whether the access address of the storage device can be accessed according to whether the access command determined according to the first read/write indication information is the same as the access command determined according to the second read/write indication information. If the access operation and the third read/write indication information are determined according to the first read/write indication information If the determined access operation is the same, the storage device accesses the storage address corresponding to the row address carried by the ACT and the column address carried by the CAS. The storage device of the embodiment of the present application can recognize the read/write instruction in advance, and start the read/write access operation in advance, thereby improving the bus transmission efficiency and the CPU processing efficiency.

Optionally, in an embodiment of the present application, if the access operation determined by the storage device according to the first read/write indication information carried by the ACT command is inconsistent with the access operation determined according to the second read/write indication information carried by the subsequent CAS command, When the storage device gives the information of the DDR access exception, the CPU is notified by an Error Correction Code (ECC) or an Alert_n pin information.

When receiving an error indication of ECC error or Alert_n, the CPU determines whether the accessed storage space conforms to the access characteristics, and performs the correction to continue the access.

Therefore, the method for accessing the storage device in the embodiment of the present application determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction carrying the first read/write indication information and the row address, and according to the Determining the access operation to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address, so that the storage The device recognizes in advance whether the access operation is a read operation or a write operation, and prolongs the response time of the storage device for reading and writing operations, thereby enabling communication with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

FIG. 6 illustrates an interaction flow diagram of a method of accessing a storage device in accordance with one embodiment of the present application. The meanings of the various terms in the embodiments of the present application are the same as those of the foregoing embodiments.

It should be noted that this is only to help those skilled in the art to better understand the embodiments of the present application, and not to limit the scope of the embodiments of the present application.

310. The CPU carries a first access address on the first ACT command, where the first access address includes a first row address and first read/write indication information.

320. The CPU sends a first ACT command to the storage device.

330. The storage device configures a transmission direction of the data transceiving interface according to the first read/write indication information.

The storage device determines whether the first access operation is a read operation or a write operation according to the first read/write indication information, and configures a transmission direction of the corresponding data transceiving interface according to the determined first access operation. If the first access operation is a read operation, the storage device adjusts the data transceiving interface to a transmit status. If the first access operation is a write operation, the storage device adjusts the data transceiving interface to a receiving state.

340. The CPU sends a first CAS instruction to the storage device, where the CAS instruction carries the first column address.

After receiving the first ACT instruction carrying the first read/write indication information, the storage device also receives the first CAS instruction, and the first CAS instruction carries the column address.

350. The storage device accesses the address space corresponding to the first row address and the first column address according to the first row address and the first column address.

360. The CPU carries a second access address on the second ACT instruction, where the second access address includes a second row address and second read/write indication information.

370. The CPU sends a second ACT command to the storage device.

380. Determine whether the access operation determined by the storage device according to the first read/write indication information is the same as the access operation determined by the second read/write indication information, and determine whether to modify the transmission direction of the data interface.

If they are different, you need to configure the transmission direction of the appropriate data interface. If they are the same, you do not need to modify the transmission direction of the data interface. The storage device can further reduce the operation steps and reduce power consumption.

390. The CPU sends a second CAS instruction to the storage device, where the second CAS instruction carries the second column address.

400. The CPU accesses the address space corresponding to the second row address and the second column address according to the second row address and the second column address.

It should be understood that the foregoing specific manners of the corresponding information may refer to the foregoing embodiments, and are not described herein for brevity.

Therefore, the method for accessing the storage device in the embodiment of the present application determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction carrying the first read/write indication information and the row address, and according to the Determining the access operation to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address, so that the storage The device recognizes in advance whether the access operation is a read operation or a write operation, and prolongs the response time of the storage device for reading and writing operations, thereby enabling communication with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

It should be understood that, in the various embodiments of the present application, the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application. The implementation process constitutes any limitation.

A method of accessing a storage device according to an embodiment of the present application is described in detail above, which will be described below. A storage device according to an embodiment of the present application.

FIG. 7 shows a schematic block diagram of a memory device 500 in accordance with an embodiment of the present application. As shown in FIG. 7, the storage device 500 includes:

The first receiving module 510 is configured to receive a first row of instructions for performing a first access operation on the storage device, where the first row of instructions carries a first access address, where the first access address includes a first row address and a first read and write address Indication information;

The first determining module 520 is configured to determine, according to the first read/write indication information, that the first access operation is a read operation or a write operation;

The first processing module 530 is configured to perform a preparation operation of the determined first access operation according to the first access operation determined by the first determining module 520, where the preparing operation is used by the storage device to complete the preset time threshold. a read operation or a preparation process of the write operation;

a second receiving module 540, configured to receive a column instruction for performing the first access operation on the storage device, where the column instruction carries a column address;

The second processing module 550 is configured to access the first row address and the address space corresponding to the column address in the storage device according to the first row address and the column address.

Therefore, the storage device provided by the embodiment of the present application determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction carrying the first read/write indication information and the row address, and determining according to the determined The access operation is performed to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address, so that the storage device is advanced It is recognized whether the access operation is a read operation or a write operation, which prolongs the response time of the storage device for reading and writing operations, and thus can communicate with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

Optionally, in an embodiment of the present application, the first processing module 530 is specifically configured to: configure a data interface transmission direction of the storage device according to the determined first access operation, where the data interface transmission direction includes an input direction and Output direction.

Optionally, in an embodiment of the present application, the first read/write indication information includes at least one field; the first determining module 520 is specifically configured to: determine, according to the value of the at least one field, that the first access operation is Read or write operation.

Optionally, in an embodiment of the present application, the storage device 500 further includes: a third receiving module, configured to receive a second row of instructions for performing a second access operation on the storage device, the second row of instructions Carrying a second access address, where the second access address includes a second row address and a second read/write indication information, and the second determining module is configured to determine, according to the second read/write indication information, that the second access operation is a read operation or a third determining module, configured to determine whether to modify an interface transmission direction of the storage device according to whether the determined second access operation is the same as the determined first access operation; and the third processing module, according to the determining The second access operation is the same as the determined first access operation, and is used to determine that the interface transmission direction of the storage device is not modified.

The storage device 500 according to an embodiment of the present application may correspond to a storage device of a method of accessing a storage device according to an embodiment of the present application, and the above-described and other operations and/or functions of respective modules in the storage device 500 respectively implement the foregoing respective methods The corresponding process, for the sake of brevity, will not be described here.

Therefore, the storage device provided by the embodiment of the present application determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction carrying the first read/write indication information and the row address, and determining according to the determined The access operation is performed to enable the storage device to complete the preparation operation of the determined access operation within a preset time threshold, receive the column instruction carrying the column address, and access the address space corresponding to the row address and the column address, so that the storage device is advanced It is recognized whether the access operation is a read operation or a write operation, which prolongs the response time of the storage device for reading and writing operations, and thus can communicate with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

8 shows a system 700 for accessing a storage device of the present application, the system 700 comprising: a CPU 702, a storage device 500 of the embodiment of the present application, at least one network interface 705 or other communication interface, and at least one communication bus 703 for Achieve connection communication between devices. A communication connection with at least one other network element is achieved by at least one network interface, which may be wired or wireless.

It should be understood that, in the embodiment of the present application, the processor 702 may be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit), or other programmable logic device. , discrete gates or transistor logic devices, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any processor with a short read and write delay.

The communication bus 703 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. The 702 and the storage device 500 may also communicate through other types of buses, such as optical fibers or optical waveguides. But for the sake of clarity, the various totals in the picture The lines are all labeled as communication bus 703.

The embodiment of the present application further provides a computer storage medium, which can store program instructions for indicating any of the above methods.

Optionally, the storage medium may be specifically the storage device 500.

As shown in FIG. 9 , the embodiment of the present application further provides a storage device 800, which is a hardware device for performing the foregoing method function of accessing a storage device.

The storage device 800 includes an interface module 801, at least one clock domain conversion circuit module 802, a command decode and execution module 803, and a data storage module 804. The interface module 101 further includes a data interface module and a command address interface module, wherein the data interface module further includes a receiving portion and a transmitting portion. The receiving part of the data interface module mainly samples and receives high-speed serial signals such as data from the high-speed bus interface, and performs serial-to-parallel conversion to convert into parallel signals with relatively low speed; the transmitting part of the data interface module mainly receives from the inside of the FPGA. Data, parallel and serial conversion, modulation, etc., are then sent to the high speed bus interface. The receiving part of the command address interface module mainly samples and receives high-speed serial signals such as addresses and command data from the high-speed bus interface, and performs serial-to-parallel conversion to convert into parallel signals with relatively low speed. The clock domain conversion circuit 102 converts the signal from the interface circuit clock domain to the FPGA internal clock domain, or converts the signal from the FPGA internal clock domain to the interface circuit clock domain, because in the hardware circuit, its signal must be associated with the portion of the The clock signals match, otherwise a signal sampling error will occur. The command decode and execute module 803 decodes the command and address on the command bus to translate the correct DDR command sequence and execute the corresponding command based on the internal state. The data storage module 804 is configured to store read and write data.

The storage device 800 receives a first row of instructions for performing a first access operation on the storage device through a command address interface, and transmits the command to the command decoding and execution module 803 via the clock domain conversion circuit 802, and the command decoding and execution module 803 translates The first access address carries the first access address, and the first access address includes the first row address and the first read/write indication information, and determines, according to the first read/write indication information, that the first access operation is a read operation or a write operation, and performing a preparation operation of the first access operation according to the determined first access operation, receiving a column instruction for performing the first access operation on the storage device through the command address interface, and transmitting to the clock domain conversion circuit 802 The command decoding and execution module 803, the command decoding and execution module 803 translates the first column instruction to carry the column address, and the data storage module 804 accesses the first row address and the column address in the storage device according to the first row address and the column address. The corresponding address space. For example, storing data in an address space corresponding to a first row address and a column address, or sending data in an address space corresponding to a first row address and a column address go with.

Optionally, as an embodiment, the command decoding and execution module 803 performs a preparation operation for the access operation, including configuring a data transmission direction of the interface module 801,

Optionally, as an embodiment, the first read/write indication information includes at least one field, and the command decoding and execution module 803 is further configured to determine, according to the value of the at least one field, that the first access operation is a read operation or Write operation.

Optionally, as an embodiment, the storage device 800 receives a second row of instructions for performing a second access operation on the storage device by using a command address interface, where the second row instruction carries a second access address and passes through a clock domain conversion circuit. 802 is transmitted to the command decoding and execution module 803, and the command decoding and execution module 803 translates the second access address to include the second row address and the second read/write indication information, and determines the second read/write indication information according to the second read/write indication information. The second access operation is a read operation or a write operation, and determining whether to modify the transmission direction of the data of the interface module 801 according to whether the determined second access operation is the same as the determined first access operation, if the second access operation is determined according to the determination As with the determined first access operation, it is determined that the data interface transmission direction of the storage device is not modified.

It can be seen from the above technical solution provided by the embodiment of the present application that the storage device determines whether the access operation is a read operation or a write operation according to the first read/write indication information by receiving a line instruction that carries the first read/write indication information and the row address. And performing, according to the determined access operation, a preparation operation that enables the storage device to complete the determined access operation within a preset time threshold, receiving a column instruction carrying the column address, and accessing an address space corresponding to the row address and the column address, The storage device is configured to recognize in advance whether the access operation is a read operation or a write operation, thereby prolonging the response time of the storage device for reading and writing operations, and thereby being able to communicate with the CPU. In addition, the embodiment of the present application avoids that the CPU separately sends the read/write instruction before sending the line instruction, thereby reducing bandwidth occupation.

It should be understood that the specific examples in the present application are only intended to help those skilled in the art to better understand the embodiments of the present application, and do not limit the scope of the embodiments of the present application.

It should be understood that the term "and/or" herein is merely an association relationship describing an associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

It should be understood that, in the various embodiments of the present application, the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application. The implementation process constitutes any limitation.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or a light. A medium such as a disk that can store program code.

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of this application is subject to the scope of protection of the claims.

Claims (12)

1. A method for accessing a storage device, comprising:

   Receiving a first row of instructions for performing a first access operation on the storage device, the first row of instructions carrying a first access address, where the first access address includes a first row address and first read/write indication information;

   Determining, according to the first read/write indication information, that the first access operation is a read operation or a write operation;

   Performing a preparation operation of the determined first access operation according to the determined first access operation, where the preparation operation is used by the storage device to complete the read operation or the preparation process of the write operation within a preset time threshold ;

   Receiving a column instruction for performing the first access operation on the storage device, the column instruction carrying a column address;

   And accessing, by the first row address and the column address, an address space corresponding to the first row address and the column address in the storage device.
2. The method according to claim 1, wherein the preparing operation for performing the determined access operation according to the determined first access operation comprises:

   And configuring, according to the determined first access operation, a data interface transmission direction of the storage device, where the data interface transmission direction includes an input direction and an output direction.
3. The method according to claim 1 or 2, wherein the first read/write indication information comprises at least one field;

   The determining, according to the first read/write indication information, that the first access operation is a read operation or a write operation includes:

   Determining, according to the value of the at least one field, that the first access operation is the read operation or the write operation.
4. The method according to any one of claims 1 to 3, further comprising:

   Receiving a second row of instructions for performing a second access operation on the storage device, the second row of instructions carrying a second access address, the second access address comprising a second row address and second read/write indication information;

   Determining, according to the second read/write indication information, that the second access operation is the read operation or the write operation;

   Determining whether to modify a data interface transmission direction of the storage device according to whether the determined second access operation is the same as the determined first access operation;

   And determining that the data interface transmission direction of the storage device is not modified when the determined second access operation is the same as the determined first access operation.
5. A storage device, comprising:

   a first receiving module, configured to receive a first row of instructions for performing a first access operation on the storage device, where the first row of instructions carries a first access address, where the first access address includes a first row address and a first Read and write indication information;

   a first determining module, configured to determine, according to the first read/write indication information, that the first access operation is a read operation or a write operation;

   a first processing module, configured to perform a preparation operation of the determined first access operation according to the first access operation determined by the first determining module, where the preparing operation is used by the storage device within a preset time threshold Completing the read operation or the preparation process of the write operation;

   a second receiving module, configured to receive a column instruction for performing the first access operation on the storage device, where the column instruction carries a column address;

   The second processing module is configured to access the address space corresponding to the first row address and the column address in the storage device according to the first row address and the column address.
6. The storage device according to claim 5, wherein the first processing module is specifically configured to:

   And configuring, according to the determined first access operation, a data interface transmission direction of the storage device, where the data interface transmission direction includes an input direction and an output direction.
7. The storage device according to claim 5 or 6, wherein the first read/write indication information includes at least one field;

   The first determining module is specifically configured to:

   Determining, according to the value of the at least one field, that the first access operation is the read operation or the write operation.
8. The storage device according to any one of claims 5 to 7, wherein the storage device further comprises:

   a third receiving module, configured to receive a second row of instructions for performing a second access operation on the storage device, where the second row of instructions carries a second access address, the second access address includes a second row address, and a second Read and write indication information;

   a second determining module, configured to determine, according to the second read/write indication information, that the second access operation is the read operation or the write operation;

   a third determining module, configured to determine whether to modify a data interface transmission direction of the storage device according to whether the determined second access operation is the same as the determined first access operation;

   And the third processing module is configured to determine not to modify a data interface transmission direction of the storage device when the determined second access operation is the same as the determined first access operation.
9. A storage device, comprising: a command decoding and execution module, a command address interface module, a clock domain conversion circuit module, a data interface module, and a data storage module;

   The command address interface module is configured to receive a first line instruction for performing a first access operation on the storage device, and receive a column instruction for performing the first access operation on the storage device;

   The clock domain conversion circuit module is configured to convert a clock domain of the first row instruction and the column instruction received by the command address interface module;

   The command decoding and execution module is configured to decode a first row instruction and a column instruction after converting a clock domain by the clock domain conversion circuit module, and identify that the first row instruction carries a first access address and The column instruction carries a column address, where the first access address includes a first row address and first read/write indication information, and determines, according to the first read/write indication information, that the first access operation is a read operation or a write operation, and a preparation operation of the determined first access operation according to the determined first access operation, the prepare operation being performed by the storage device to complete the read operation within a preset time threshold or The preparation process of the write operation;

   The data interface module is configured to receive or send data;

   The data storage module is configured to store data received by the data interface module to the first row address according to the first row address and the column address identified by the command decoding and execution module The address space corresponding to the column address, or the data in the address space corresponding to the first row address and the column address is sent by the data interface module.
10. The storage device according to claim 9, wherein the command decoding and execution module is specifically configured to:

    And configuring, according to the determined first access operation, a transmission direction of the data interface module, where a transmission direction of the data interface module includes an input direction and an output direction.
11. The storage device according to claim 9 or 10, wherein the first read/write indication information comprises at least one field;

    The command decoding and execution module is specifically configured to:

    Determining, according to the value of the at least one field, that the first access operation is the read operation or the write operation.
12. The storage device according to any one of claims 9 to 11, wherein the command address interface module is further configured to receive a second line instruction for performing a second access operation on the storage device;

    The clock domain conversion circuit module is further configured to convert a clock domain of the second row instruction received by the command address interface module;

    The command decoding and execution module is further configured to decode a second row of instructions after the clock domain is converted by the clock domain conversion circuit module, and identify that the second row instruction carries a second access address, where The second access address includes a second row address and second read/write indication information, and determines, according to the second read/write indication information, that the second access operation is the read operation or the write operation, and according to the determining Whether the second access operation is the same as the determined first access operation, determining whether to modify the transmission direction of the data interface module, when the determined second access operation is the same as the determined first access operation, Used to determine not to modify the transmission direction of the data interface module.

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