CN115460350B - Image processing method and system based on FPGA - Google Patents
Image processing method and system based on FPGA Download PDFInfo
- Publication number
- CN115460350B CN115460350B CN202211071486.9A CN202211071486A CN115460350B CN 115460350 B CN115460350 B CN 115460350B CN 202211071486 A CN202211071486 A CN 202211071486A CN 115460350 B CN115460350 B CN 115460350B
- Authority
- CN
- China
- Prior art keywords
- data
- intermediate data
- image
- address information
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 25
- 238000012545 processing Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000007547 defect Effects 0.000 claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims description 68
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 claims description 62
- 238000012937 correction Methods 0.000 claims description 17
- 230000000630 rising effect Effects 0.000 claims description 14
- 230000008569 process Effects 0.000 abstract description 12
- 238000004364 calculation method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000003702 image correction Methods 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
The invention discloses an image processing method and system based on an FPGA, which are applied to an FPGA processor, and relate to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and comprises the following steps: acquiring an environment image shot by a camera in real time, and converting the environment image into image data; removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data; judging whether the intermediate data meets a plurality of writing conditions of the address information one by one; if all the data are satisfied, the address information is written into the intermediate data to generate target data; the image data and the target data are sent to a main computing unit. The method solves the technical problems that the prior art needs the deep participation of the CPU, consumes a large amount of CPU resources and causes delay in the image processing process. The invention releases the basic image processing function by utilizing the parallel processing capability of the FPGA processor, thereby reducing the delay of the system.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to an image processing method and system based on an FPGA.
Background
With the development of artificial intelligence, intelligent automobiles gradually enter the field of view of the public. The intelligent automobile is also called an unmanned automobile, the surrounding environment of the automobile is sensed through an on-board sensor, and a central control system of the automobile comprehensively controls the steering and the speed of the automobile according to information such as roads, obstacles and the like sensed by the sensor, so that the automobile can safely and reliably run on the roads. Therefore, the image-based sensing technology is a key technology of the unmanned vehicle, and has obvious advantages in the fields of environment sensing and navigation compared with other traditional sensor sensing technologies. But the transmission and processing of a large number of images occupy a large amount of computing resources, so preprocessing of a large-data-volume, high-bandwidth image is increasingly important.
In the prior art, the image data is usually directly sent to the main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and depth participation of a CPU is required, so that a great deal of CPU resources are consumed, and delay is generated in the image processing process.
Disclosure of Invention
The invention provides an image processing method and system based on an FPGA, which solve the technical problems that in the prior art, image data is directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and the deep participation of a CPU is needed, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention provides an image processing method based on an FPGA, which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
acquiring an environment image shot by the camera in real time, and converting the environment image into image data;
removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data;
judging whether the intermediate data meets a plurality of writing conditions of the address information one by one;
if all the address information is satisfied, writing the address information into the intermediate data to generate target data;
the image data and the target data are sent to the main computing unit.
Optionally, the device motherboard connector is connected with the camera and the FPGA processor respectively; the step of acquiring the environment image shot by the camera in real time and converting the environment image into image data comprises the following steps:
transmitting the environment image shot by the camera to the equipment mainboard connector in real time according to a GMSL2 protocol to generate GMSL2 data;
And de-serializing the GMSL2 data through the equipment main board connector to generate image data.
Optionally, the step of removing address information carried by the image data and correcting according to an image defect of the image data to generate intermediate data includes:
removing address information carried by the image data to generate address-free data;
converting the RAW format in the address-free data into an RGB format to generate RGB image data;
correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction includes gamma correction, image enhancement, image scaling, and image recognition.
Optionally, the DDR4 component is connected with the FPGA processor; the step of judging whether the intermediate data satisfies a plurality of writing conditions of the address information one by one includes:
judging whether the intermediate data meets the writing starting condition of the address information;
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
If so, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and a write data valid signal to the DDR4 component;
when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
and if the address information is equal to the address information, judging that the intermediate data meets all the writing conditions of the address information.
Optionally, the step of determining whether the intermediate data satisfies a writing start condition of the address information includes:
judging whether the intermediate data meets the writing starting condition of the address information; the intermediate data further includes a frame start write signal;
if the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
and if the frame start writing signal is not a rising edge, judging that the intermediate data does not meet the writing start condition of the address information.
Optionally, the step of acquiring the frame start address of the intermediate data and determining whether the transmission data in the fifo queue satisfies the transmission condition of the intermediate data if the frame start address of the intermediate data is satisfied includes:
If yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, transmitting address information corresponding to the intermediate data to the DDR4 component;
if not, accumulating the new transmission data to the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data.
Optionally, if the address byte length corresponding to the intermediate data is obtained, and the step of judging whether the ready received signal sent by the DDR4 component is received includes:
if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
judging whether a ready received address signal sent by the DDR4 component is received or not;
and when the ready-to-receive address signal is received, acquiring a write data valid signal of the intermediate data, and judging whether the ready-to-receive data signal sent by the DDR4 component is received.
Optionally, when receiving the feedback signal of the DDR4 component, the step of determining whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data further includes:
When receiving a feedback signal of the DDR4 component, acquiring the byte number corresponding to the burst byte length data from the feedback signal;
judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, accumulating and writing new address data into the burst byte length data;
and skipping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
Optionally, the method further comprises:
acquiring an environment video shot by the camera in real time;
compressing the environment video according to a preset format and sending the environment video to the main computing unit.
The second aspect of the present invention provides an image processing system based on FPGA, applied to an FPGA processor, involving a camera and a main computing unit, where the FPGA processor is connected to the camera and the main computing unit, respectively, the system includes:
The image data module is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
the intermediate data module is used for removing address information carried by the image data, correcting the image defects according to the image data and generating intermediate data;
the writing condition module is used for judging whether the intermediate data meets a plurality of writing conditions of the address information one by one;
the target data module is used for writing the address information into the intermediate data to generate target data if all the address information is met;
and the sending module is used for sending the image data and the target data to the main computing unit.
From the above technical scheme, the invention has the following advantages:
according to the invention, the environment image shot by the camera is acquired in real time, the environment image is converted into the image data, and the address information carried in the image data is removed, so that the data transmission can be convenient, the efficiency and the delay are low, and the intermediate data are generated according to the corresponding correction of the image defects in the image data; and judging whether the intermediate data meets a plurality of writing conditions of the address information one by one, and when all the intermediate data meet the writing conditions, writing the address information into the intermediate data to generate target data. The image data is sent to the main calculation unit together with the target data. The method solves the technical problems that in the prior art, image data is usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, depth participation of a CPU is needed, a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention uses the parallel processing capability of the FPGA processor to release the basic image processing function in the main computing unit, reduces the delay of the system, directly uses the technical means of parallel and data flow of the FPGA to realize a large number of image processing algorithms in the early stage, releases a large number of computing resources and can be used for deploying more algorithm models.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a flowchart of steps of an image processing method based on FPGA according to a first embodiment of the present invention;
fig. 2 is a flowchart of steps of an image processing method based on FPGA according to a second embodiment of the present invention;
fig. 3 is a schematic structural connection diagram of a vehicle-mounted camera (camera), a device motherboard connector and an FPGA processor according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of an internal structure of an FPGA processor according to a second embodiment of the present invention;
Fig. 5 is a flow diagram of an internal state machine of an image processing method based on FPGA according to a third embodiment of the present invention;
fig. 6 is a schematic diagram of an external interface of a Writepath component of an FPGA-based image processing method according to a third embodiment of the present invention;
fig. 7 is a block diagram of an image processing system based on FPGA according to a fourth embodiment of the present invention.
Detailed Description
The embodiment of the invention provides an image processing method and system based on an FPGA (field programmable gate array), which are used for solving the technical problems that in the prior art, image data is directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and deep participation of a CPU (Central processing Unit) is needed, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of an FPGA-based image processing method according to an embodiment of the present invention.
The invention provides an image processing method based on an FPGA, which is applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
and 101, acquiring an environment image shot by a camera in real time, and converting the environment image into image data.
The FPGA is characterized in that FPGA (Field Programmable Gate Array), a Field Programmable Gate Array (FPGA) contains resources such as a trigger, a lookup table, a multiplier and the like, and a programmed FPGA processor connects the resources according to certain logic. The FPGA has rich IO resources, data can be processed in parallel in the chip, the FPGA can be externally connected with a DDR chip, and the FPGA can also be processed when a large data volume is needed to be cached. The data processing and transmission of the FPGA almost do not need the participation of a CPU, the CPU is required to participate in depth when the CPU calculates, the number of cores of the CPU is limited, and the switching task is delayed. The FPGA can process three rows of formulas, for example, to calculate Y, B, CR in parallel, one step per clock. R0.299, G0.587, B0.114 may be calculated simultaneously and then added for the next clock. The calculation of the section is completed independently by the multiplier and the resources such as the lookup table, and the participation of a CPU or other devices is not needed, so that the FPGA can utilize any collocation of logic resources to realize parallel processing of data, a large amount of calculation resources can be saved, and the main calculation unit can conveniently deploy more algorithm models.
In the embodiment of the invention, the environment image shot by the camera is acquired in real time, so that the environment image can be conveniently and timely processed, and the environment image is converted into the image data for convenient transmission, so that the subsequent processing is convenient.
And 102, removing address information carried by the image data, correcting according to the image defects of the image data, and generating intermediate data.
The intermediate data refers to new data generated by removing address information and performing operations such as image correction on the image data.
In a specific embodiment, address information carried by image data is removed, no-address data is generated, the no-address data is in a data format in an AMD FPGA, data transmission is carried out in a data stream mode, and no address operation is carried out, so that the transmission efficiency is high, and the delay is low. The correction may include gamma correction, image enhancement, image scaling, image recognition, etc. according to the respective image defects in the image data, and if no image defects are present, no correction operation is required.
Step 103, judging whether the intermediate data meets a plurality of writing conditions of the address information one by one.
The writing conditions refer to a series of conditions set according to the writing request of the address information.
In a specific embodiment, before the address information is written into the intermediate data, the intermediate data needs to satisfy a plurality of writing conditions simultaneously in a predetermined order. If the intermediate data is needed to be judged whether the condition for starting writing of the address information can be met or not; the second judgment is that the transmission data in the first-in first-out queue can not meet the transmission condition of the intermediate data; thirdly, judging whether a prepared receiving signal sent by the DDR4 component is received or not; and judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not, wherein the writing conditions comprise, but are not limited to, the corresponding writing conditions can be increased, modified or deleted according to actual situations.
And 104, if all the data are satisfied, writing the address information into the intermediate data to generate target data.
The target data is data obtained by performing a series of processes such as address removal, format conversion, image correction, and address rewriting on the image data.
In a specific embodiment, if the intermediate data satisfies all the writing conditions of the address information, the address information may be written into the intermediate data. If one item of intermediate data does not meet the writing condition of the address information, corresponding relevant operation is executed according to the condition of the writing condition, and the target data can not be generated until all writing conditions are met.
Step 105, the image data and the target data are sent to the main computing unit.
The target data after processing and the image data (raw data) are sent to the main computing unit together through the PCIE interface, and are used for later data placement and the like.
According to the invention, the environment image shot by the camera is acquired in real time, the environment image is converted into the image data, and the address information carried in the image data is removed, so that the data transmission can be convenient, the efficiency and the delay are low, and the intermediate data are generated according to the corresponding correction of the image defects in the image data; and judging whether the intermediate data meets a plurality of writing conditions of the address information one by one, and when all the intermediate data meet the writing conditions, writing the address information into the intermediate data to generate target data. The image data is sent to the main calculation unit together with the target data. The method solves the technical problems that in the prior art, image data is usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, depth participation of a CPU is needed, a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention uses the parallel processing capability of the FPGA processor to release the basic image processing function in the main computing unit, reduces the delay of the system, directly uses the technical means of parallel and data flow of the FPGA to realize a large number of image processing algorithms in the early stage, releases a large number of computing resources and can be used for deploying more algorithm models.
Referring to fig. 2-4, fig. 2 is a flowchart illustrating steps of an FPGA-based image processing method according to a second embodiment of the present invention.
The invention provides an image processing method based on an FPGA, which is applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
step 201, sending an environment image shot by a camera to a device motherboard connector in real time according to a GMSL2 protocol, and generating GMSL2 data.
GMSL (Gigabit Multimedia Serial Links) is a gigabit multimedia serial link.
In a specific embodiment, as shown in fig. 3, a vehicle-mounted camera (camera) is connected to a device motherboard FAKRA connector through a coaxial cable, and an internal running protocol is GMSL2, so that an environmental image shot by the camera is sent to the device motherboard connector through the coaxial cable to generate GMSL2 data.
Step 202, deserializing the GMSL2 data through the device motherboard connector to generate image data.
In a specific embodiment, the device motherboard FAKRA connector outputs the received GMSL2 signal to the deserializing chip, and converts GMSL2 data into image data (MIPI data) and sends the image data to the FPGA.
MIPI (Mobile Industry Processor Interface) is a mobile industry processor interface.
And 203, removing address information carried by the image data, correcting according to the image defects of the image data, and generating intermediate data.
Optionally, step 203 further comprises the following steps S11-S13:
s11, removing address information carried by the image data to generate address-free data;
s12, converting the RAW format in the address-free data into an RGB format to generate RGB image data;
s13, correcting according to the image defects of the RGB image data to generate intermediate data; the correction comprises gamma correction, image enhancement, image scaling and image recognition.
In a specific embodiment, as shown in fig. 4, the image data (MIPI data) is transmitted to the FPGA through IO, and first enters the mipi_rx component to be converted into unaddressed data (axi4_stream data).
Secondly, the camera enters a Bayer-RGB component to convert a RAW format transmitted by the camera into an RGB format, each pixel of the RAW format is represented by one color, and the other two colors can be obtained by calculating the difference value when the surrounding points need to contain the pixels of the color. For example, one pixel has only a green color, and the red color averages the two pixels up and down or left and right without the difference. The operation at this time is also realized by the data stream mode and the parallel buffer technology. The realization algorithm is a high-resolution difference algorithm, can provide finer image edge characteristics, is particularly suitable for unmanned vehicles to recognize scenes, and can be used for multipoint parallel calculation compared with an original CPU.
Finally, the Image processing component is also used for realizing the functions of gamma correction, image enhancement, image scaling and the like of the Image through a data stream mode, and specifically, the correction can be carried out according to the corresponding Image defects.
It should be noted that, the data flow mode is that the back-end component is ready to feed back the ready signal, and the upper component continues to transmit data downward when receiving the ready signal.
Step 204, judging whether the intermediate data meets a plurality of writing conditions of the address information one by one.
Optionally, the DDR4 component is also related, and the DDR4 component is connected with the FPGA processor; step 204 also includes the following steps S21-S26:
s21, judging whether the intermediate data meets the condition of starting writing of address information;
s22, if so, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
s23, if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
s24, if the data is received, reading burst byte length data from the intermediate data, and transmitting burst byte length data, address byte length and writing data valid signals to the DDR4 component;
S25, when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
and S26, if the address information is equal to the address information, judging that the intermediate data meets all writing conditions of the address information.
It should be noted that, the DDR4 component (DDR 4 chip) refers to a data cache for image processing; the writing start condition refers to a condition set for starting writing of address information; the frame start address refers to the start address of the first frame of the intermediate data; the first-in first-out queue (FIFO, first Input First Output) refers to a conventional sequential execution method, where an instruction entered first completes and retires, and then a second instruction is executed.
In a specific embodiment, as shown in fig. 4, when the image data is subjected to a series of processes to obtain intermediate data, after the intermediate data enters the Writepath component, a plurality of writing conditions are satisfied in a predetermined order, and then the address information can be written into the intermediate data.
Specifically, it is first determined whether or not the intermediate data satisfies the condition for starting writing of the address information, and when the intermediate data satisfies the condition for starting writing of the address information, the writing of the address information is started, and the frame start address of the intermediate data is acquired, and the address information is written from the frame start address. When the intermediate data does not satisfy the condition for starting writing of the address information, writing of the address information cannot be started.
The second judgment is that the transmission data in the first-in first-out queue can not meet the transmission condition of the intermediate data, when the transmission data is enough to transmit the address information corresponding to the intermediate data, the length of the address byte corresponding to the intermediate data is obtained, and the address information corresponding to the intermediate data is transmitted to the DDR4 component; when the conveying data is insufficient to convey the address information corresponding to the intermediate data, continuously accumulating the new conveying data until the conveying data is sufficient to convey the address information corresponding to the intermediate data.
And thirdly, judging whether a prepared receiving signal sent by the DDR4 component is received or not, reading burst byte length data from intermediate data when the prepared receiving signal is received, and transmitting burst byte length data, address byte length and writing data valid signals to the DDR4 component.
When the feedback signal of the DDR4 component is received, fourth judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data, and if so, judging that the intermediate data meets all writing conditions of the address information. The address information can be written into the intermediate data.
Optionally, step S21 further includes the following steps S31-S33:
s31, judging whether the intermediate data meets the condition of starting writing of address information; the intermediate data also includes a frame start write signal;
S32, if the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
if the frame start write signal is not a rising edge, it is determined that the intermediate data does not satisfy the start write condition of the address information.
The frame start write signal refers to a signal for starting writing of the first frame.
In a specific embodiment, the determination that the intermediate data cannot meet the start writing condition of the address information is determined by whether the frame start writing signal is a rising edge. If the frame start write signal is a rising edge, it is determined that the intermediate data satisfies the start write condition of the address information. If the frame start write signal is not a rising edge, it is determined that the intermediate data does not satisfy the start write condition of the address information.
Optionally, step S22 further includes the following steps S41-S43:
s41, if so, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
s42, if the data is satisfied, transmitting address information corresponding to the intermediate data to the DDR4 component;
and S43, if the transmission data does not meet the transmission conditions, accumulating the new transmission data into the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission conditions of the intermediate data.
In a specific embodiment, if the intermediate data meets the condition of starting writing of the address information, the frame start address of the intermediate data can be obtained, then the condition that the transmission data in the first-in first-out queue can not meet the transmission condition of the intermediate data is judged, when the transmission data is enough to transmit the address information corresponding to the intermediate data, the address byte length corresponding to the intermediate data is obtained, and the address information corresponding to the intermediate data is transmitted to the DDR4 component; when the conveying data is insufficient to convey the address information corresponding to the intermediate data, continuously accumulating the new conveying data until the conveying data is sufficient to convey the address information corresponding to the intermediate data.
Optionally, step S23 further includes the following steps S51-S53:
s51, if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
s52, judging whether a ready received address signal sent by the DDR4 component is received or not;
and S53, when the ready-to-receive address signal is received, acquiring a write data valid signal of the intermediate data, and judging whether the ready-to-receive data signal sent by the DDR4 component is received.
In the embodiment of the invention, if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, namely, the length of an address byte corresponding to the intermediate data is acquired, whether the ready received address signal and the ready received data signal sent by the DDR4 component are received or not is judged in sequence; when the ready received address signal is received, the write data valid signal of the intermediate data is acquired, and the write data valid signal is known, when the ready received address signal is received, the burst byte length data is read from the intermediate data, and the burst byte length data, the address byte length and the write data valid signal are transmitted to the DDR4 component.
Optionally, step S25 further includes the following steps S61-S64:
s61, when a feedback signal of the DDR4 component is received, acquiring the byte number corresponding to burst byte length data from the feedback signal;
s62, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
s63, when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, accumulating and writing the new address data into the burst byte length data;
s64, jumping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
In a specific embodiment, when a feedback signal of the DDR4 component is received, the feedback signal carries burst byte length data, wherein the burst byte length data comprises byte numbers, whether the byte numbers corresponding to the burst byte length data are equal to the byte numbers corresponding to the intermediate data or not is compared, and when the byte numbers are equal to the byte numbers corresponding to the intermediate data, the intermediate data can be judged to meet all writing conditions of address information, and the address information can be written into the intermediate data; when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, the new address data is accumulated and written into the burst byte length data, and the operation of comparing whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not is repeatedly executed until the byte numbers of the burst byte length data and the intermediate data are equal.
And step 205, if all the data are satisfied, the address information is written into the intermediate data to generate target data.
In the embodiment of the present invention, the implementation process of step 205 is similar to that of step 104, and will not be repeated here.
Step 206, sending the image data and the target data to the main computing unit.
In a specific embodiment, the FPGA transmits the processed image data (raw data) to the main computing unit for later data dropping, etc. As shown in fig. 4, the pcie_dma module packages the processed target data in the DDR4 module into a packet of PCIE protocol, and sends the packet of PCIE protocol to the main computing unit, so as to play roles of protocol conversion and data movement.
Note that DMA (Direct Memory Access), for direct memory access, can access DDR4 components in real time.
The method further comprises the following steps S71-S72:
s71, acquiring an environment video shot by a camera in real time;
s72, compressing the environment video according to a preset format and sending the environment video to a main computing unit.
It should be noted that, the cu_h264/H265 component shown in fig. 4 is a video codec module of the FPGA.
In a specific embodiment, the environment video data shot by the camera is acquired in real time, and the VCU_H264/H2265 module compresses the environment video data according to the H265 format. And transmits the compressed video to the main computing unit for later data dropping, etc.
According to the invention, the environment image shot by the camera is acquired in real time, the environment image is converted into the image data, and the address information carried in the image data is removed, so that the data transmission can be convenient, the efficiency and the delay are low, and the intermediate data are generated according to the corresponding correction of the image defects in the image data; and judging whether the intermediate data meets a plurality of writing conditions of the address information one by one, and when all the intermediate data meet the writing conditions, writing the address information into the intermediate data to generate target data. The image data is sent to the main calculation unit together with the target data. The method solves the technical problems that in the prior art, image data is usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, depth participation of a CPU is needed, a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention uses the parallel processing capability of the FPGA processor to release the basic image processing function in the main computing unit, reduces the delay of the system, directly uses the technical means of parallel and data flow of the FPGA to realize a large number of image processing algorithms in the early stage, releases a large number of computing resources and can be used for deploying more algorithm models.
Referring to fig. 5-6, fig. 5 is a schematic flow diagram of an internal state machine of an FPGA-based image processing method according to a third embodiment of the present invention.
The invention provides an internal state machine execution flow of an image processing method based on an FPGA, which is shown in combination with fig. 5 and 6, and specifically comprises the following steps:
the state machine goes from W_IDLE to W_WRADDR_CMD when axis_ tvs _i is a rising edge; meanwhile, assigning a frame start address to axi_awaddr_o; pulling down the dmadone signal, representing the start of writing data;
the data input into the FIFO by the waiting module interface axis interface in the W_WRADDR_CMD state machine can send a burst data; cut to when enough to send one burst of data: the w_wraddr_cmd_wait state machine pulls the axi_awvalid_o signal high and pulls the axi_wvalid_o signal low because the data is not transferred at this time, but the address of the data is transferred; assigning the byte length axi_awlen_o of the write; pulling up feedback axi_break_o to the DDR4 module;
waiting for DDR4 to transmit ready to receive address signals in the W_WRADDR_CMD_WAIT state machine: the axi_awready_i signal, when high, switches to the w_wrdata state machine while pulling the write data valid signal high: axi_wvalid_o; the axi_awvalid_o signal is pulled low because the address signal has been received by DDR4 when the axi_awready_i signal is high.
The received data ready signal from DDR4 is received at the W_WRDATA state machine: when axi_wrready_i, data in the FIFO is read at the same time until the data of one burst length is read, and the read data is sent to DDR4 together with axi_wvalid_o signal, axi_awleno signal, and the like.
When the data transmission of one burst is completed, the w_wrdata_cmd_last state machine is switched to, and the axi_write_o signal is pulled high, representing that one burst write is completed,
waiting for a feedback signal axi_bsvalid_i of DDR4 in a W_WRDATA_CMD_LAST state machine, and after receiving the feedback signal of DDR4, judging that the written burst byte number is insufficient for the byte number of axis_width_i, which is input by a module. If not enough to switch to the state machine: w_wraddr_cmd cycles. Meanwhile, according to the number of bytes written suddenly LAST time, the address written this time is accumulated in the W_WRDATA_CMD_LAST state machine: axi_awaddr_o. And (3) cycling repeatedly until the data of one frame is completely written. The state then switches to the idle state machine: W_IDLE, while pulling high the dmadone signal, waits for the next write.
Specifically, the meaning represented by each signal is as follows:
axis_treatment_o: judging whether the FIFO is full or not, if the FIFO is full, pulling down the signal tells the upstream that the data can not be sent any more;
axis_tdata_i: waiting for data written into the FIFO;
axis_tlast_i: waiting to write the last data flag bit of one row of FIFO data;
axis_width_i: the number of bytes of a row, used to calculate whether the abrupt writing is completed;
axis_height_i: how many lines a frame has for calculating whether a frame of data is completed;
start_addr_i: one frame is at the start write address of DDR 4.
As shown in fig. 6, the respective interfaces represent the following meanings:
axis is data stream data;
axis_tclk_i data stream clock;
axis_ tvs _i module start write signal;
axis_width_i: the frame width to be transmitted;
axis_height_i: the frame height to be transmitted;
start_addr_i: a starting position for starting writing in the memory;
axis_tddr_sel_i: a plurality of address selection signals;
rd_dmadone: the reading module reads out a frame indication signal;
m00_axi: an address mapping data interface;
dmadone: writing a frame indication signal;
write_addr: the frame address being written;
axis_tddr_sel_o: one frame being written, frame number.
Referring to fig. 7, fig. 7 is a block diagram of an image processing system based on FPGA according to a fourth embodiment of the present invention.
The invention provides an image processing system based on an FPGA, which is applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the system comprises:
The image data module 701 is configured to acquire an environmental image captured by the camera in real time, and convert the environmental image into image data;
the intermediate data module 702 is configured to remove address information carried by the image data, and correct the image data according to an image defect of the image data, so as to generate intermediate data;
a writing condition module 703, configured to determine whether the intermediate data meets a plurality of writing conditions of the address information one by one;
the target data module 704 is configured to write the address information into the intermediate data if all the address information is satisfied, and generate target data;
a transmitting module 705 for transmitting the image data and the target data to the main computing unit.
Optionally, the image data module 701 includes:
the image data sub-module is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
and the intermediate data sub-module is used for removing address information carried by the image data, correcting the image defects according to the image data and generating intermediate data.
Optionally, the intermediate data module 702 further includes:
the non-address data sub-module is used for removing address information carried by the image data and generating non-address data;
the RGB image data sub-module is used for converting the RAW format in the address-free data into an RGB format to generate RGB image data;
The intermediate data sub-module is used for correcting the image defects of the RGB image data to generate intermediate data; the correction comprises gamma correction, image enhancement, image scaling and image recognition.
Optionally, the DDR4 component is also related, and the DDR4 component is connected with the FPGA processor; the write condition module 703 further includes:
the writing condition submodule is used for judging whether the intermediate data meets the writing condition of the address information;
the transmission condition sub-module is used for acquiring a frame start address of the intermediate data and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data or not if the transmission condition is met;
the ready-received signal submodule is used for acquiring the address byte length corresponding to the intermediate data and judging whether the ready-received signal sent by the DDR4 component is received or not if the ready-received signal is met;
the DDR4 assembly submodule is used for reading burst byte length data from intermediate data and transmitting burst byte length data, address byte length and writing data effective signals to the DDR4 assembly if the burst byte length data and the address byte length and writing data effective signals are received;
the byte number judging sub-module is used for judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not when receiving the feedback signal of the DDR4 component;
And the all-writing-condition sub-module is used for judging that the intermediate data meets all writing conditions of the address information if the intermediate data is equal to the all-writing-condition sub-module.
Optionally, the writing condition sub-module further includes:
a writing start condition sub-module for judging whether the intermediate data meets the writing start condition of the address information; the intermediate data also includes a frame start write signal;
the frame start writing signal is a rising edge sub-module and is used for judging that the intermediate data meets the writing start condition of the address information if the frame start writing signal is a rising edge;
the frame start write signal is not a rising edge sub-module, and is used for determining that the intermediate data does not meet the start write condition of the address information if the frame start write signal is not a rising edge.
Optionally, the conveying condition sub-module further comprises:
the sub-module for judging the conveying condition is used for acquiring the frame start address of the intermediate data if the conveying condition is met, and judging whether the conveying data in the first-in first-out queue meets the conveying condition of the intermediate data or not;
the sub-module meeting the conveying condition is used for transmitting address information corresponding to the intermediate data to the DDR4 component if the conveying condition is met;
and the sub-module is not satisfied with the transmission condition and is used for accumulating the new transmission data into the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue satisfies the transmission condition of the intermediate data if the transmission condition is not satisfied.
Optionally, the ready received signal submodule further includes:
the address byte length submodule is used for acquiring the address byte length corresponding to the intermediate data if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
the ready-to-receive address signal sub-module is used for judging whether the ready-to-receive address signal sent by the DDR4 component is received or not;
and the ready-received data signal sub-module is used for acquiring a write data valid signal of the intermediate data when the ready-received address signal is received and judging whether the ready-received data signal sent by the DDR4 component is received.
Optionally, the judging byte number sub-module further includes:
the byte acquisition sub-module is used for acquiring the byte number corresponding to the burst byte length data from the feedback signal when the feedback signal of the DDR4 component is received;
a sub-module for judging whether the byte number is equal or not, and judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
the byte number is smaller than the sub-module, and is used for accumulating and writing new address data into the burst byte length data when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data;
And the jump execution sub-module is used for jumping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
The system further comprises:
the environment video sub-module is used for acquiring the environment video shot by the camera in real time;
and the compression environment video sub-module is used for compressing the environment video according to a preset format and transmitting the environment video to the main computing unit.
According to the invention, the environment image shot by the camera is acquired in real time, the environment image is converted into the image data, and the address information carried in the image data is removed, so that the data transmission can be convenient, the efficiency and the delay are low, and the intermediate data are generated according to the corresponding correction of the image defects in the image data; and judging whether the intermediate data meets a plurality of writing conditions of the address information one by one, and when all the intermediate data meet the writing conditions, writing the address information into the intermediate data to generate target data. The image data is sent to the main calculation unit together with the target data. The method solves the technical problems that in the prior art, image data is usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, depth participation of a CPU is needed, a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention uses the parallel processing capability of the FPGA processor to release the basic image processing function in the main computing unit, reduces the delay of the system, directly uses the technical means of parallel and data flow of the FPGA to realize a large number of image processing algorithms in the early stage, releases a large number of computing resources and can be used for deploying more algorithm models.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. An image processing method based on an FPGA is characterized by being applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
acquiring an environment image shot by the camera in real time, and converting the environment image into image data;
removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data;
judging whether the intermediate data meets a plurality of writing conditions of the address information one by one; the DDR4 component is connected with the FPGA processor; the step of judging whether the intermediate data satisfies a plurality of writing conditions of the address information one by one includes:
Judging whether the intermediate data meets the writing starting condition of the address information;
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
if so, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and a write data valid signal to the DDR4 component;
when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
if the address information is equal to the intermediate data, judging that the intermediate data meets all writing conditions of the address information;
if all the address information is satisfied, writing the address information into the intermediate data to generate target data;
the image data and the target data are sent to the main computing unit.
2. The FPGA-based image processing method of claim 1, further involving a device motherboard connector connected to the camera and the FPGA processor, respectively; the step of acquiring the environment image shot by the camera in real time and converting the environment image into image data comprises the following steps:
Transmitting the environment image shot by the camera to the equipment mainboard connector in real time according to a GMSL2 protocol to generate GMSL2 data;
and de-serializing the GMSL2 data through the equipment main board connector to generate image data.
3. The FPGA-based image processing method according to claim 1, wherein the step of removing address information carried by the image data and correcting according to an image defect of the image data to generate intermediate data includes:
removing address information carried by the image data to generate address-free data;
converting the RAW format in the address-free data into an RGB format to generate RGB image data;
correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction includes gamma correction, image enhancement, image scaling, and image recognition.
4. The FPGA-based image processing method according to claim 1, wherein the step of judging whether the intermediate data satisfies a start writing condition of the address information, comprises:
judging whether the intermediate data meets the writing starting condition of the address information; the intermediate data further includes a frame start write signal;
If the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
and if the frame start writing signal is not a rising edge, judging that the intermediate data does not meet the writing start condition of the address information.
5. The FPGA-based image processing method according to claim 1, wherein the step of acquiring the frame start address of the intermediate data and determining whether the transport data in the fifo queue satisfies the transport condition of the intermediate data if satisfied, comprises:
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, transmitting address information corresponding to the intermediate data to the DDR4 component;
if not, accumulating the new transmission data to the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data.
6. The FPGA-based image processing method according to claim 1, wherein the step of acquiring the address byte length corresponding to the intermediate data and determining whether a ready received signal sent by the DDR4 component is received if the address byte length is satisfied comprises:
If the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
judging whether a ready received address signal sent by the DDR4 component is received or not;
and when the ready-to-receive address signal is received, acquiring a write data valid signal of the intermediate data, and judging whether the ready-to-receive data signal sent by the DDR4 component is received.
7. The FPGA-based image processing method according to claim 1, wherein the step of determining whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data when the feedback signal of the DDR4 component is received, further comprises:
when receiving a feedback signal of the DDR4 component, acquiring the byte number corresponding to the burst byte length data from the feedback signal;
judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data;
when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, accumulating and writing new address data into the burst byte length data;
And skipping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
8. The FPGA-based image processing method of claim 1, further comprising:
acquiring an environment video shot by the camera in real time;
compressing the environment video according to a preset format and sending the environment video to the main computing unit.
9. An image processing system based on an FPGA, applied to an FPGA processor, involving a camera and a main computing unit, the FPGA processor being connected to the camera and the main computing unit, respectively, the system comprising:
the image data module is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
the intermediate data module is used for removing address information carried by the image data, correcting the image defects according to the image data and generating intermediate data;
the writing condition module is used for judging whether the intermediate data meets a plurality of writing conditions of the address information one by one; the DDR4 component is connected with the FPGA processor; the step of judging whether the intermediate data satisfies a plurality of writing conditions of the address information one by one includes: judging whether the intermediate data meets the writing starting condition of the address information; if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data; if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not; if so, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and a write data valid signal to the DDR4 component; when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data; if the address information is equal to the intermediate data, judging that the intermediate data meets all writing conditions of the address information;
The target data module is used for writing the address information into the intermediate data to generate target data if all the address information is met;
and the sending module is used for sending the image data and the target data to the main computing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211071486.9A CN115460350B (en) | 2022-09-02 | 2022-09-02 | Image processing method and system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211071486.9A CN115460350B (en) | 2022-09-02 | 2022-09-02 | Image processing method and system based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115460350A CN115460350A (en) | 2022-12-09 |
| CN115460350B true CN115460350B (en) | 2024-01-12 |
Family
ID=84301854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211071486.9A Active CN115460350B (en) | 2022-09-02 | 2022-09-02 | Image processing method and system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115460350B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521141A (en) * | 2011-12-01 | 2012-06-27 | 福州瑞芯微电子有限公司 | Device and method for reading compact storage image data |
| WO2018029339A1 (en) * | 2016-08-12 | 2018-02-15 | Chestnote N.V. | Conditional records data storage method and retrieval system |
| WO2018027535A1 (en) * | 2016-08-09 | 2018-02-15 | 华为技术有限公司 | Method for accessing storage device and storage device |
| CN110266961A (en) * | 2019-07-23 | 2019-09-20 | 江苏鼎速网络科技有限公司 | Image generating method, system and image forming apparatus |
| CN110717852A (en) * | 2019-06-13 | 2020-01-21 | 内蒙古大学 | FPGA-based field video image real-time segmentation system and method |
| CN112948295A (en) * | 2019-12-11 | 2021-06-11 | 中国科学院声学研究所 | FPGA and DDR high-speed data packet transmission system and method based on AXI4 bus |
| CN113630586A (en) * | 2021-07-28 | 2021-11-09 | 英特灵达信息技术(深圳)有限公司 | Single-light-source full-color camera |
| WO2021232843A1 (en) * | 2020-05-22 | 2021-11-25 | 浪潮电子信息产业股份有限公司 | Image data storage method, image data processing method and system, and related apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170083320A1 (en) * | 2015-09-19 | 2017-03-23 | Microsoft Technology Licensing, Llc | Predicated read instructions |
| US20220077856A1 (en) * | 2021-11-13 | 2022-03-10 | Intel Corporation | Circuits And Methods For Accessing Signals In Integrated Circuits |
-
2022
- 2022-09-02 CN CN202211071486.9A patent/CN115460350B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521141A (en) * | 2011-12-01 | 2012-06-27 | 福州瑞芯微电子有限公司 | Device and method for reading compact storage image data |
| WO2018027535A1 (en) * | 2016-08-09 | 2018-02-15 | 华为技术有限公司 | Method for accessing storage device and storage device |
| WO2018029339A1 (en) * | 2016-08-12 | 2018-02-15 | Chestnote N.V. | Conditional records data storage method and retrieval system |
| CN110717852A (en) * | 2019-06-13 | 2020-01-21 | 内蒙古大学 | FPGA-based field video image real-time segmentation system and method |
| CN110266961A (en) * | 2019-07-23 | 2019-09-20 | 江苏鼎速网络科技有限公司 | Image generating method, system and image forming apparatus |
| CN112948295A (en) * | 2019-12-11 | 2021-06-11 | 中国科学院声学研究所 | FPGA and DDR high-speed data packet transmission system and method based on AXI4 bus |
| WO2021232843A1 (en) * | 2020-05-22 | 2021-11-25 | 浪潮电子信息产业股份有限公司 | Image data storage method, image data processing method and system, and related apparatus |
| CN113630586A (en) * | 2021-07-28 | 2021-11-09 | 英特灵达信息技术(深圳)有限公司 | Single-light-source full-color camera |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115460350A (en) | 2022-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101237548B (en) | Image pickup apparatus and control method, image display apparatus and control method | |
| CN111651384B (en) | Register reading and writing method, chip, subsystem, register set and terminal | |
| CN108566357B (en) | Image transmission and control system and method based on ZYNQ-7000 and FreeRTOS | |
| CN102402413A (en) | Electronic system communicating with image sensor, controller and controlling method | |
| US11314457B2 (en) | Data processing method for data format conversion, apparatus, device, and system, storage medium, and program product | |
| CN113132552B (en) | Video stream processing method and device | |
| US9508109B2 (en) | Graphics processing | |
| US6446155B1 (en) | Resource bus interface | |
| US11237991B2 (en) | Image processing accelerator | |
| WO2024051674A1 (en) | Image processing circuit and electronic device | |
| US7739428B2 (en) | Memory control apparatus and memory control method | |
| CN115460350B (en) | Image processing method and system based on FPGA | |
| WO2023169369A1 (en) | Pedestrian re-identification method, system, apparatus and device, and medium | |
| CN106385556B (en) | A kind of arrow load ccd image acquisition compressibility | |
| CN101483768A (en) | Electronic apparatus | |
| EP2772049A1 (en) | Multiple stream processing for video analytics and encoding | |
| WO2013100920A1 (en) | Video encoding in video analytics | |
| CN117156073B (en) | Video data transmission device and system | |
| JPH09109461A (en) | Apparatus for restoring compressed two-value image data | |
| JP2004056376A (en) | Semiconductor device and data transfer control method | |
| US20100254618A1 (en) | Method for Accessing Image Data and Related Apparatus | |
| CN117351592B (en) | Vehicle abnormal state judging method and device, complex event processing engine and medium | |
| Flouzat et al. | EVPS: an automotive video acquisition and processing platform | |
| CN216661188U (en) | FPGA and ARM's waste classification device | |
| CN113328998B (en) | Image data transmission method and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |