JPS6488994A - Storage device - Google Patents

Storage device

Info

Publication number
JPS6488994A
JPS6488994A JP62245450A JP24545087A JPS6488994A JP S6488994 A JPS6488994 A JP S6488994A JP 62245450 A JP62245450 A JP 62245450A JP 24545087 A JP24545087 A JP 24545087A JP S6488994 A JPS6488994 A JP S6488994A
Authority
JP
Japan
Prior art keywords
refreshment
storage device
supplied
address
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245450A
Other languages
Japanese (ja)
Inventor
Shigeki Izumo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62245450A priority Critical patent/JPS6488994A/en
Publication of JPS6488994A publication Critical patent/JPS6488994A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce power consumption by providing a refreshment control circuit and a control circuit executing a normal memory access on a storage device using a DRAM array and independently operating them. CONSTITUTION:When the storage device is normally used, power source is supplied to the whole circuits in the device and the whole operation requested to the storage device is executed. When a refreshment request is given from the outside through a control line 24 now, a RAS (a row address strobing) signal 1 for operation, a column address strobing (a CAS) signal 1 are generated by the refreshment control, circuit 22 and supplied to the DRAM array 21 through OR gates 26 and 27 as they are. Besides, when an address and an access request are given from the outside through an address/control line 25, normal signals RAS 2 and CAS 2 are generated by an access control circuit 23 and supplied to the array 21 through the OR gates 26 and 2 in the same way. Thus, the refreshment operation is stopped in a memory content maintaining term.
JP62245450A 1987-09-29 1987-09-29 Storage device Pending JPS6488994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245450A JPS6488994A (en) 1987-09-29 1987-09-29 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245450A JPS6488994A (en) 1987-09-29 1987-09-29 Storage device

Publications (1)

Publication Number Publication Date
JPS6488994A true JPS6488994A (en) 1989-04-03

Family

ID=17133842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245450A Pending JPS6488994A (en) 1987-09-29 1987-09-29 Storage device

Country Status (1)

Country Link
JP (1) JPS6488994A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108139992A (en) * 2016-08-09 2018-06-08 华为技术有限公司 Access the method and storage device of storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108139992A (en) * 2016-08-09 2018-06-08 华为技术有限公司 Access the method and storage device of storage device
CN108139992B (en) * 2016-08-09 2020-06-16 华为技术有限公司 Method for accessing storage device and storage device

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