CN102522113B - SDRAM bridge circuit - Google Patents

Abstract

The invention relates to an SDRAM bridge circuit, comprising a first module, a second module and a PHY module, wherein the first module is used for analyzing SDRAM access commands sent by a controller, the second module is used for converting the SDRAM access commands into commands which are acceptable to the PHY module, the PHY module is used for accessing a memory by using the commands which are acceptable to the PHY module, and the memory and the controller are different in SDRAM type. According to the invention, the SDRAM controller can be allowed to realize the access to the DDR3 SDRAM to carry out data access through the bridge circuit; compared with replacing or redeveloping chips of the integrated SDRAM controller, the circuit modification is small, the development period is short, the cost is low, and the bridge circuit is well compatible with the original system.

Description

A kind of SDRAM bridgt circuit

Technical field

The present invention relates to the access control of Synchronous Dynamic Random Access Memory.

Background technology

Synchronous Dynamic Random Access Memory (SDRAM) is widely used in various electronic products, simultaneously also in continuous update.Up to now, a large amount of commercial successive dynasties products have SDRAM, DDR SDRAM, DDR2SDRAM and DDR3SDRAM (full name of DDR is Double Data Rate, and meaning is double data rate).More early stage SDRAM has exited main flow and has even stopped production, and increasing product is used storer of new generation as DDR3SDRAM.

SDRAM accepts the access of sdram controller, and DDR/DDR2/DDR3 SDRAM accepts the access of controller and PHY (Physical Interface, physical layer interface), realizes data access.Every generation memory all can only carry out physical connection with corresponding controller or PHY, can not be general between each generation, such as SDRAM can only connect sdram controller, can not connect DDR3PHY.

The chip that needs plug-in storer, generally by integrated corresponding memory controller or PHY, realizes the access to storer.When memory updating is regenerated, original memory controller or PHY also face replacing problem, and more changer controller or PHY just need to change or again develop chip.

When existing chip is changed or revised integrated new PHY, meeting " is pulled one hair and move the whole body ", causes circuit change amount large, and the construction cycle is long, costly, and can not be compatible with original system.Such as the central processor CPU of plug-in SDRAM need to be replaced by the CPU of plug-in DDR3SDRAM time, operating system also faces replacing, and software is exploitation again all; Huge when chip-scale, while again developing, overall work amount is huge, costly.

Summary of the invention

The object of this invention is to provide can solution of the above problems.

For achieving the above object, the invention provides a kind of SDRAM bridgt circuit.This circuit comprises the first module, the second module and PHY module; Wherein, the SDRAM visit order that the first module parses controller is sent here, the second module is converted to the acceptable order of PHY module SDRAM visit order, and PHY module is utilized the acceptable command access storer of described PHY module, and wherein storer and controller have different SDRAM types.

The present invention, by a kind of SDRAM bridgt circuit of design, can allow sdram controller pass through this bridgt circuit, realizes the access to DDR3SDRAM, carries out data access; Compare the chip of changing or again developing integrated sdram controller, circuit is changed little, and the construction cycle is short, and cost is low, and well compatible with original system.

Accompanying drawing explanation

Below by drawings and Examples, technical scheme of the present invention is described in further detail.In accompanying drawing:

Fig. 1 is the schematic diagram of the SDRAM bridgt circuit of the embodiment of the present invention;

Fig. 2 has illustrated the interface signal situation of the first module 110;

Fig. 3 has illustrated the schematic diagram that the second module 120 is changed;

Fig. 4 is SDRAM reading out data switching schematic diagram;

Fig. 5 is SDRAM data writing switching schematic diagram;

Fig. 6 is the schematic diagram in the situation of transferring one to one;

Fig. 7 writes the long schematic diagram that has influence on the switching of next reading order of command process holding time;

Fig. 8 is the schematic diagram in a pair of two situations of transferring;

The schematic diagram that Fig. 9 has illustrated to utilize two cover PHY switchings to read and write;

Figure 10 is state-transition table;

Figure 11 increases bit wide to reduce BL minimizing data transmission period;

Figure 12 reduces the schematic diagram that bit wide increases BL;

Figure 13 is the schematic diagram of the SDRAM bridgt circuit of another embodiment of the present invention.

Embodiment

Fig. 1 is the schematic diagram of the SDRAM bridgt circuit of the embodiment of the present invention.As shown in Figure 1, SDRAM bridgt circuit comprises the first module 110, the second modules 120 and DDR3 physical interface (calling PHY in the following text) module 130.Three common processes that sdram controller visit order are converted to access DDR3SDRAM storer that realize of module.

The first module 110, also can be described as SDRAM visit order and resolves and data transmit-receive module, is responsible for resolving the visit order that sdram controller is sent here, and the signal transmitting and receiving between outside sdram controller.Specifically, module 110 is resolved visit order, and gives order and data conversion module 120 by visit order and data to be written after resolving; Meanwhile, receive the sense data that the second module 120 is sent here, and it is sent to outside sdram controller.

The second module 120, also can be described as order and data conversion module, is responsible for SDRAM visit order and data to be converted to the acceptable form of DDR3 PHY and sequential.Specifically, order the visit order of SDRAM and data writing, is converted to form and the sequential of DDR3 PHY with data conversion module 120, gives DDR3 PHY module 130; Meanwhile, receive the reading out data that DDR3 PHY module 130 is sent here, be converted to data layout and the sequential of sdram controller, give SDRAM visit order and resolve and data transmit-receive module 110.

The integrated DDR3 PHY of DDR3 PHY module 130, is responsible for controlling DDR3 SDRAM storer.Specifically, receive order and data writing that the second module 120 is sent here, give outside DDR3 SDRAM storer; Receive the data that read from outside DDR3 SDRAM storer simultaneously, send to the second module 120.Different according to application scenarios, DDR3 PHY module 130 can be integrated one or more.In the drawings, DDR3 PHY module 130 is divided into a set of DDR3 PHY and two kinds of applicable cases of two cover DDR3 PHY (also comprising inner buffer).

Fig. 2 has illustrated the interface signal situation of the first module 110.As shown in Figure 2, the first module 110 according to sdram controller, send here synchronously with road clock CLK, all reception signals from sdram controller are carried out to input sample, to giving that the transmitted signal of sdram controller is exported and preparing the data that read from DDR3 SDRAM storer for sdram controller.

Signal from sdram controller comprises SDRAM control signal CKE, CS#, WE#, CAS#, RAS#, address signal A, BA, and data I/O shielded signal DQM, data-signal is DQ (write/read).CKE is sheet internal clock enable signal, and CS# forbids or enables all input signals outside CLK, CKE and DQM.WE# writes enable signal.CAS#, RAS# are respectively columns and rows address latch signals.Address signal A is address bus, and BA is that group address is selected.DQM controls output buffering under reading mode, shielding input data under WriteMode.

The first module 110 is carried out command analysis by above-mentioned control signal according to SDRAM truth table, be converted to SDRAM visit order, i.e. ACTIVE (activating row), READ (reading), WRITE (writing), PRECHARGE (precharge), REFRESH (refreshing) command signal.Command signal after conversion is given the second module 120.In addition, write and also done separated with the data bus of reading.

Fig. 3 has illustrated the schematic diagram that the second module 120 is changed.As shown in Figure 3, the conversion that the second module 120 is responsible between SDRAM visit order, data and DDR3 PHY unit.In an example, that according to the work clock of the second module 120 and sdram controller, sends here is synchronous with the phase relation between the clock CLK of road, visit order ACTIVE, READ, WRITE, PRECHARGE, REFRESH are converted to DDR3PHY command signal, change relevant data simultaneously.The work clock of the second module is the interface clock of DDR3 PHY unit regulation, and that can send here by collection sdram controller synchronously determines the phase relation between the two with the hopping edge of road clock CLK, to guarantee the correctness of data acquisition.Generally, the interface clock of PHY unit regulation has higher than the synchronous frequency with road clock.DDR3 PHY unit is to provide the internuncial IP (ip module) between memory controller and DDR3 memory devices.PHY unit provides standard DDR phy interface bus in memory interface side, in local side, provides internal bus interface.Internal bus interface has defined signal, the sequential between DDR3 PHY and corresponding DDR3 sdram controller.

In the present invention, sdram controller sends various visit orders, and SDRAM bridgt circuit is correct resolves and conversion visit order, realizes that data correctly write DDR3 SDRAM storer and from wherein reading.

Fig. 4 is SDRAM reading out data switching schematic diagram.When sdram controller is initiated read operation request, the first module in SDRAM bridgt circuit and the second module are converted to the logic reading order to DDR3 SDRAM by read operation request, and DDR3 PHY module reads DDR3 SDRAM according to this logic reading order.In embodiments of the present invention, the data of the DDR3 SDRAM that reads that the second module 120 reception DDR3 PHY modules are sent here; Then, the first module 110 is sent reading out data to sdram controller, completes the process of reading.In an example, the second module completes in the time and reads DDR3 SDRAM at the DDR3 side CL of agreement (CAS latency, column address strobe postpones, approximately 6-7 PHY clock); The first module is given sdram controller by reading out data at the controller side CL of the agreement from reading order (being generally 2,3 clocks) in the time.

Fig. 5 is SDRAM data writing switching schematic diagram.When sdram controller is initiated write operation requests, SDRAM bridgt circuit is converted to write operation requests the write order of DDR3 SDRAM.In addition, under burst mode, SDRAM bridgt circuit will receive complete or part data writing conventionally, just can give DDR3 PHY module, then writes DDR3 SDRAM.Therefore, write the time that DDR3 SDRAM data complete, longer than the conventional SDRAM ablation process time possibly, take sdram controller and write the portion of time after order.

When sdram controller is initiated data writing, and while initiating reading out data, according to writing DDR3SDRAM command process holding time, whether can have influence on the switching of SDRAM reading order, can produce following two kinds of substitute modes: (1) transfers one to one; (2) a pair of two switchings.

Fig. 6 is the schematic diagram in the situation of transferring one to one.When writing DDR3 SDRAM command process holding time and can not have influence on the switching of next reading order of sdram controller, adopt the plug-in DDR3 SDRAM of a set of DDR3 PHY just can complete sdram controller access switching.Now, sdram controller sends after data writing order, and the interval time enough that is bound to is initiated reading order again.In another case, if the reading address of sdram controller can predict, just can read in advance DDR3 SDRAM data, the buffer memory being left in PHY module is ready to.When PHY module is write data to DDR3 SDRAM, PHY module sends to sdram controller by the data of depositing in buffer memory by the second module 120, the first module 110 based on read request.

Specifically, order and data that the second module 120 is sent the first module 110 here, be converted to command signal form and the sequential of DDR3PHY, give DDR 3PHY module 130, receive the reading out data that DDR3 PHY module 130 is sent here simultaneously, be converted to form and the sequential of sdram controller, give the first module 110.

If it is long to write DDR3 SDRAM command process holding time, can have influence on the switching (referring to Fig. 7) of the next reading order of sdram controller.Now, adopt the two cover plug-in DDR3 SDRAM of DDR3 PHY and inner buffer binding operations, complete sdram controller access switching.

Fig. 8 is the schematic diagram in a pair of two situations of transferring.As shown in Figure 8, PHY module 130 comprises two cover DDR3 PHY unit (being designated as respectively 1# PHY, 2# PHY).1# and 2#PHY unit be external DDR3SDRAM storer (being designated as respectively 1# DDR3,2# DDR3) all.It is synchronous that the data writing of 1#, 2# bis-cover DDR3 need to be done mirror image.

PHY module 130 also comprises inner buffer.Inner buffer always writes recent write operation and requires the data that write.

Switch over operation is carried out in 1# PHY, 2# PHY bis-cover switchings in turn, and inner buffer has only just been enabled reading of data when identical with nearest write address reading address, and the sdram controller that combined access is transferred.

When sdram controller data writing, suppose that 1# PHY first writes, write inner buffer simultaneously, 2# PHY awaits orders, and prepares to accept at any time the reading order that sdram controller sends.Now if (when writing 1# PHY), sdram controller is initiated read operation order, if the address of read and write is different, by 2#PHY, has been responsible for data reading; If the address of read and write is identical, inner buffer is read the data of buffer memory before.After 1#PHY has write, the data that write 1#PHY are write to 2#PHY, to keep the data synchronous mirror of two cover PHY unit write stories.Avoided like this reading transferring unsuccessfully.The schematic diagram that Fig. 9 has illustrated to utilize two cover PHY switchings to read and write.

Normal work period, if reading address is different from nearest write address, in 1# PHY and 2# PHY, which cover just reads the free time, if two overlap all free time, selects arbitrarily a set of; If it is identical with nearest write address to read address, read inner buffer.

In an example, the second module 120 adopts state machines to control the operation of different PHY and connected DDR3SDRAM thereof.

Figure 10 is state-transition table.As shown in the figure, when the second module resets or when state machine enters idle IDLE state from other states, the second module is sent here according to the first module writes, reading order is different, and state machine is carried out to different state transitions.

1) when the first module 110 is sent write operation <WRITE n> (writing n) here (n is address), select 1#PHY to carry out write operation (in figure, mark 100) to its connected 1#DDR3, data writing deposits inner buffer (in figure, mark 101) in simultaneously;

2) when the write operation <WRITE of 1# PHY n> (writing n) does not also complete, when the first module 110 is just sent read operation here, <READ m> (reads m, be that reading address is different from writing address), start and read the connected 2# DDR3 of 2# PHY (in figure, mark 102), read switching;

3) after 2# DDR3 reads and transferred, the data of carrying out 2# DDR3 write (in figure, mark 105), and the content that writes 1# DDR3 is write to 2# DDR3, and the data writing mirror image that completes 1#, 2# DDR3 is synchronous; After having write (in figure, mark 106), enter IDLE state;

4) when the write operation <WRITE of 1# DDR3 n> (writing n) does not also complete, when the first module 110 is just sent read operation <READ n> (reading n) (being that reading address is identical with writing address) here, start and read inner buffer (in figure, mark 103), read switching; After completing and reading, the data that enter 2#DDR3 write (in figure 105), and the data writing mirror image that completes 1#, 2# bis-cover DDR3 is synchronous;

5) when completing, the write operation <WRITE of 1# DDR3 n> (writing n) also do not receive the reading order that the first module 110 is sent here, carry out 2#DDR3 data and write (in figure, mark 104), the data writing mirror image that completes 1#, 2# bis-cover DDR3 is synchronous; After having write (in figure, mark 106), enter idle <IDLE> state.

According to SDRAM access rate, the second module is selected burst transfer periodic quantity and bit wide, to tackle different demands.

In one embodiment, can increase DDR3 SDRAM memory side bit wide, reduce BL (burst transfer cycle) value, reduce data transmission period, make reading out data switching obtain the more processing time, correctly complete switching.

Figure 11 increases bit wide to reduce BL minimizing data transmission period.As shown in figure 11, for example, sdram controller data bit width 8 bit bit wides, burst-length BL=8, CL=3, clock frequency 100MHz, have the 30ns time from the read command of sdram controller to sending data back to.DDR3 SDRAM side is taked clock rate 800MHz, CL=10.If BL=8 can not complete switching in the 30ns that sdram controller requires, the bit wide of the second module and PHY module need to be increased to 16 bits, BL is reduced to 4, reduced data transmission period, just can in 30ns, complete switching, and total data bit number is identical, correctly realizes.This way is applicable to the scene that SDRAM access rate is higher.

In another embodiment, in the situation that meeting transit time, reduce the bit wide of DDR3 SDRAM storer, increase BL value, reduce costs.Figure 12 reduces the schematic diagram that bit wide increases BL.For example, sdram controller data bit width 32 bit bit wides, BL=4, CL=3, clock frequency 50MHz, from the read command of sdram controller, to sending data back to, have the 60ns time, DDR3 side is taked clock rate 400MHz, CL=6, it is that 16 bits, BL are increased to 8 that bit wide is reduced by half, add order conversion and data transmission period, in the 60ns that still can require at sdram controller, complete switching, and total data bit (bit) number is identical, correct realization, has reduced cost.This way is applicable to the scene that SDRAM access rate is lower.

Figure 13 is the schematic diagram of the SDRAM bridgt circuit of another embodiment of the present invention.As shown in figure 13, SDRAM bridgt circuit comprises the 3rd module 220 and DDR3 PHY module 130.Compare with the SDRAM bridgt circuit shown in Fig. 1, the first module 110 and the second module 120 are replaced by the 3rd module 220.In the 3rd module 220, work clock and the enabling pulse with road clock synchronous with SDRAM is provided, under the control of enabling pulse, with this work clock, gather sdram controller signal, and directly do not use SDRAM synchronous clock.The 3rd module 220 is resolved the visit order that sdram controllers are sent here, and complete and outside sdram controller between signal transmitting and receiving.Specifically, the 3rd module 220 is resolved visit order under the control of high frequency clock, and visit order and data to be written after resolving are converted to the acceptable form of DDR3 PHY and sequential.DDR3 PHY module 130 receives order and the data writing that the 3rd module 220 is sent here, gives outside DDR3 SDRAM storer; Receive the data that read from outside DDR3 SDRAM storer simultaneously, send to the 3rd module 220.

The present invention is except the bridging method of the above-mentioned SDRAM switching DDR3 SDRAM enumerating, in the situation that meeting transit time, be equally applicable to SDRAM and be forwarded to DDR2 SDRAM, DDR SDRAM and be forwarded to the bridge joint that DDR2 SDRAM, DDR SDRAM are forwarded to DDR3 SDRAM.As long as the visit order that sdram controller or DDRPHY send is changed and is had time enough to access accordingly DDR2/DDR3 SDRAM, DDR2/DDR3 PHY to DDR2/DDR3 PHY to read DDR2/DDR3 SDRAM data and can send back in the time at the CL of sdram controller/DDR PHY agreement, just can be correct realize bridge joint.

The present invention, by a kind of SDRAM bridgt circuit of design, can allow sdram controller pass through this bridgt circuit, realizes the access to DDR3 SDRAM, carries out data access; Compare the chip of changing or again developing integrated sdram controller, circuit is changed little, and the construction cycle is short, and cost is low, and well compatible with original system.

Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection domain being not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (5)

1. a SDRAM bridgt circuit, is characterized in that comprising the first module, the second module and DDR3PHY module; Wherein, the SDRAM visit order that the first module parses controller is sent here, the second module is converted to the acceptable order of DDR3PHY module SDRAM visit order, and DDR3PHY module is utilized described acceptable command access storer, and wherein storer and controller have different SDRAM types;

Described the first module is worked under controller Sui road clock control, and the second module is worked under the control of the interface clock of DDR3PHY module regulation;

Described DDR3PHY module comprises a PHY unit;

Described DDR3PHY module comprises at least one the 2nd PHY unit and buffer circuit, and described the second module selects a PHY unit to transfer from a PHY unit and described at least one the 2nd PHY unit;

The second module comprises state machine, and the second module is coordinated the work of a PHY unit and the 2nd PHY unit according to state machine;

When the second module receives the SDRAM visit order of write operation, described state machine selects a PHY unit to carry out write operation, and data writing deposits inner buffer in simultaneously; When the second module receives the SDRAM visit order of the reading address read operation different with writing address and said write operation and also do not complete, described state machine selects the 2nd PHY unit to carry out read operation;

When the second module receives the SDRAM visit order of the read operation that reading address is identical with writing address and said write operation and also do not complete, described state machine starts and reads inner buffer; And after completing and reading, the data in inner buffer write the 2nd PHY unit.

2. SDRAM bridgt circuit as claimed in claim 1, it is characterized in that the first module and the second block merging are the 3rd module, the 3rd module is resolved visit order under the control of the work clock with controller Sui road clock synchronous, and the visit order after resolving is converted to the acceptable order of DDR3PHY.

3. the SDRAM bridgt circuit as described in one of claim 1-2, is characterized in that the first module carries out command analysis by above-mentioned control signal according to truth table.

4. the SDRAM bridgt circuit as described in one of claim 1-2, is characterized in that the access rate according to SDRAM, and the second module is selected burst transfer periodic quantity and bit wide.

5. the SDRAM bridgt circuit as described in one of claim 1-2, is characterized in that controller is sdram controller or DDR PHY device, and storer is DDR2SDRAM or DDR3SDRAM.