WO2022247647A1

WO2022247647A1 - Timing controller and display device

Info

Publication number: WO2022247647A1
Application number: PCT/CN2022/092374
Authority: WO
Inventors: 刁鸿浩
Original assignee: 北京芯海视界三维科技有限公司; 视觉技术创投私人有限公司
Priority date: 2021-05-25
Filing date: 2022-05-12
Publication date: 2022-12-01
Also published as: TW202246951A; TWI802414B; CN113010020A

Abstract

The present application relates to the technical field of 3D image data processing. Disclosed is a timing controller, comprising: an MCU, a 3D module, an eyeball processing module, a receiving module and an output module, wherein the MCU is connected to a first input end of the 3D module; the eyeball processing module is connected to a second input end of the 3D module; the receiving module is connected to a third input end of the 3D module; the output module is connected to an output end of the 3D module; the MCU is configured to send control information to the 3D module; the eyeball processing module is configured to receive an image acquired by an image sensor and obtain the coordinates of eyeballs according to the image; the receiving module is configured to receive image data and send the image data to the 3D module; the 3D module is configured to generate a pixel driving signal according to the coordinates of the eyeballs, the control information and the image data; and the output module is configured to output the pixel driving signal to a display screen. By means of the timing controller provided in the present application, the user experience can be improved. Further disclosed in the present application is a display device.

Description

Timing controller and display device

This application claims the priority of the Chinese patent application filed with the China Intellectual Property Office on May 25, 2021, with the application number 2021105681095 and the title of the invention "a timing controller and display device", the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the technical field of 3D image data processing, for example, to a timing controller and a display device.

Background technique

At present, the data processing of electronic devices is usually performed by the central processing unit (CPU). Since the amount of 3D data is much larger than that of 2D data, problems such as delays and freezes will occur when the CPU processes 3D data, which will affect the user experience. .

Contents of the invention

In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is presented below. This summary is not intended to be an extensive overview or to identify key/critical elements or to delineate the scope of these embodiments, but rather serves as a prelude to the detailed description that follows.

Embodiments of the present disclosure provide a timing controller and a display device to solve the above technical problems.

In some embodiments, the timing controller includes: a microprocessor MCU, a 3D module, an eyeball processing module, a receiving module and an output module, the MCU is connected to the first input terminal of the 3D module, and the eyeball processing module is connected to the second input terminal of the 3D module. The input terminal is connected, the receiving module is connected to the third input terminal of the 3D module, and the output module is connected to the output terminal of the 3D module, wherein,

MCU configured to send control information to the 3D module;

The eyeball processing module is configured to receive the image acquired by the image sensor and obtain eyeball coordinates according to the image;

A receiving module configured to receive image data and send the image data to the 3D module;

A 3D module configured to generate pixel driving signals according to eyeball coordinates, control information and image data;

The output module is configured to output the pixel driving signal to the display screen.

In some embodiments, a display device includes a timing controller as described above.

The timing controller and display device provided by the embodiments of the present disclosure can achieve the following technical effects:

To a certain extent, the user experience is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the application.

Description of drawings

At least one embodiment is exemplified by the corresponding drawings, and these exemplifications and drawings do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. does not constitute a proportional limit, and where:

FIG. 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure;

Fig. 2 shows a schematic structural diagram of an eyeball processing module in an embodiment of the present disclosure;

FIG. 3 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 4 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 5 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 6 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 7 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 8 shows a schematic structural diagram of a display device in an embodiment of the present disclosure.

Detailed ways

In order to understand the characteristics and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present disclosure. In the following technical description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, at least one embodiment can be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawings.

Usually, the display (or display panel) will have a timing controller (Timing Controller, TCON), also called TCON board or screen driver board, which is used to receive red, green and blue (RGB) data signals, clock signals and control signals, etc. Input signals, and then convert these input signals into signals capable of driving the display.

An embodiment of the present disclosure provides a timing controller, which will be described below.

FIG. 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure.

As shown in the figure, the timing controller 700 may include: a microprocessor (MCU, Microcontroller Unit) 10, an eyeball processing module 20, a three-dimensional 3D module 30, a receiving module 40 and an output module 50, the first of the MCU 10 and the 3D module 30 One input end is connected, the eyeball processing module 20 is connected with the second input end of the 3D module 30, the receiving module 40 is connected with the third input end of the 3D module 30, and the output module 50 is connected with the output end of the 3D module 30, wherein,

MCU 10 is configured to send control information to the 3D module;

The eyeball processing module 20 is configured to receive the image acquired by the image sensor and obtain eyeball coordinates according to the image;

The receiving module 40 is configured to receive image data and send the image data to the 3D module;

The 3D module 30 is configured to generate a pixel driving signal according to eyeball coordinates, control information and image data;

The output module 50 is configured to output the pixel driving signal to the display screen.

The embodiment of the present disclosure improves the existing timing controller, adding a hardware unit for computing image data and a hardware unit for computing eyeball coordinates in the timing controller. The CPU does not need to participate in any computing of image data, and the image data The operation of the operation and the operation of the eye coordinates are all realized by a special hardware device such as a timing controller, which improves the efficiency to a certain extent. Using the timing controller provided by the embodiment of the present disclosure for 3D display can increase the processing rate, reduce the delay, and improve User viewing experience.

In some embodiments, the 3D module 30 can include two input pins bin and one output pin bin, the output pin of the MCU 10 can be connected with an input pin of the 3D module 30, and the output pin of the receiving module 40 can be It is connected with another input pin of the 3D module 30 , and the input pin of the output module 50 is connected with the output pin of the 3D module 30 .

In some embodiments, the input terminal of the timing controller 700 may be connected to the application processor AP, and the AP provides image data. Optionally, the image data may be a video picture acquired by an image sensor, or a virtual video picture generated by the AP.

In some embodiments, the image data may include left eye image data and right eye image data.

In some embodiments, the eyeball coordinates may include coordinates x and y in the horizontal and vertical directions in the screen coordinate system, and may also include a depth value z from the eyeball to the screen. The eyeball coordinates may include coordinates of the left eye and coordinates of the right eye.

In some embodiments, the output module 50 may transmit signals in a peer-to-peer (P2P, Peer-to-peer) manner.

In some embodiments, the 3D module 30, the eyeball processing module 20, and the output module 50 can be connected to the MCU 10 through a bus. Optionally, the bus may be an AXI (Advanced extensible Interface) bus or the like.

Fig. 2 shows a schematic structural diagram of an eyeball processing module in an embodiment of the present disclosure.

As shown in the figure, in some embodiments, the eyeball processing module 20 may include an image receiving unit 201, an eyeball processing unit 202 and an image sending unit 203,

An image receiving unit 201, connected to the image sensor, configured to receive an image provided by the image sensor;

The eyeball processing unit 202 is configured to acquire the image provided by the image sensor and calculate eyeball coordinates;

The image sending unit 203 is configured to send the eyeball coordinates to the 3D module 30 .

In some embodiments, the image sensor may be a sensing device such as a camera. The timing controller TCON can be connected with the image sensor, receives the image taken by the image sensor through the image receiving unit 201, then processes the image through the eyeball processing unit 202, calculates the position of the eyeball in the image (eyeball coordinates), and then transmits the image through the image The unit 203 sends the eyeball coordinates to the 3D module 30 .

In some embodiments, the image sensor can acquire images including faces (for example: human faces), and the eyeball processing unit 203 can calculate and process the images including faces to obtain eyeball coordinates. Wherein, the calculation and processing of the image by the eyeball processing unit 203 can be realized by using an existing eyeball coordinate extraction algorithm.

In some embodiments, the timing controller can be connected with one image sensor, which captures images including faces; or, the timing controller can be connected with two or more image sensors, and each image sensor's shooting The ranges can be different, and the eyeball processing unit 202 can calculate and process images provided by different image sensors to obtain eyeball coordinates.

FIG. 3 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 includes a processing unit 100 and a first interface 101, the first interface 101 is connected to a memory 104, and the memory 104 pre-stores optical data;

The processing unit 100 is further configured to send a read command to the first interface 101;

The first interface 101 is configured to acquire optical data from the memory 104 according to a read command, and send it to the 3D module 30 .

In some embodiments, the processing unit 100 may send a read command to the first interface 101 after each power-on.

In some embodiments, the optical data may include a correspondence between pixels (each pixel may include multiple sub-pixels, and each sub-pixel may also include multiple compound sub-pixels, etc.) on the display screen and the grating. Optionally, the grating may include a lenticular grating or the like. The corresponding relationship may include the number of compound sub-pixels in each grating, the horizontal position arrangement, the vertical position arrangement and the like.

In some embodiments, optical data may be transmitted from an application processor AP.

In some embodiments, the first interface 101 may be a Serial Peripheral Interface (SPI, Serial Peripheral Interface).

In some embodiments, the memory 104 may be a non-volatile storage medium Flash. Optionally, when the first interface 101 is an SPI interface, the memory 104 may be a SPI Flash storage device.

FIG. 4 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 also includes a second interface 102,

The second interface 102 is configured to receive optical data;

The processing unit 100 is further configured to send a write command to the first interface 101;

The first interface 101 is further configured to acquire optical data according to a write command and write the optical data into the memory 104 .

FIG. 5 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the timing controller 700 may also include an image transmission interface unit 60 connected to the input end of the receiving module 30,

The image transmission interface unit 60 may be configured to receive the image data in the first protocol format, convert it into image data in the second protocol format, and output it to the receiving module 40 .

In some embodiments, the image transmission interface unit 60 may be a Mobile Industry Processor Interface (MIPI, Mobile Industry Processor Interface). Optionally, it may be a MIPI display interface (DSI, Display Serial Interface).

FIG. 6 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 may also include a third interface 103,

The third interface 103 is configured to send initialization data to the image transmission interface unit 60;

The image transmission interface unit 60 is configured to perform initialization according to initialization data.

In some embodiments, the third interface 103 may be an IIC interface.

In some embodiments, the image transmission interface unit 60 may further include an initialization interface configured to receive initialization data.

In some embodiments, the initialization interface of the image transmission interface unit 60 may be an IIC interface configured to receive initialization data. Optionally, the IIC interface of the image transmission interface unit 60 can be an IIC slave interface IIC-s, the third interface 103 can be an IIC master master interface IIC-m, and the second interface 102 can be a slave interface IIC- s.

In some embodiments, the receiving module 40 may also be configured to rearrange the pixels of the image data before sending the image data to the 3D module 30 .

In some embodiments, the MCU 10 may be configured to send mode control information to the 3D module 30, and the 3D module 30 may be configured to output a pixel driving signal in a corresponding mode according to eyeball coordinates, mode control information, and image data.

In some embodiments, the mode control information may include at least one of the following: 2D mode, calibration mode, 3D mode;

The 3D module 30 can be configured to output the received image data after pixel expansion according to the number of composite sub-pixels of each pixel in the 2D mode; output the pre-stored standard image in the calibration mode; and output the received image data in the 3D mode The obtained image data is output after determining the pixel arrangement of the left and right eyes according to the eyeball coordinates and optical data.

FIG. 7 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the 3D module 30 may include a register 301, a selection unit 302, a standard image unit 303, and a 3D algorithm unit 304, and the register 301 is connected to the selection unit 302 and the 3D algorithm unit 304 respectively,

The selection unit 302 is configured to receive the mode control information of the register 301 to select and connect to the standard graphics unit 303 or the 3D algorithm unit 304;

The standard map unit 303 is configured to output a pre-stored standard map in the calibration mode;

The 3D algorithm unit 304 is configured to output the received image data after determining the left and right eye pixel arrangement according to the eye coordinates and optical data in 3D mode, and output the received image data after pixel expansion in 2D mode.

In some embodiments, the processing unit 100 can configure the value of the 3D mode in the bus configuration register 301 as 1, which means that the 3D module 30 needs to work in the 3D mode. When the 3D module 30 determines that the value of the 3D mode is 1, the 3D algorithm unit 304 3D calculation of image data will be performed. Optionally, specific 3D operations may be implemented using existing 3D algorithms.

In some embodiments, the processing unit 100 can configure the value of the calibration mode in the bus configuration register 301 to be 1, while the value of the 3D mode is 0, which means that the 3D module 30 needs to work in the calibration mode, and the calibration map unit 303 determines the value of the calibration mode. When the value is 1, the pre-stored standard map is output.

In some embodiments, the processing unit 100 can configure the value of the calibration mode in the bus configuration register 301 to be 0, while the value of the 3D mode is 0, which means that the 3D module 30 needs to work in the 2D mode, and the 3D algorithm unit 304 determines the value of the calibration mode. When the value is 0 and the value of the 3D mode is 0, each pixel of the image data is copied and output to the output module 50 .

In some embodiments, in the 2D mode, the 3D algorithm unit 304 can copy each pixel of the image data N times, and output it to the output module 50 . The number of duplications is related to the number of composite sub-pixels included in each sub-pixel.

In some embodiments, the selection unit 302 may be implemented using a switch circuit. Optionally, the selection unit 302 may include three input pins A, B, and C, wherein, the input pin A is a 3D mode, the input pin B is a calibration mode, the input pin C is a 2D mode, and the three pins The high and low levels of the output pin can determine which module is turned on. For example: pin A inputs high level, pin B and pin C low level, selection unit 302 and 3D algorithm unit 304 conduction (3D mode); pin B inputs high level, pin A and pin C low level, selection unit 302 and standard image unit 303 conduction (calibration mode); pin C input high level, pin A and pin B low level, selection unit 302 and 3D algorithm unit 304 conduction ( 2D mode).

In some embodiments, the processing of the 2D mode can also be implemented by a functional unit independent of the 3D algorithm unit 304 .

In some embodiments, each functional module and unit in the embodiments of the present disclosure may be implemented by means of hardware circuits and the like.

An embodiment of the present disclosure also provides a display device, including the above timing controller 700 .

As shown in the figure, in some embodiments, the display device may include a timing controller 700, and optionally, may also include a display screen 800, and the timing controller 700 may output pixel driving signals to the display screen 800 to drive the display of the display screen. .

The timing controller and display device provided by the embodiments of the present disclosure can be used in liquid crystal display (LCD, Liquid Crystal Display), light-emitting diode (LED, Light-Emitting Diode) and other devices.

The timing controller and the display device provided by the embodiments of the present disclosure may be used in 2D, 3D and other display devices.

The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, procedural, and other changes. The examples merely represent possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The scope of embodiments of the present disclosure includes the full scope of the claims, and all available equivalents of the claims. When used in the present application, although the terms 'first', 'second', etc. may be used in the present application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be called a second element, and likewise, a second element could be called a first element, without changing the meaning of the description, as long as all occurrences of "first element" are renamed consistently and all occurrences of "Second component" can be renamed consistently. The first element and the second element are both elements, but may not be the same element. Also, the terms used in the present application are used to describe the embodiments only and are not used to limit the claims. As used in the examples and description of the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well unless the context clearly indicates otherwise . Similarly, the term "and/or" as used in this application is meant to include any and all possible combinations of one or more of the associated listed ones. Additionally, when used in this application, the term "comprise" and its variants "comprises" and/or comprising (comprising) etc. refer to stated features, integers, steps, operations, elements, and/or The presence of a component does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groupings of these. Without further limitations, an element defined by the statement "comprising a ..." does not preclude the presence of additional identical elements in the process, method or apparatus comprising the element. Herein, what each embodiment focuses on may be the difference from other embodiments, and the same and similar parts of the various embodiments may refer to each other. For the method, product, etc. disclosed in the embodiment, if it corresponds to the method part disclosed in the embodiment, then the relevant part can refer to the description of the method part.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software may depend on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for each specific application, but such implementation should not be considered as exceeding the scope of the disclosed embodiments. Those skilled in the art can clearly understand that for the convenience and brevity of description, the working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, and details are not repeated here.

In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of units may only be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integrate into another system, or some features may be ignored, or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms. A unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

In the drawings, the width, length, thickness, etc. of structures such as elements or layers may be exaggerated in consideration of clarity and descriptiveness. When a structure such as an element or layer is said to be "disposed on" (or "mounted on", "laid on", "attached to", "coated on" and similar descriptions) another element or layer is "over" or " When "on", the structure such as the element or layer may be directly "arranged on" or "on" the other element or layer mentioned above, or there may be an intermediate element or layer between the above-mentioned another element or layer, etc. structure, even partially embedded in another element or layer described above.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the disclosure. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or portion of code that includes at least one executable instruction for implementing a specified logical function . In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than that disclosed in the description, and sometimes there is no specific agreement between different operations or steps. order. For example, two consecutive operations or steps may, in fact, be performed substantially concurrently, or they may sometimes be performed in the reverse order, depending upon the functionality involved. Each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by dedicated hardware implemented in combination with computer instructions.

Claims

A timing controller, comprising: a microprocessor MCU, a 3D module, an eyeball processing module, a receiving module and an output module, the MCU is connected to the first input of the 3D module, the eyeball processing module is connected to the 3D The second input terminal of the module is connected, the receiving module is connected to the third input terminal of the 3D module, and the output module is connected to the output terminal of the 3D module, wherein,

The MCU is configured to send control information to the 3D module;

The eyeball processing module is configured to receive an image acquired by an image sensor and obtain eyeball coordinates according to the image;

The receiving module is configured to receive image data and send the image data to the 3D module;

The 3D module is configured to generate a pixel driving signal according to the eye coordinates, control information and the image data;

The output module is configured to output the pixel driving signal to a display screen.
The timing controller according to claim 1, wherein the eyeball processing module comprises an image receiving unit, an eyeball processing unit and an image sending unit,

The image receiving unit is connected to the image sensor and is configured to receive an image provided by the image sensor;

The eyeball processing unit is configured to acquire the image provided by the image sensor and calculate eyeball coordinates;

The image sending unit is configured to send the eyeball coordinates to the 3D module.
The timing controller according to claim 1, wherein the MCU includes a processing unit and a first interface, the first interface is connected to a memory, and the memory pre-stores optical data;

The processing unit is further configured to send a read command to the first interface;

The first interface is configured to obtain the optical data from the memory according to the read command, and send it to the 3D module.
The timing controller according to claim 3, wherein the MCU further comprises a second interface,

the second interface configured to receive optical data;

The processing unit is further configured to send a write command to the first interface;

The first interface is further configured to acquire the optical data according to the write command and write the optical data into the memory.
The timing controller according to claim 3, further comprising an image transmission interface unit connected to the input end of the receiving module,

The image transmission interface unit is configured to receive image data in the first protocol format, convert it into image data in the second protocol format, and output it to the receiving module.
The timing controller according to claim 5, wherein the MCU further comprises a third interface,

The third interface is configured to send initialization data to the image transmission interface unit;

The image transmission interface unit is configured to perform initialization according to the initialization data.
The timing controller according to claim 1, wherein the MCU is configured to send mode control information to the 3D module, and the 3D module is further configured to The above image data outputs the pixel driving signal in the corresponding mode.
The timing controller according to claim 7, wherein the mode control information includes at least one of the following: 2D mode, calibration mode, 3D mode;

The 3D module is configured to output the received image data after pixel expansion according to the number of composite sub-pixels of each pixel in the 2D mode; output the pre-stored standard image in the calibration mode; and output the received image data in the 3D mode The image data of the left and right eyes are determined according to the eyeball coordinates and optical data and then output.
The timing controller according to claim 8, wherein the 3D module includes a register, a selection unit, a standard graph unit, and a 3D algorithm unit, and the registers are respectively connected to the selection unit and the 3D algorithm unit,

The selection unit is configured to receive the mode control information of the register and select to connect with the standard graphics unit or the 3D algorithm unit;

The standard map unit is configured to output a pre-stored standard map in calibration mode;

The 3D algorithm unit is configured to output the received image data after determining the pixel arrangement of the left and right eyes according to eyeball coordinates and optical data in 3D mode, and output the received image data after pixel expansion in 2D mode.
A display device, comprising the timing controller as claimed in any one of claims 1-9.