WO2022247646A1

WO2022247646A1 - Timing controllers and display device

Info

Publication number: WO2022247646A1
Application number: PCT/CN2022/092372
Authority: WO
Inventors: 刁鸿浩
Original assignee: 北京芯海视界三维科技有限公司; 视觉技术创投私人有限公司
Priority date: 2021-05-25
Filing date: 2022-05-12
Publication date: 2022-12-01
Also published as: TW202246950A; CN113012621A

Abstract

A timing controller and a display device. The timing controller comprises: an FPGA apparatus (200) and a bridging apparatus (100), wherein the bridging apparatus (100) is configured to receive image data, perform protocol conversion on same, and then send the image data to the FPGA apparatus (200); and the FPGA apparatus (200) is configured to receive eyeball coordinates and the image data, and output a pixel driving signal to a display screen according to the eyeball coordinates and the image data. Another timing controller, comprising: an FPGA apparatus (200) and a bridging apparatus (100), wherein the bridging apparatus (100) is configured to receive image data, perform protocol conversion on same and then send the image data to the FPGA apparatus (200); and the FPGA apparatus (200) is configured to receive an image that comprises eyes and the image data, obtain eyeball coordinates according to the image that comprises the eyes, and output a pixel driving signal to a display screen according to the eyeball coordinates and the image data.

Description

Timing controller and display device

This application claims the priority of a Chinese patent application filed with the China Intellectual Property Office on May 25, 2021, with application number 2021105681108, and the title of the invention is "Sequence Controller and Display Device", the entire contents of which are incorporated by reference in this application .

technical field

The present application relates to the technical field of 3D image data processing, for example, it relates to a timing controller and a display device.

Background technique

At present, the data processing of electronic devices is usually performed by the central processing unit (CPU). Since the amount of 3D data is much larger than that of 2D data, problems such as delays and freezes will occur when the CPU processes 3D data, which will affect the user experience. .

Contents of the invention

In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is presented below. This summary is not intended to be an extensive overview or to identify key/critical elements or to delineate the scope of these embodiments, but rather serves as a prelude to the detailed description that follows.

Embodiments of the present disclosure provide a timing controller and a display device to solve the above technical problems.

In some embodiments, the timing controller includes: an FPGA device and a bridge device,

The bridging device is configured to receive the image data and send the image data to the FPGA device after performing protocol conversion;

The FPGA device is configured to receive eyeball coordinates and image data, and output pixel driving signals to the display screen according to the eyeball coordinates and image data.

The FPGA device is configured to receive images including eyes and image data, obtain eye coordinates according to the images including eyes, and output pixel driving signals to the display screen according to the eye coordinates and image data.

In some embodiments, the display device includes: the timing controller mentioned above.

The timing controller and display device provided by the embodiments of the present disclosure can achieve the following technical effects:

To a certain extent, the user experience is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the application.

Description of drawings

At least one embodiment is exemplified by the corresponding drawings, and these exemplifications and drawings do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. does not constitute a proportional limit, and where:

FIG. 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 2 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 3 shows a schematic structural diagram of a bridging device in an embodiment of the present disclosure;

FIG. 4 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 5 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure;

FIG. 6 shows a schematic structural diagram of a display device in an embodiment of the present disclosure.

Detailed ways

In order to understand the characteristics and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present disclosure. In the following technical description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, at least one embodiment can be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawings.

Usually, the display (or display panel) will have a timing controller (Timing Controller, TCON), also called TCON board or screen driver board, which is used to receive red, green and blue (RGB) data signals, clock signals and control signals, etc. Input signals, and then convert these input signals into signals capable of driving the display.

An embodiment of the present disclosure provides a timing controller, which will be described below.

FIG. 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure.

As shown in the figure, the timing controller may include: a bridge device 100 and a Field Programmable Gate Array (FPGA, Field Programmable Gate Array) device 200,

The bridge device 100 is configured to receive the image data and send the image data to the FPGA device 200 after performing protocol conversion;

The FPGA device 200 is configured to receive eyeball coordinates and image data, and output pixel driving signals to the display screen according to the eyeball coordinates and image data.

The embodiment of the present disclosure improves the existing timing controller. In the timing controller, a hardware unit for 3D image data processing is realized through FPGA design, and the image data is obtained after bridging with the FPGA through a bridging device, and the FPGA can complete the 3D image. For data processing, the CPU does not need to participate in any calculation of image data. The calculation of image data can be realized through a dedicated hardware device such as a timing controller, which improves efficiency to a certain extent. The timing controller provided by the embodiment of the present disclosure is used for 3D The display can increase the processing rate, reduce the delay, and improve the user's viewing experience.

In some embodiments, the bridge device 100 can be a bridge chip or a conversion chip, which can usually convert one signal format into another signal format, for example: the Mobile Industry Processor Interface (MIPI, Mobile Industry Processor) of the original image data Interface) signal into low-voltage differential signal (LVDS, Low-Voltage Differential Signaling).

In some embodiments, the bridge device 100 may receive the image data sent by the application processor AP, and may also receive the image data acquired by the image sensor. The image data sent by the AP may be virtual video data generated by the AP, and the image data acquired by the image sensor may be real video data captured by the image sensor in real time.

In some embodiments, the image data may include left eye image data and right eye image data.

FIG. 2 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure.

As shown in the figure, in some embodiments, the FPGA device 200 may include a microprocessor MCU 210, a 3D module 220, a receiving module 230 and an output module 240, the MCU 210 is connected to the first input of the 3D module 220, and the receiving module 230 It is connected to the second input terminal of the 3D module 220, and the output terminal of the 3D module 220 is connected to the output module 240, wherein,

The MCU 210 can be configured to receive the eye coordinates and send the eye coordinates and control information to the 3D module 220;

The receiving module 230 may be configured to receive image data and send the image data to the 3D module 220;

The 3D module 220 may be configured to output pixel driving signals according to eyeball coordinates, control information and image data.

In some embodiments, the 3D module 220 may include two input pin bins and one output pin bin, the output pin of the MCU 210 may be connected to one input pin of the 3D module 220, and the output pin of the receiving module 230 may be connected to The other input pin of the 3D module 220 is connected, and the input pin of the output module 240 is connected to the output pin of the 3D module 220 .

In some embodiments, the MCU 210 may be connected to the image sensor, or to the processing unit of the image sensor, to obtain the user's eye coordinates. Optionally, the eyeball coordinates may include coordinates x and y in the horizontal and vertical directions in the screen coordinate system, and may also include a depth value z from the eyeball to the screen. The eyeball coordinates may include coordinates of the left eye and coordinates of the right eye.

In some embodiments, the output module 240 may transmit signals in a peer-to-peer (P2P, Peer-to-peer) manner.

In some embodiments, the 3D module 220 and the output module 240 can be connected to the MCU 210 through a bus. Optionally, the bus may be an AXI (Advanced eXtensible Interface) bus or the like.

In some embodiments, the bridge device 100 can be connected to the receiving module 230 and configured to receive the image data and send the image data to the receiving module 230 after performing protocol conversion.

In some embodiments, the bridge device 100 may include an output pin connected to an input pin of the receiving module 230 of the FPGA.

In some embodiments, the MCU 210 may also be configured to send initialization data to the bridge device 100; the bridge device 100 may also be configured to perform initialization according to the initialization data.

In some embodiments, the bridge device 100 may include an initialization input pin connected to an output pin of the MCU 210 of the FPGA for receiving initialization data sent by the MCU 210.

In some embodiments, the initialization input pin of the bridge device 100 may adopt an inter-integrated circuit (IIC, Inter-Integrated Circuit) interface. The interface used by the MCU 210 to send initialization data to the bridge device 100 can also be an IIC interface. Optionally, the interface used by the MCU 210 to send initialization data to the bridge device 100 may be an IIC master interface, and the initialization input pin of the bridge device 100 may be an IIC slave interface.

In some embodiments, the MCU 210 can also be configured to receive optical data and send the optical data to the 3D module 220, and the 3D module 220 can be configured to output pixel driving signals according to eye coordinates, control information, optical data, and image data.

In some embodiments, the MCU 210 can send optical data to the 3D module 220 after each power-on.

In some embodiments, the optical data may include a correspondence between pixels (each pixel may include multiple sub-pixels, and each sub-pixel may also include multiple compound sub-pixels, etc.) on the display screen and the grating. Optionally, the grating may include a lenticular grating or the like. The corresponding relationship may include the number of compound sub-pixels in each grating, the horizontal position arrangement, the vertical position arrangement and the like.

In some embodiments, optical data may be transmitted from an application processor AP.

In some embodiments, the control information may include control information in at least one of the following modes: 2D mode, 3D mode;

The 3D module 220 is configured to expand the image data according to the number of composite sub-pixels of each pixel before outputting in 2D mode, and output the driving signal of the composite sub-pixels of each pixel according to eyeball coordinates and image data in 3D mode.

In some embodiments, in the 2D mode, the 3D module 220 can copy each pixel of the image data N times and output it to the output module 240 . The number of duplications is related to the number of composite sub-pixels included in each sub-pixel. For example: each pixel includes three sub-pixels, each sub-pixel includes 4 composite sub-pixels, in 2D mode, each sub-pixel of the image data can be copied 4 times and then output to the output module 240 .

Fig. 3 shows a schematic structural diagram of a bridging device in an embodiment of the present disclosure.

As shown in the figure, in some embodiments, the bridging device 100 may include a first protocol input unit 110, a protocol processing unit 120 and a second protocol output unit 130,

The first protocol input unit 110 is configured to receive image data in a first protocol format;

The protocol processing unit 120 is configured to convert the image data in the first protocol format into the second protocol format;

The second protocol output unit 130 is configured to transmit the image data in the second protocol format to the FPGA device.

In some embodiments, the first protocol input unit 101 may be a MIPI interface unit. Optionally, an interface unit can be displayed for MIPI DSI.

In some embodiments, the second protocol output unit 103 may be an LVDS interface unit.

In some embodiments, the bridging device 100 may further include a first rearrangement unit configured to rearrange the pixels of the image data, for example: rearrange the pixel arrangement of the original image data that does not conform to the preset rules to conform to Pixel arrangement of preset rules.

In some embodiments, the receiving module 230 may further include a second rearrangement unit configured to rearrange the pixels of the image data, for example: rearrange the pixel arrangement sent by the bridge device 100 to conform to preset rules Pixel arrangement.

In some embodiments, the rearrangement of pixels may be as follows: the bridge device 100 rearranges the image data into a clock including N RGB data, and the receiving module 230 rearranges a clock including N RGB data into a clock including M RGB data Data, N and M are not equal. Optionally, N>M.

In some embodiments, each functional module and unit in the embodiments of the present disclosure may be implemented by means of hardware circuits and the like.

The embodiment of the present disclosure also provides a timing controller, which will be described below.

FIG. 4 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure.

The FPGA device 200 is configured to receive images including eyes and image data, obtain eye coordinates according to the images including eyes, and output pixel driving signals to the display screen according to the eye coordinates and image data.

FIG. 5 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, FPGA device 200 can include microprocessor MCU 210, 3D module 220, eyeball processing module 250, receiving module 230 and output module 240, MCU 210 and eyeball processing module 250 are all connected with 3D module 220 is connected to the first input end, the receiving module 230 is connected to the second input end of the 3D module 220, and the output end of the 3D module 220 is connected to the output module 240, wherein,

The MCU 210 is configured to send control information to the 3D module 220;

The eyeball processing module 250 is configured to receive the image acquired by the camera device and obtain eyeball coordinates according to the image, and send the eyeball coordinates to the 3D module 220;

The receiving module 230 is configured to receive image data and send the image data to the 3D module 220;

The 3D module 220 is configured to output pixel driving signals according to eye coordinates, control information and image data.

The embodiment of the present disclosure improves the existing timing controller. In the timing controller, the hardware unit for 3D image data processing and eyeball processing is realized through FPGA design, and the image data is obtained after bridging with the FPGA through a bridge device, and the FPGA can be used. To complete the eyeball processing and 3D image data processing, the CPU does not need to participate in any calculation of image data, and the calculation of image data can be realized through a dedicated hardware device such as a timing controller, which improves efficiency to a certain extent. The embodiment of the present disclosure provides The 3D display of the advanced timing controller can increase the processing rate, reduce the delay, and improve the user's viewing experience.

In some embodiments, the MCU 210 can also be configured to send initialization data to the bridge device 100; the bridge device 100 is also configured to perform initialization according to the initialization data.

In some embodiments, the MCU 210 can also be configured to receive optical data and send the optical data to the 3D module 220, and the 3D module 220 is configured to output pixel driving signals according to eye coordinates, control information, optical data, and image data.

In some embodiments, the bridging device 100 may include a first protocol input unit 101, a protocol processing unit 102 and a second protocol output unit 103,

The first protocol input unit 101 is configured to receive image data in a first protocol format;

The protocol processing unit 102 is configured to convert the image data in the first protocol format into the second protocol format;

The second protocol output unit 103 is configured to transmit the image data in the second protocol format to the FPGA device.

An embodiment of the present disclosure also provides a display device, including the timing controller described above.

As shown in the figure, in some embodiments, the display device may include a timing controller, and optionally, may also include a display screen, and the timing controller may output pixel driving signals to the display screen to drive display on the display screen.

The timing controller and display device provided by the embodiments of the present disclosure can be used in liquid crystal display (LCD, Liquid Crystal Display), light-emitting diode (LED, Light-Emitting Diode) and other devices.

The timing controller and the display device provided by the embodiments of the present disclosure may be used in 2D, 3D and other display devices.

In some embodiments, the display device may further include other components for supporting normal operation of the display device, such as at least one of components such as a communication interface, a frame, and a control circuit.

The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, procedural, and other changes. The examples merely represent possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The scope of embodiments of the present disclosure includes the full scope of the claims, and all available equivalents of the claims. When used in the present application, although the terms 'first', 'second', etc. may be used in the present application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be called a second element, and likewise, a second element could be called a first element, without changing the meaning of the description, as long as all occurrences of "first element" are renamed consistently and all occurrences of "Second component" can be renamed consistently. The first element and the second element are both elements, but may not be the same element. Also, the terms used in the present application are used to describe the embodiments only and are not used to limit the claims. As used in the examples and description of the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well unless the context clearly indicates otherwise . Similarly, the term "and/or" as used in this application is meant to include any and all possible combinations of one or more of the associated listed ones. Additionally, when used in this application, the term "comprise" and its variants "comprises" and/or comprising (comprising) etc. refer to stated features, integers, steps, operations, elements, and/or The presence of a component does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groupings of these. Without further limitations, an element defined by the statement "comprising a ..." does not preclude the presence of additional identical elements in the process, method or apparatus comprising the element. Herein, what each embodiment focuses on may be the difference from other embodiments, and the same and similar parts of the various embodiments may refer to each other. For the method, product, etc. disclosed in the embodiment, if it corresponds to the method part disclosed in the embodiment, then the relevant part can refer to the description of the method part.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software may depend on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for each particular application, but such implementation should not be considered as exceeding the scope of the disclosed embodiments. Those skilled in the art can clearly understand that for the convenience and brevity of description, the working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, and details are not repeated here.

In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of units may only be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integrate into another system, or some features may be ignored, or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms. A unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

In the drawings, the width, length, thickness, etc. of structures such as elements or layers may be exaggerated in consideration of clarity and descriptiveness. When a structure such as an element or layer is said to be "disposed on" (or "mounted on", "laid on", "attached to", "coated on" and similar descriptions) another element or layer is "over" or " When "on", the structure such as the element or layer may be directly "arranged on" or "on" the other element or layer mentioned above, or there may be an intermediate element or layer between the above-mentioned another element or layer, etc. structure, even partially embedded in another element or layer described above.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the disclosure. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or portion of code that includes at least one executable instruction for implementing a specified logical function . In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than that disclosed in the description, and sometimes there is no specific agreement between different operations or steps. order. For example, two consecutive operations or steps may, in fact, be performed substantially concurrently, or they may sometimes be performed in the reverse order, depending upon the functionality involved. Each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by dedicated hardware implemented in combination with computer instructions.

Claims

A timing controller, comprising: Field Programmable Gate Array FPGA device and bridge device,

The bridging device is configured to receive image data and send the image data to the FPGA device after performing protocol conversion;

The FPGA device is configured to receive eyeball coordinates and image data, and output pixel driving signals to the display screen according to the eyeball coordinates and image data.
The timing controller according to claim 1, wherein the FPGA device comprises a microprocessor MCU, a 3D module, a receiving module and an output module, the MCU is connected to the first input of the 3D module, and the receiving The module is connected to the second input terminal of the 3D module, and the output terminal of the 3D module is connected to the output module, wherein,

The MCU is configured to receive eye coordinates and send the eye coordinates and control information to the 3D module;

The receiving module is configured to receive image data and send the image data to the 3D module;

The 3D module is configured to output a pixel driving signal according to the eyeball coordinates, control information and the image data.
A timing controller, comprising: Field Programmable Gate Array FPGA device and bridge device,

The bridging device is configured to receive image data and send the image data to the FPGA device after performing protocol conversion;

The FPGA device is configured to receive images including eyes and image data, obtain eye coordinates according to the images including eyes, and output pixel driving signals to a display screen according to the eye coordinates and the image data.
The timing controller according to claim 3, wherein the FPGA device comprises a microprocessor MCU, a 3D module, an eyeball processing module, a receiving module and an output module, and the MCU and the eyeball processing module are all connected with the 3D The first input end of the module is connected, the receiving module is connected to the second input end of the 3D module, and the output end of the 3D module is connected to the output module, wherein,

The MCU is configured to send control information to the 3D module;

The eyeball processing module is configured to receive the image acquired by the camera device, obtain eyeball coordinates according to the image, and send the eyeball coordinates to the 3D module;

The receiving module is configured to receive image data and send the image data to the 3D module;

The 3D module is configured to output a pixel driving signal according to the eyeball coordinates, control information and the image data.
The timing controller according to claim 2 or 4, wherein the bridging device is connected to the receiving module and is configured to receive image data and send the image data to the receiving module after performing protocol conversion.
The timing controller according to claim 2 or 4, wherein the MCU is further configured to send initialization data to the bridge device; and the bridge device is further configured to perform initialization according to the initialization data.
The timing controller according to claim 2 or 4, wherein the MCU is further configured to receive optical data and send the optical data to the 3D module, and the 3D module is configured to , control information, optical data, and the image data output pixel driving signals.
The timing controller according to claim 2 or 4, wherein the control information includes control information of at least one of the following modes: 2D mode, 3D mode;

The 3D module is configured to output the image data after pixel expansion according to the number of composite sub-pixels of each pixel in 2D mode, and output each pixel in 3D mode according to the eyeball coordinates and the image data The driving signal of the composite sub-pixel.
The timing controller according to claim 1 or 3, wherein the bridging device comprises a first protocol input unit, a protocol processing unit and a second protocol output unit,

The first protocol input unit is configured to receive image data in a first protocol format;

The protocol processing unit is configured to convert the image data in the first protocol format into a second protocol format;

The second protocol output unit is configured to transmit the image data in the second protocol format to the FPGA device.
A display device, comprising the timing controller as claimed in any one of claims 1-9.