CN102164251B - Signal processing circuit and signal processing method for image sensor - Google Patents
Signal processing circuit and signal processing method for image sensor Download PDFInfo
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- CN102164251B CN102164251B CN201110137713.9A CN201110137713A CN102164251B CN 102164251 B CN102164251 B CN 102164251B CN 201110137713 A CN201110137713 A CN 201110137713A CN 102164251 B CN102164251 B CN 102164251B
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Abstract
The invention relates to a signal processing circuit and a signal processing method for an image sensor. The signal processing circuit comprises at least two image capacitors, at least two reset capacitors, a first switching unit and a second switching unit, wherein the at least two image capacitors are configured to controllably acquire an image signal of at least one pixel; the at least two reset capacitors are configured to controllably acquire a reset signal of the at least one pixel; the first switching unit is configured to couple at least one of the at least two image capacitors to the at least one pixel in response to a control signal to acquire the image signal and make the at least two image capacitors share the acquired image signal; and the second switching unit is configured to couple at least one of the at least two reset capacitors to the at least one pixel in response to the control signal to acquire the reset signal and make the at least two reset capacitors share the acquired reset signal.
Description
Technical field
The present invention relates to image sensor technologies field, more specifically, the present invention relates to a kind of signal processing circuit and signal processing method of imageing sensor.
Background technology
Along with the development of semiconductor technology, imageing sensor has been widely used in the various fields that need to carry out digital imagery, in electronic products such as digital camera, Digital Video.According to the difference of photoelectric conversion mode, imageing sensor can be divided into two classes conventionally: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, cmos image sensor has the advantages such as volume is little, low in energy consumption, production cost is low, therefore, cmos image sensor is easy to be integrated in mancarried electronic aids such as mobile phone, notebook computer, panel computer, as providing the camera module of digital imagery function to use.
Along with the progress of imageing sensor manufacturing process, in the prior art, the resolution of imageing sensor improves greatly, conventionally can reach 5,000,000 pixels or higher.Yet for having the imageing sensor of high-resolution, the lifting of image resolution ratio inevitably causes needing data volume to be processed to increase, this can further increase difficulty that successive image signal is processed.For example, in preview mode (Preview Mode), if keep image resolution ratio constant, can make the frame per second (Frame Rate) that in preview mode, image shows too low, affect preview effect.
In order to improve the frame per second that in preview mode, image shows, a kind of existing image-signal processing method abandons the part signal in the picture signal that imageing sensor gathers, for example only obtain the picture signal of all even number lines, and omit the picture signal of all odd-numbered lines.Although this image-signal processing method can reach the object that reduces view data treating capacity, yet this tends to cause the excessive loss of image information, thereby can reduce significantly the quality that image shows.
Summary of the invention
Visible, a kind of image processing circuit and image processing method of imageing sensor need to be provided, when reducing data processing amount and improving image display frame rate, avoid as much as possible the decline of image displaying quality.
In order to address the above problem, according in the embodiment of one aspect of the invention, provide a kind of signal processing circuit of imageing sensor, comprising: at least two image electric capacity, are configured to controllably obtain the picture signal of at least one pixel; At least two reset capacitance, are configured to controllably obtain the reset signal of at least one pixel; The first switch unit, is configured at least one at least two image electric capacity described in making in response to control signal and is couple to described at least one pixel to obtain picture signal, and described in making, at least two image electric capacity is shared the picture signal of obtaining; And second switch unit, be configured at least one at least two reset capacitance described in making in response to control signal and be couple to described at least one pixel to obtain reset signal, and described in making, at least two reset capacitance are shared the reset signal of obtaining.
In embodiment according to a further aspect of the invention, a kind of signal processing method of imageing sensor is also provided, comprise the steps: to provide at least two image electric capacity, it is configured to controllably obtain the picture signal of at least one pixel; At least two reset capacitance are provided, and it is configured to controllably obtain the reset signal of at least one pixel; At least one in described at least two image electric capacity is coupled to described at least one pixel to obtain picture signal; At least one in described at least two reset capacitance is coupled to described at least one pixel to obtain reset signal; Between described at least two image electric capacity, share the picture signal of obtaining; And between described at least two reference capacitances, share the reset signal obtain.
Compared with prior art, the mode that the signal processing circuit of imageing sensor of the present invention adopts pixel to merge (binning) reduces needs data volume to be processed, because the signal from different pixels in image sensor pixel array can and be shared by different electric capacity collections, this has been avoided the excessive loss of image information, thereby improves image displaying quality.In addition the mode of operation that, the present invention can also effective compatible picture signal reads line by line.
Above characteristic of the present invention and other characteristics are partly set forth embodiment hereinafter clearly.
Accompanying drawing explanation
By reading the following detailed description to non-limiting example with reference to accompanying drawing, can more easily understand features, objects and advantages of the invention.Wherein, same or analogous Reference numeral represents same or analogous device.
Fig. 1 shows a kind of 4T dot structure of imageing sensor;
Fig. 2 shows the signal processing circuit of imageing sensor according to an embodiment of the invention;
Fig. 3 shows the signal processing circuit of imageing sensor according to another embodiment of the present invention, wherein further shows a kind of particular circuit configurations of the first switch unit and the second switch unit;
Fig. 4 shows the sequential chart for the control signal of Fig. 3 signal processing circuit;
Fig. 5 shows the optional structure of another kind of switch unit;
Fig. 6 shows the signal processing method of imageing sensor according to an embodiment of the invention.
Embodiment
Discuss enforcement and the use of embodiment below in detail.Yet, should be appreciated that discussed specific embodiment only exemplarily illustrates and implements and use ad hoc fashion of the present invention, but not limit the scope of the invention.
Cmos image sensor adopts the dot structure of 3T or 4T conventionally.3T dot structure refers in each pixel of cmos image sensor pel array, except the photodiode for sensitization, also comprises 3 transistors, is respectively that transistor and row selecting transistor are followed in reset transistor, source.4T dot structure has further increased a transfering transistor on the basis of 3T dot structure.For signal processing circuit of the present invention and processing method, it both can be processed the signal of 3T dot structure imageing sensor, also can process the signal of 4T dot structure imageing sensor, in the following embodiments, the 4T dot structure of only take describes as example, but the imageing sensor that it should be understood that the other types that comprise 3T dot structure or other dot structures also belongs to scope of the present invention.
Fig. 1 shows a kind of 4T dot structure of imageing sensor, comprises that photodiode 101, transfering transistor 102, reset transistor 103, source follow transistor 104 and row selecting transistor 105.
Wherein, photodiode 101 is for example coupled to, between the first reference potential VSS (common electrical pressure side or negative power end) and the source electrode of transfering transistor 102, for responding to light intensity variation, forms corresponding charge signal.
The drain electrode of transfering transistor 102 is connected with the grid that transistor 104 is followed in source electrode and the source of reset transistor 103, the grid of this transfering transistor 102 is used for receiving transfer control signal TX, shifting under the control of control signal TX, the corresponding conducting of transfering transistor 102 or shutoff, thereby the charge signal that photodiode 101 is responded to is read out to the drain electrode of this transfering transistor 102, and by this drain electrode stored charge signal.
The drain electrode of reset transistor 103 is connected to the second reference potential VDD (for example positive power source terminal), its grid is used for receiving reseting controling signal RST, under the control of this reseting controling signal RST, the corresponding conducting of reset transistor 103 or shutoff, thus the grid of following transistor 104 to source provides reset signal.
The drain electrode that transistor 104 is followed in source is connected to the second reference potential VDD, and its source electrode is connected to the drain electrode of row selecting transistor 105, for the charge signal that transfering transistor 102 is obtained, is converted to voltage signal.The source electrode of row selecting transistor 105 is connected with bit line BL, its grid is used for receiving array selecting signal RS, under the control of this row selection signal RS, row selecting transistor 105 is corresponding to be opened or closure, thereby the drain electrode that makes source follow transistor 104 is selectively couple to bit line BL, and then the signal that transistor 104 conversion is followed in source is exported by bit line BL.
Fig. 2 shows the signal processing circuit of imageing sensor according to an embodiment of the invention.In Fig. 2, also show the partial pixel in image sensor pixel array, comprise the first pixel 211 and the second pixel 212.In the present embodiment, the first pixel 211 and the second pixel 212 are arranged in the same row of image sensor pixel array, and its output is couple to same bit line BL jointly.This signal processing circuit comprises:
The first image electric capacity 201 and the second image electric capacity 202, be configured to controllably obtain the picture signal of at least one pixel in pel array, for example the picture signal of the first pixel 211 and/or the second pixel 212;
The first reset capacitance 203 and the second reset capacitance 204, be configured to controllably obtain the reset signal of at least one pixel in pel array, for example the reset signal of the first pixel 211 and/or the second pixel 212;
The first switch unit 205, be configured to make in response to control signal at least one in this first image electric capacity 201 and the second image electric capacity 202 to be couple at least one pixel in pel array to obtain picture signal, and make this first image electric capacity 201 and the second image electric capacity 202 share the picture signal of obtaining; And
The second switch unit 206, be configured to make in response to control signal at least one in this first reset capacitance 203 and the second reset capacitance 204 to be couple at least one pixel in pel array to obtain reset signal, and make this first reset capacitance 203 and the second reset capacitance 204 share the reset signal of obtaining.
It should be noted that, in actual applications, difference according to specific needs, signal processing circuit can also comprise 3 above image electric capacity, these image electric capacity can obtain the picture signal of different pixels in pel array respectively, and share obtained picture signal; Similarly, this signal processing circuit can further include 3 above reset capacitance, and these reset capacitance can be obtained the reset signal of different pixels in pel array respectively, and share obtained reset signal.Like this, the signal that this signal processing circuit can gather 3 above pixels merges, and reduces image resolution ratio to reduce data processing amount.Be appreciated that, for 3 above pixels, the mode that its signal merges and 2 picture element signals merge similar.Therefore,, in following embodiment, only with signal processing circuit or the method that the signal of 2 pixels is merged, describe.Correspondingly, this signal processing circuit has 2 image electric capacity and 2 reset capacitance.
It should be noted that in addition, 2 alleged pixels, are the operations for a signal merging here.In actual applications, signal processing circuit is the cycle to carry out ground to the processing of each pixel in pel array, for example, in the mode of lining by line scan, obtain the signal of every a line.Signal processing circuit, after the once merging that completes obtained signal, can be amplified this signal and pass through the digital signal that analog to digital conversion circuit (A/D Converter) is converted to corresponding size further; Afterwards, signal processing circuit can be obtained the signal of 2 other pixels (for example, 2 adjacent pixels of aforementioned 2 pixels) again and carry out the merging of obtained signal again.
In this article, term " obtains " and refers between two pole plates of electric capacity and load electrical potential difference, and so that this electric capacity is charged, described charging should make to have stored in electric capacity the quantity of electric charge corresponding with described electrical potential difference.
In one embodiment, this signal processing circuit also comprises amplifying unit 207, for amplifying through shared picture signal and the voltage difference of reset signal.Therefore, the first switch unit 205 is also configured to make in response to control signal at least one in the first image electric capacity 201 and the second image electric capacity 202 to be couple to this amplifying unit 207 to provide through shared picture signal.Correspondingly, the second switch unit 206 is also configured to make in response to control signal at least one in described the first reset capacitance 203 and the second reset capacitance 204 to be couple to this amplifying unit 207 to provide through shared reset signal.
Particularly, in the first switch unit 205 and the second switch unit 206, can comprise respectively more than one switch, wherein each switch has the control end for reception control signal.Difference based on institute's reception control signal, each switch is opened respectively or is closed, thereby make each image electric capacity or reset capacitance be couple to pel array, and obtain corresponding picture signal or reset signal by bit line BL, or make each image electric capacity or reset capacitance be couple to the input of amplifying unit 207, to provide through shared picture signal and reset signal to amplifying unit 207.Wherein, bit line BL conventionally with pel array in a row pixel couple mutually, can obtain the signal that in this row pixel, different rows pixel provides according to the difference of row selection signal RS.
Next the working method of this signal processing circuit is described in detail.
First, signal processing circuit gathers the reset signal of the first pixel 211.Particularly, the control based on row selection signal RS, the first pixel 211 is selected, row selecting transistor 221 conductings wherein.Then, reseting controling signal RST controls reset transistor 222 conductings, and the first pixel 211 provides the first reset signal to bit line BL.Simultaneously, the second switch unit 206 makes the first reset capacitance 203 and/or the second reset capacitance 204 be couple to this bit line BL in response to control signal, thereby obtain this first reset signal, in the first reset capacitance 203 and/or the second reset capacitance 204, stored the first reset charge Qref1 corresponding with the first reset signal.Be appreciated that during gathering the first reset signal, the second switch unit 206 should make the disconnection that is connected between the first reset capacitance 203 and the second reset capacitance 204 and amplifying unit 207.
Then, signal processing circuit gathers the picture signal of the first pixel 211.Particularly, the control based on row selection signal RS, the first pixel 211 is still selected, and row selecting transistor 221 is wherein still in conducting state.Shift 223 conductings of control signal TX controls metastasis transistor, the first pixel 211 provides the first picture signal to bit line BL.Simultaneously, the first switch unit 205 makes the first image electric capacity 201 and/or the second image electric capacity 202 be couple to this bit line BL in response to control signal, thereby obtain this first picture signal, in the first image electric capacity 201 and/or the second image electric capacity 202, stored the first image charge Q corresponding with the first picture signal
sig1.Be appreciated that during gathering the first picture signal, the first switch unit 205 should make the disconnection that is connected between the first image electric capacity 201 and the second image electric capacity 202 and amplifying unit 207; And the first reset capacitance 203 and the second reset capacitance 204 and bit line BL and with amplifying unit 207 between be connected all and disconnect.
Next, signal processing circuit gathers the reset signal of the second pixel 212.Particularly, the control based on row selection signal RS, the second pixel 212 is selected, row selecting transistor 226 conductings wherein.Then, reseting controling signal RST controls reset transistor 227 conductings, and the second pixel 212 provides the second reset signal to bit line BL.Meanwhile, the first switch unit 205 makes the first reset capacitance 203 or the second reset capacitance 204 be couple to this bit line BL in response to control signal, thereby obtains this second reset signal.Wherein, if the first reset capacitance 203 and the second reset capacitance 204 have all been obtained the first reset signal, any that can be in the first reset capacitance 203 or the second reset capacitance 204 obtained the second reset signal.If but only had one to obtain the first reset signal in this first reset capacitance 203 and the second reset capacitance 204, only could obtain the second reset signal by the reset capacitance of not obtaining the first reset signal, to avoid the first reset signal to lose.Like this, in the first reset capacitance 203 and the second reset capacitance 204, just stored respectively the first reset charge Q
ref1and the second reset charge Q corresponding with the second reset signal
ref2.Be appreciated that, during gathering the second reset signal, the second switch unit 206 should make the disconnection that is connected between the first reset capacitance 203 and the second reset capacitance 204 and amplifying unit 207, and the first image electric capacity 201 and the second image electric capacity 202 disconnect with amplifying unit 207 and with being connected all of bit line BL.
Afterwards, signal processing circuit gathers the picture signal of the second pixel 212.Particularly, the control based on row selection signal RS, the second pixel 212 is still selected, and row selecting transistor 226 is wherein still in conducting state.Shift 228 conductings of control signal TX controls metastasis transistor, the second pixel 212 provides the second picture signal to bit line BL.Meanwhile, the second switch unit 206 makes the first image electric capacity 201 and/or the second image electric capacity 202 be couple to this bit line BL in response to control signal, thereby obtains this second picture signal.Wherein, if the first image electric capacity 201 and the second image electric capacity 202 have all obtained the first picture signal, any that can be in the first image electric capacity 201 or the second image electric capacity 202 obtained the second picture signal.If but only had one to obtain the first picture signal in this first image electric capacity 201 and the second image electric capacity 202, only could obtain the second picture signal by the image electric capacity that does not obtain the first picture signal, to avoid the first picture signal to lose.Like this, in the first image electric capacity 201 and the second image electric capacity 202, just stored respectively the first image charge Q
sig1and the second image charge Q corresponding with the second picture signal
sig2.Be appreciated that, during gathering the second picture signal, the first switch unit 205 should make the disconnection that is connected between the first image electric capacity 201 and the second image electric capacity 202 and amplifying unit 207, and the first reset capacitance 203 and the second reset capacitance 204 and bit line BL and with amplifying unit 207 between be connected all and disconnect.
By above-mentioned steps, completed obtaining of each pixel image signal and reset signal.Then, the first switch unit 205 makes the first image electric capacity 201 and the second image electric capacity 202 be connected in parallel in response to control signal, and the second switch unit 206 makes the first reset capacitance 203 and the second reset capacitance 204 be connected in parallel in response to control signal.
Like this, the first image charge Q
sig1with the second image charge Q
sig2between the first image electric capacity 201 and the second image electric capacity 202, share, according to the ratio of capacitance, redistribute, and form new picture signal.The first image electric capacity 201 of take obtains the second picture signal and the second image electric capacity 202 obtains the first picture signal as example.After carrying out the merging of described image signal voltage, the first image electric capacity 201 should equate with the voltage of picture signal on the second image electric capacity 202, be specially (C
sig1u
sig2+ C
sig2u
sig1)/(C
sig1+ C
sig2), C wherein
sig1the capacitance that represents the first image electric capacity 201, C
sig2the capacitance that represents the second image electric capacity 202, U
sig1the voltage that represents the first picture signal, U
sig2the voltage that represents the second picture signal.
In actual applications, what the capacitance of the first image electric capacity 201 and the second image electric capacity 202 can be according to application demand is different and different, i.e. the first picture signal and the second picture signal weighted in signal merges.According to one embodiment of present invention, this first image electric capacity 201 can equate with the capacitance of the second image electric capacity 202, and like this, the magnitude of voltage of the picture signal after merging is (U
sig2+ U
sig1)/2.
Similarly, the first reset charge Q
ref1with the second reset charge Q
ref2between the first reset capacitance 203 and the second reset capacitance 204, share, and form new reset signal.Be appreciated that in the shared process of electric charge, the first switch unit 205 and the second switch unit 206 should make the disconnection that is connected between each electric capacity and amplifying unit 207 and pixel.
By sharing of charge signal in electric capacity, realized the merging corresponding to the picture signal of different pixels.The decline of the caused picture quality of picture signal of traditional omission (skipping) a line or multirow pixel had both been avoided in the merging of this picture signal, for example in image, crenellated phenomena is serious, effectively reduced again the data volume that successive image signal is processed, thereby can improve the frame per second that image shows, particularly in the application scenarios of similar preview mode.
At settling signal, share (merging) afterwards, can further shared picture signal and reset signal be offered to amplifying unit 207, particularly, the first switch unit 205 makes at least one in the first image electric capacity 201 and the second image electric capacity 202 be couple to an input of amplifying unit 207 in response to control signal, to provide through shared picture signal; And the second switch unit 206 makes at least one in the first reset capacitance 203 and the second reset capacitance 204 be couple to another input of amplifying unit 208 in response to control signal, to provide through shared picture signal.Wherein, than two image electric capacity (and two reset capacitance) being all couple to the playback mode of amplifying unit, only couple one of them image electric capacity (and a reset capacitance) and to the playback mode of amplifying unit 207, be equivalent to reduce the capacitance of amplifying unit 207 inputs, thereby gain amplifier is reduced.Especially, in a preferred embodiment, image electric capacity all equates with the capacitance of reset capacitance, in this case, the gain amplifier that only couples image/reset capacitance playback mode only have couple two image/reset capacitance playback modes gain amplifier 1/2.When outside light intensity is higher, the reduction of gain amplifier can be avoided image overexposure, thereby improves picture quality.
In the present embodiment, the signal that this signal processing circuit has been used between different pixels signal merges, and different image capacitance arrangement is to obtain the picture signal of different pixels, and different reset capacitance is configured to obtain the reset signal of different pixels.But in actual applications,, this signal processing circuit still can compatible not carried out the mode of operation of signal merging, for example, in picture photographing mode.
In addition, because this signal processing circuit has a plurality of controlled image/reset capacitance, carry out collection signal, so it can carry out read output signal in mode more flexibly.
Particularly, when a pixel is carried out to signals collecting, two image/reset capacitance all can be couple to this pixel to obtain corresponding signal, in this case, when read output signal, two image/reset capacitance all can be couple to amplifying unit 207, or only an image/reset capacitance be couple to amplifying unit 207, wherein, the gain amplifier of front kind of playback mode is the latter's twice.On the other hand, also can only couple an image/reset capacitance and carry out collection signal to pixel, in this case, when read output signal, can between two image/reset capacitance, share the signal gathering, and two image/reset capacitance are all couple to amplifying unit 207, due to another image/reset capacitance collection signal not, so the magnitude of voltage of signal reduces half after sharing, and also corresponding reduction of gain amplifier.
Normally, in imageing sensor, the charge signal of pixel in pel array induction is selected and obtains by row, and therefore, for the first above-mentioned pixel and the second pixel, it is in two row pixels of pel array, to be positioned at two pixels of same row.According to one embodiment of present invention, this imageing sensor is black and white image transducer, and the first pixel and the second pixel are two pixels in two row pixels adjacent in pel array.In another embodiment, this imageing sensor is color image sensor, Baeyer RGB (Bayer RGB) imageing sensor for example, the first pixel and the second pixel are the neighbors that the same row of being arranged in of pel array belong to same tone, for example adjacent two redness (R) pixel in same row.
It should be noted that, at least two pixels in previous embodiment are the pixels that are arranged in the same row of pel array, and it shares same bit line and provides signal to an amplifying unit.For two pixels in different lines or the signal between more pixels, merge, because adopting different bit lines, it to different amplifying units, provides signal, and different amplifying units has, different image/reset capacitance is obtained and storage signal, therefore, for the pixel that is arranged in different lines, when read output signal, corresponding bit line can be interconnected, and then make corresponding image/reset capacitance in parallel to share signal mutually, can realize the merging of signal.
Fig. 3 shows the signal processing circuit of imageing sensor according to another embodiment of the present invention, wherein further shows a kind of particular circuit configurations of the first switch unit and the second switch unit.Just as previously described, the first switch unit and the second switch unit can comprise a plurality of series connection and/or the gate-controlled switch being connected in parallel, and by changing the wherein conducting state of switch, image/reset capacitance are couple on different nodes.In actual applications, the control signal that gate-controlled switch receives can be by control module independently, and for example micro-control unit (MCU) provides.
Particularly, this signal processing circuit comprises the first image electric capacity 301, the second image electric capacity 302, the first reset capacitance 303, the second reset capacitance 304, the first switch unit 312 and the second switch unit 313.
Wherein, the first switch unit 312 is coupled between input and the first output, comprises the first switch 305, second switch 306 and the 3rd switch 307 that are connected in series; Between the first switch 305 and second switch 306, having the first intermediate node 361, the first image electric capacity 301 is coupled between this first intermediate node 361 and the first reference potential VSS; Between second switch 306 and the 3rd switch 307, having the second intermediate node 362, the second image electric capacity 302 is coupled between this second intermediate node 362 and the first reference potential VSS.This first reference potential VSS is for example common potential end, or negative power end.
The second switch unit 312 is coupled between input and the second output, comprises the 4th switch 308, the 5th switch 309 and the 6th switch 310 that are connected in series; Between the 4th switch 308 and the 5th switch 309, having the 3rd intermediate node 363, the first reset capacitance 303 is coupled between the 3rd intermediate node 363 and the first reference potential VSS; Between the 5th switch 309 and the 6th switch 310, having the 4th intermediate node 364, the second reset capacitance 304 is coupled between the 4th intermediate node 364 and the first reference potential VSS.
Be appreciated that for 3 above image electric capacity, the first switch unit 312 4 above switches of can connecting, and each image electric capacity is respectively coupled between intermediate node and the first reference potential VSS.Similarly, for 3 above reset capacitance, the second switch unit 313 4 above switches of can connecting, and each reset capacitance is respectively coupled between intermediate node and the first reference potential.
In specific embodiment, the first switch 305, second switch 306, the 3rd switch 307, the 4th switch 308, the 5th switch 309 and the 6th switch 310 all can adopt mos transistor switch, for example nmos transistor switch or PMOS transistor switch, the grid of this MOS transistor is as the control end of reception control signal, and the source electrode of MOS transistor and drain electrode are for transmission of signal.
Fig. 4 shows the sequential chart for the control signal of Fig. 3 signal processing circuit.Next, in conjunction with Fig. 3 and Fig. 4, the work of the imageing sensor of one embodiment of the invention and signal processing circuit thereof is further detailed.
Each control signal in Fig. 4 is carried in corresponding switch or transistorized control end respectively.Particularly, row selection signal RS is loaded in the grid of the row selecting transistor of each pixel in pel array; Reset signal RST is loaded in the grid of the reset transistor of each pixel; Shift the grid that control signal TX is loaded in the transfering transistor of each pixel; The first control signal SHR is loaded in the control end of the 4th switch 308; The second control signal SHS is loaded in the control end of the first switch 305; The 3rd control signal EQ is loaded in the control end of second switch 306 and the 5th switch 309; The 4th control signal SEL is loaded in the control end of the 3rd switch 307 and the 6th switch 310.
First, at the first period T1, by the second image electric capacity 302 and the second reset capacitance 304, obtained respectively the first reset signal V of the first pixel 321
ref1with the first picture signal V
sig1.
Particularly, the 3rd control signal EQ is remained valid, this makes second switch 306 and the 5th switch 309 keep conducting, and the first image electric capacity 301 and the second image electric capacity 302 are connected in parallel, and the first reset capacitance 303 and the second reset capacitance 304 are connected in parallel; , the row selection signal RS of the first pixel 321 correspondences is remained valid, this makes row selecting transistor 345 conductings of the first pixel 321, thereby the first pixel 321 is connected to bit line BL meanwhile.In the case, again successively reset signal RST, the first control signal SHR, shift control signal TX and the second control signal SHS is set to effectively, thereby turns on reset transistor 343, the 4th switch 308, transfering transistor 342 and the first switch 305 successively.
Under above-mentioned sequencing control, the conducting of reset transistor 343 makes bit line BL receive the first reset signal.And then, the conducting of the 4th switch 308 and the 5th switch 309 makes the first reset capacitance 303 and the second reset capacitance 304 obtain the first reset signal V simultaneously
ref1, the second reset capacitance 304 is stored based on described the first reset signal V
ref1the the first reset charge Q generating
ref1, i.e. C
ref2v
ref1, C wherein
ref2the capacitance that represents the second reset capacitance 304.Afterwards, the conducting of transfering transistor 342 makes bit line BL receive the first picture signal V
sig1.And then, the first switch 305 makes the first image electric capacity 301 and the second image electric capacity 302 obtain the first picture signal V with the conducting of second switch 306 simultaneously
sig1, the second image electric capacity 302 is stored based on described the first picture signal V
sig1the the first image charge Q generating
sig1, i.e. C
sig2v
sig1, C wherein
sig2the capacitance that represents the second image electric capacity 302.
Afterwards, at the second period T2, by the first image electric capacity 301 and the first reset capacitance 303, obtain respectively the second reset signal V
ref2with the first picture signal V
sig2.
Particularly, the 3rd control signal EQ is kept to invalid, this makes second switch 306 and the 5th switch 309 keep turn-offing, and the first image electric capacity 301 and the second image electric capacity 302 disconnect, and the first reset capacitance 303 and the second reset capacitance 304 disconnect; , the row selection signal RS of the second pixel 322 correspondences is remained valid, this makes row selecting transistor 350 conductings of the second pixel 322, thereby the second pixel 322 is connected to bit line BL meanwhile.In the case, again successively reset signal RST, the first control signal SHR, shift control signal TX and the second control signal SHS is set to effectively, thereby turns on reset transistor 348, the 4th switch 308, transfering transistor 347 and the first switch 305 successively.
Under above-mentioned sequencing control, the conducting of reset transistor 348 makes bit line BL receive the second reset signal V
ref2.And then, the 4th switch 308 conductings make the first reset capacitance 303 obtain the second reset signal V
ref2, the first reset capacitance 303 is stored based on described the second reset signal V
ref2the the second reset charge Q generating
ref2, i.e. C
ref1v
ref2, C wherein
ref1the capacitance that represents the second reset capacitance 303.Afterwards, the conducting of transfering transistor 347 makes bit line BL correspondingly obtain the second picture signal V of the second pixel 322
sig2.And then, the conducting of the first switch 305 makes the first image electric capacity 301 obtain the second picture signal V
sig2, the first image electric capacity 301 is stored based on described the second picture signal V
sig2the the second image charge Q generating
sig2, i.e. C
sig1v
sig2, C wherein
sig1the capacitance that represents the first image electric capacity 301.
Can find out, after described the first period T1 and the second period T2, the first image electric capacity 301 and the second image electric capacity 302 have obtained respectively based on the second picture signal V
sig2with the first picture signal V
sig1the the second image charge Q generating
sig2with the first image charge Q
sig1, the first reset capacitance 303 and the second reset capacitance 304 have obtained respectively the second reset signal V
ref2with based on the first reset signal V
ref1the the second reset charge Q generating
ref2with the first reset charge Q
ref1.These electric charges have reflected respectively the size of the first pixel 321 and the second pixel 322 picture signals and reset signal.
Next, at phase III T3, respectively to the first image electric capacity 301 and the second image electric capacity 302, and the first reset capacitance 303 and the second reset capacitance 304 are carried out electric charge and are shared.
Particularly, only the 3rd control signal EQ is set to effectively, and this is connected in parallel the first image electric capacity 301 and the second image electric capacity 302, the first image charge Q obtaining
sig1with the second image charge Q
sig2redistribute betwixt, and finally make the first image electric capacity 301 equate with the magnitude of voltage between the second image electric capacity 302 two-plates.Similarly, the second image electric capacity 303 and the second reset capacitance 304 are also connected in parallel, the first reset charge Q obtaining
ref1with the second reset charge Q
ref2redistribute betwixt, and finally make the first reset capacitance 303 equate with the magnitude of voltage between the second reset capacitance 304 two-plates.
Then, at fourth stage T4, the 4th control signal SEL is effective by column, and image/reset signal that each row are merged is read successively.The 4th control signal SEL is set to effectively make corresponding the 3rd switch 307 and the 6th switch 310 conductings, the 3rd control signal EQ is set to effectively so that second switch 306 and the 5th switch conduction simultaneously, thereby make the first image electric capacity 301 and the second image electric capacity 302 be connected to an input of amplifying unit 314, and the first reset capacitance 303 and the second reset capacitance 304 are connected to another input of amplifying unit 314, and then the reset signal on it and sub image signal are supplied with to amplifying unit 314 indescribably.Amplifying unit 314 amplifies the voltage difference of picture signal and reset signal further, and the output voltage through amplifying is offered to follow-up signal processing circuit.
Alternatively, at fourth stage T4, can also be set to invalid (not shown) so that second switch 306 and the 5th switch 309 disconnect by the 3rd control signal EQ, thereby make the second image electric capacity 302 and the second reset capacitance 304 be connected respectively to two inputs of amplifying unit 314, and obtained reset signal and picture signal is provided.
As aforementioned, if desired the signal of different lines pixel is merged, can when reading, make to need corresponding the 4th control signal of row of merging simultaneously effective.Like this, each is listed as the input that corresponding image/reset capacitance is connected in amplifying unit in parallel, thereby realizes the merging of signal.
Should be appreciated that, in the present invention, the structure of the first switch unit and the second switch unit is only example, and any other can make each electric capacity be connected respectively to the different pixels of pel array and the switching circuit structure of obtaining image/reset signal all belongs to scope of the present invention.Fig. 5 shows the optional structure of another kind of switch unit, and its two electric capacity that connect are controlled by a switch of correspondence respectively.Adopt working method and the previous embodiment of signal processing circuit of switch unit of this kind of structure basic identical, do not repeat them here.
With reference to figure 6, show the signal processing method of imageing sensor according to an embodiment of the invention, comprise the following steps:
Execution step S602, provides at least two image electric capacity, and it is configured to controllably obtain the picture signal of at least one pixel;
Execution step S604, provides at least two reset capacitance, and it is configured to controllably obtain the reset signal of at least one pixel;
Execution step S606, is coupled to described at least one pixel to obtain picture signal by least one in described at least two image electric capacity;
Execution step S608, is coupled to described at least one pixel to obtain reset signal by least one in described at least two reset capacitance;
Execution step S610 shares the picture signal of obtaining between described at least two image electric capacity; And
Execution step S612 shares the reset signal of obtaining between described at least two reference capacitances.
In one embodiment of the invention, after step S610 and S610, also comprise: at least one in described two image electric capacity is couple to amplifying unit to provide through shared picture signal; And at least one in described two reset capacitance is couple to amplifying unit to provide through shared reset signal.
In one embodiment of the invention, described step S606 also comprises: described at least two image electric capacity are coupled to different pixels to obtain corresponding picture signal; Correspondingly, described step S608 also comprises: described at least two image electric capacity are coupled to different pixels to obtain corresponding picture signal.
In one embodiment of the invention, described pixel is positioned at the same row of image sensor pixel array.
In one embodiment of the invention, described pixel is the pixel of same tone in image sensor pixel array.
In one embodiment of the invention, the step of obtaining described reset signal is to carry out before obtaining the step of described picture signal.
In one embodiment of the invention, the capacitance of described at least two image electric capacity equates.
In one embodiment of the invention, described reset capacitance all equates with the capacitance of described image electric capacity.
Although illustrate in detail and described the present invention in accompanying drawing and aforesaid description, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The invention is not restricted to above-mentioned execution mode.
The those skilled in the art of those the art can, by research specification, disclosed content and accompanying drawing and appending claims, understand and implement other changes of the execution mode to disclosing.In the claims, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number.In the practical application of invention, a part may execute claims the function of middle quoted a plurality of technical characterictics.Any Reference numeral in claim should not be construed as the restriction to scope.
Claims (16)
1. a signal processing circuit for imageing sensor, comprising:
At least two image electric capacity, are configured to controllably obtain respectively the picture signal of at least two different pixels;
At least two reset capacitance, are configured to controllably obtain respectively the reset signal of at least two different pixels;
The first switch unit, described in being configured to make in response to control signal at least two image electric capacity be couple to described at least two different pixels to obtain corresponding picture signal, and the picture signal at least two image electric capacity is redistributed according to the capacitance ratio of described at least two image electric capacity described in making, to form new picture signal; And
The second switch unit, described in being configured to make in response to control signal at least two reset capacitance be couple to described at least two different pixels to obtain corresponding reset signal, and the reset signal at least two reset capacitance is redistributed according to the capacitance ratio of described at least two reset capacitance described in making, to form new reset signal;
Wherein, described at least two different pixels are positioned at the same row of image sensor pixel array.
2. signal processing circuit according to claim 1, is characterized in that, also comprises amplifying unit, for amplifying the voltage difference of described new picture signal and described new reset signal.
3. signal processing circuit according to claim 2, it is characterized in that, at least one described in described the first switch unit is also configured to make in response to control signal at least two image electric capacity is couple to described amplifying unit so that described new picture signal to be provided.
4. signal processing circuit according to claim 2, it is characterized in that, at least one described in described the second switch unit is also configured to make in response to control signal at least two reset capacitance is couple to described amplifying unit so that described new reset signal to be provided.
5. signal processing circuit according to claim 1, it is characterized in that, described the first switch unit comprises at least three switches that are connected in series that are coupled between input node and the first output node, the wherein said switch being connected in series has at least two intermediate nodes that are positioned at switch room, and each in described at least two image electric capacity is respectively coupled between described intermediate node and reference potential.
6. signal processing circuit according to claim 1, it is characterized in that, described the second switch unit comprises at least three switches that are connected in series that are coupled between input node and the second output node, the wherein said switch being connected in series has at least two intermediate nodes that are positioned at switch room, and each in described at least two reset capacitance is respectively coupled between described intermediate node and reference potential.
7. signal processing circuit according to claim 1, is characterized in that, described at least two different pixels are pixels of same tone in image sensor pixel array.
8. signal processing circuit according to claim 1, is characterized in that, the capacitance of described at least two image electric capacity equates.
9. signal processing circuit according to claim 8, is characterized in that, described reset capacitance equates with the capacitance of described image electric capacity.
10. an imageing sensor, comprises pel array, and according to the signal processing circuit described in any one in claim 1 to 9.
The signal processing method of 11. 1 kinds of imageing sensors, comprises the steps:
At least two image electric capacity are provided, and it is configured to controllably obtain respectively the picture signal of at least two different pixels;
At least two reset capacitance are provided, and it is configured to controllably obtain respectively the reset signal of at least two different pixels;
Described in described at least two image electric capacity are coupled to, at least two different pixels are to obtain corresponding picture signal;
Described in described at least two reset capacitance are coupled to, at least two different pixels are to obtain corresponding reset signal;
According to the capacitance ratio of described at least two image electric capacity, the picture signal in described at least two image electric capacity is redistributed, to form new picture signal; And
According to the capacitance ratio of described at least two reset capacitance, the reset signal in described at least two reset capacitance is redistributed, to form new reset signal;
Wherein, described at least two different pixels are positioned at the same row of image sensor pixel array.
12. signal processing methods according to claim 11, is characterized in that, after forming the step of described new picture signal and described new reset signal, also comprise:
At least one in described two image electric capacity is couple to amplifying unit so that described new picture signal to be provided; And
At least one in described two reset capacitance is couple to amplifying unit so that described new reset signal to be provided.
13. signal processing methods according to claim 11, is characterized in that, described at least two different pixels are pixels of same tone in image sensor pixel array.
14. signal processing methods according to claim 11, is characterized in that, the step of obtaining described reset signal is to carry out before obtaining the step of described picture signal.
15. signal processing methods according to claim 11, is characterized in that, the capacitance of described at least two image electric capacity equates.
16. signal processing methods according to claim 15, is characterized in that, described reset capacitance equates with the capacitance of described image electric capacity.
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| CN104580887A (en) * | 2014-12-17 | 2015-04-29 | 深圳市比维视创科技有限公司 | Method and device for expanding image resolution of photographing module of terminal, and terminal |
| CN106331434B (en) * | 2016-09-05 | 2019-09-06 | 深圳安芯微电子有限公司 | Image processing apparatus and method |
| US9998700B1 (en) | 2016-12-05 | 2018-06-12 | Omnivision Technologies, Inc. | Image sensor failure detection |
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