CN101540824A - Correlation double sampling circuit and image sensor related to same - Google Patents
Correlation double sampling circuit and image sensor related to same Download PDFInfo
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- CN101540824A CN101540824A CN200810086846A CN200810086846A CN101540824A CN 101540824 A CN101540824 A CN 101540824A CN 200810086846 A CN200810086846 A CN 200810086846A CN 200810086846 A CN200810086846 A CN 200810086846A CN 101540824 A CN101540824 A CN 101540824A
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Abstract
The invention relates to a correlation double sampling circuit and an image sensor related to the same. The correlation double sampling circuit is used for sampling reset signals and light sensing signals outputted by a line of pixels of the image sensor and comprises two sampling capacitors and four transistor switches. The sampling capacitors of the correlation double sampling circuit do not need to convert polarities in operation, so the correlation double sampling circuit can utilize an MOS capacitor with higher unit-area capacitance value to realize sampling to reduce thermal noise in sampling; and simultaneously, a framework of the correlation double sampling circuit uses fewer transistor switches, so the introduced charge injection noise can be greatly reduced when the switches are switched.
Description
Technical field
The present invention is meant a kind of correlation double sampling circuit that is used for image sensor, refers to especially a kind ofly have the circuit framework of simplifying and by not needing the sampling capacitor of polar switching in the operation, to reduce the correlation double sampling circuit that noise produces.
Background technology
Along with the constantly exploitation and growth of electronic goods such as digital camera, mobile phone, the increase that the consumption market is also lasting to the demand of Image Sensor.Generally speaking, Image Sensor at present commonly used, comprised electric charge coupling sensing element (Charge Coupled Device, CCD) and CMOS (Complementary Metal Oxide Semiconductor) Image Sensor (CMOS Image Sensor, CIS) two big classes.Wherein,, add it and can be integrated in present semiconductor technology and make in a large number, so be subjected to the utmost point and use widely because the CMOS Image Sensor has characteristics such as low operating voltage, low power consumption and high operating efficiency.
In the CMOS image sensor, generally can the signal that each picture-element sensor (Pixel Sensor) is produced be read by the analogy front-end circuit, and the application circuit that provides suitable driving force to promote back level, as analogy to digital quantizer or image-processing circuit etc.When operation, picture-element sensor can utilize reset switch that sensor is reset to the signal that initial condition be left behind with once-through operation before removing, but reset switch can be introduced replacement noise (Reset Noise) when switching, therefore this area generally can be by related two sampling (Correlation Double Sampling, CDS) circuit is realized the analogy front-end circuit, so that light sensing signal and the reset signal of being exported from each picture-element sensor carried out secondary sample, and then the difference of acquisition light sensing signal and reset signal (i.e. signal level differences before and after the exposure), the image that can avoid the CMOS image sensor to be produced is subjected to pixel replacement The noise thus.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of a known CMOS image sensor 10.CMOS image sensor 10 includes pel array 11, related two samplings (Correlation Double Sampling, CDS) gate array 12 and back level buffer circuit 13.Generally speaking, the analogy front-end circuit of CMOS image sensor 10 is made up of correlation double sampling circuit array 12 and back level buffer circuit 13.For convenience of description, the picture-element sensor that is listed as with the capable j of i in the picture-element sensor Pij represent pixel array 11 among Fig. 1, represent the correlation double sampling circuit that is coupled to all capable picture-element sensors of i with correlation double sampling circuit CDS_i, then 13 of buffer circuits of level are coupled to all correlation double sampling circuits in the correlation double sampling circuit array 12.Picture-element sensor Pij is four transistor architecture (4 Transistor, active pixel sensor 4T), it includes light sensitive diode PD, transfering transistor (Transfer Transistor) TX, reset transistor (Reset Transistor) RX, driving transistors (Drive Transistor) DX and selects transistor (Select Transistor) SX.Light sensitive diode PD is used for the intensity of sensor light photograph, and the optical charge that produced of integrated incident light line.Transfering transistor TX is used for according to shifting control signal Tg1 the optical charge that accumulates on light sensitive diode PD being transferred to node FD.Reset transistor RX is used for according to reset control signal Rst, and the voltage of replacement node FD is to supply voltage VDD.Driving transistors DX is the one source pole follower, is used for becoming corresponding current signal to export selection transistor SX to the voltage transitions of node FD.Select transistor SX then according to column selection control signal Rsel, export reset signal and light sensing signal in regular turn by output PXO.Wherein, shifting control signal Tg1, reset control signal Rst and column selection control signal Rsel can be produced by column decoder (Row Decoder), repeats no more in this.
Correlation double sampling circuit CDS_i is used in regular turn the reset signal and the light sensing signal of all capable picture-element sensors outputs of i are taken a sample, 8 switches 121～128 that it includes sampling capacitor CS and CR, constant current source I1, reference voltage VR1 and is controlled by control signal SS, SR, Sn and Scel respectively.Back level buffer circuit 13 is coupled to correlation double sampling circuit CDS_i by input VIP and VIN, 6 MOS switches 131～136 that it includes operational amplifier OP1, capacitor C 1 and C2 and is controlled by control signal S1 and S2 respectively.The mode of operation of analogy front-end circuit is summarized as follows: at first, control signal Sn short switch 123 and 124 is so that the negative terminal of sampling capacitor CS and CR is coupled to reference voltage VR1.Then, control signal SR and SS be in regular turn in two Non-overlap Phases (Non-overlappingPhase) short switch 121 and 122, reading reset signal and light sensing voltage of signals by picture-element sensor Pij respectively, and is stored among sampling capacitor CR and the CS.When CMOS image sensor 10 desires capture the signal of picture-element sensor Pij, correlation double sampling circuit CDS_i and back level buffer circuit 13 can be respectively according to control signal Scel and S2, while short switch 125～128 and switch 131,132, be coupled to reference voltage VR1 (promptly changing the polarity of sampling capacitor CS and CR) with anode with sampling capacitor CS and CR, and the characteristic of two input virtual earth by operational amplifier OP1, sampling capacitor CR and the stored electric charge difference of CS are transferred in the capacitor C 1 and C2 of back level buffer circuit 13.Thus, CMOS image sensor 10 can be passed through differential output end VOP and VON, and output is relevant to the voltage signal Vout of difference between light sensing signal and reset signal, to drive the data processing circuit of back level.Certainly, before sampling capacitor CS and CR were transferred to capacitor C 1 and C2 with stored electric charge difference, a back level buffer circuit 13 can be according to control signal S1, and short switch 133～136 is to remove capacitor C 1 and C2 in last time operating stored electric charge.Correlation timing about above-mentioned control signal please refer to Fig. 2.
Yet, analogy front-end circuit for the CMOS image sensor, main consideration when how to reduce noise and can be design, and thermal noise that the main noise source is introduced when being broadly divided into capacitor sampling and the electric charge that produced when switching the MOS switch inject noise (Charge injection noise) two kinds.Wherein, (K is a Boltzmann constant because the size of thermal noise is proportional to KT/C, T is an absolute temperature, and C represents the capacitance size of sampling capacitor), therefore it can improve by the capacitance that strengthens sampling capacitor, and the electric charge that is produced when switching the MOS switch injects noise then to be needed to reach by the quantity and the switching times that reduce the MOS switch.
Summary of the invention
Therefore, main purpose of the present invention promptly is to provide a kind of correlation double sampling circuit that is used for image sensor.
The present invention discloses a kind of complementary metal oxide semiconductor image sensor, includes a pel array and a plurality of correlation double sampling circuit.Described pel array includes a plurality of picture-element sensors that are arranged in matrix form, and each picture-element sensor is used for sensing incident light intensity, and exports reset signal and light sensing signal in regular turn.Described a plurality of correlation double sampling circuit is respectively coupled to the delegation in the described pel array, is used for described reset signal and described light sensing signal that this row is exported are taken a sample.The related two sampling units of each of described a plurality of correlation double sampling circuits include a signal input part, are used for receiving described reset signal and described light sensing signal; One first sampling capacitor has first end and second end, and described second end is coupled to reference voltage end; One second sampling capacitor has first end and second end, and described second end is coupled to described reference voltage end; One first switch is coupled between described first end of described signal input part and described first sampling capacitor, be used for described first sampling capacitor being coupled to described signal input part the voltage of described reset signal so that described first sampling capacitor is taken a sample in the phase I; One second switch is coupled between described first end of described signal input part and described second sampling capacitor, be used for described second sampling capacitor being coupled to described signal input part described light sensing voltage of signals so that described second sampling capacitor is taken a sample in second stage; One the 3rd switch is coupled to described first end of described first sampling capacitor, is used in the phase III described first sampling capacitor being coupled to first signal output part, so that the voltage that described first sampling capacitor is taken a sample exports described first signal output part to; And one the 4th switch be coupled to described first end of described second sampling capacitor, be used for described second sampling capacitor being coupled to the secondary signal output, so that the voltage that described second sampling capacitor is taken a sample exports described secondary signal output in the described phase III; Wherein, described first signal output part and described secondary signal output are the differential input terminals of back level buffer amplifier circuit.
The present invention discloses a kind of correlation double sampling circuit that is used for image sensor in addition, is used for reset signal and light sensing signal that the one-row pixels of described image sensor is exported are taken a sample.Described correlation double sampling circuit includes a signal input part, is used in receiving described reset signal and described light sensing signal; One first sampling capacitor has first end and second end, and described second end is coupled to reference voltage end; One second sampling capacitor has first end and second end, and described second end is coupled to described reference voltage end; One first switch is coupled between described first end of described signal input part and described first sampling capacitor, be used for described first sampling capacitor being coupled to described signal input part the voltage of described reset signal so that described first sampling capacitor is taken a sample in the phase I; One second switch is coupled between described first end of described signal input part and described second sampling capacitor, be used for described second sampling capacitor being coupled to described signal input part described light sensing voltage of signals so that described second sampling capacitor is taken a sample in second stage; One the 3rd switch is coupled to described first end of described first sampling capacitor, is used in the phase III described first sampling capacitor being coupled to first signal output part, so that the voltage that described first sampling capacitor is taken a sample exports described first signal output part to; And one the 4th switch be coupled to described first end of described second sampling capacitor, be used for described second sampling capacitor being coupled to the secondary signal output, so that the voltage that described second sampling capacitor is taken a sample exports described secondary signal output in the described phase III; Wherein, described first signal output part and described secondary signal output are the differential input terminals of back level buffer amplifier circuit.
Description of drawings
Fig. 1 is the schematic diagram of a known CMOS image sensor.
Fig. 2 is the sequential schematic diagram of associated control signal among Fig. 1.
Fig. 3 is the embodiment schematic diagram of CMOS image sensor of the present invention.
Fig. 4 is the sequential schematic diagram of associated control signal among Fig. 3.
Drawing reference numeral:
10,30 CMOS image sensor
11,31 pel arrays
12,32 correlation double sampling circuit arrays
13,33 back grade buffer circuits
The Pij picture-element sensor
The CDS_i correlation double sampling circuit
The PD light sensitive diode
TX, RX, DX, SX transistor
Tg1, Rst, Rsel, SS, SR, Sn, Scel, S1, S2 control signal
The FD node
VDD, VR1, Vref voltage
The PXO output
CS, CR sampling capacitor
C1, C2 electric capacity
The I1 constant current source
The OP1 operational amplifier
121～128,131～136,321～324,331～336 switches
VIP, VIN differential input terminal
VOP, VON differential output end
The Vout voltage signal
Embodiment
Please refer to Fig. 3, Fig. 3 is the embodiment schematic diagram of the present invention's one CMOS image sensor 30.CMOS image sensor 30 includes pel array 31, related two samplings (Correlation DoubleSampling, CDS) gate array 32 and back level buffer circuit 33.For convenience of description, the picture-element sensor that is listed as with the capable j of i in the picture-element sensor Pij represent pixel array 31 among Fig. 3, represent the correlation double sampling circuit that is coupled to all capable picture-element sensors of i with correlation double sampling circuit CDS_i, then 33 of buffer circuits of level are coupled to all correlation double sampling circuits in the correlation double sampling circuit array 32.Picture-element sensor Pij can be any type of picture-element sensor, and (it is used for sensing incident light intensity, and exports reset signal and light sensing signal in regular turn for 4 Transistor, active pixel sensor 4T) as one or four transistor architecture.Correlation double sampling circuit CDS_i is used in regular turn the reset signal and the light sensing signal of all capable picture-element sensor outputs of i being taken a sample, and it includes constant current source I1, sampling capacitor CR and CS, switch 321,322,323,324 and reference voltage Vref.Constant current source I1 is the read current that is used to provide picture-element sensor Pij.Sampling capacitor CR and CS be used for respectively the taking a sample voltage of reset signal and data-signal, the one end is coupled to reference voltage Vref jointly, the other end then is coupled to signal input part CIN by the switch 321 and 322 that is controlled by control signal SR and SS respectively, and the differential input terminal VIP and the VIN that are respectively coupled to back level buffer circuit 33 by the switch 323 and 324 that is controlled by control signal Scel.The MOS switch 331,332,333,334,335 and 336 that back 33 of buffer circuits of level include operational amplifier OP1, capacitor C 1 and C2 and controlled by control signal S1 and S2 respectively.The associative operation of picture-element sensor Pij and back level buffer circuit 33 is similar to picture-element sensor Pij and the back level buffer circuit 13 among Fig. 1, repeats no more in this.
When picture-element sensor Pij exports reset signal and light sensing signal in regular turn, switch 321 and 322 can be respectively according to the control signal SR and the SS of high levle, sampling capacitor CR and CS are coupled to signal input part CIN, reset signal and light sensing voltage of signals so that sampling capacitor CR and CS take a sample respectively.Then, switch 323 and 324 can be according to the control signal Scel of high levle, sampling capacitor CR and CS are coupled to the differential input terminal VIP and the VIN of back level buffer circuit 33 respectively, sampling capacitor CR and the stored voltage of CS are exported to the differential input terminal VIP and the VIN of back level buffer circuit 33 respectively.Wherein, control signal SR, SS and Scel are non-overlapped (Non-overlapping) clock signals, and at sampling capacitor CS and CR stored voltage difference is transferred to before the capacitor C 1 and C2 of back level buffer circuit 33, back level buffer circuit 33 in addition can be according to control signal S1 short switch 333～336, to remove capacitor C 1 and C2 in last time operating stored voltage.Thus, CMOS image sensor 30 of the present invention can be by the differential output end VOP and the VON of back level buffer circuit 33, output is relevant to the voltage signal Vout of difference between light sensing signal and reset signal, to drive the data processing circuit of back level, as analogy to digital converter or image-processing circuit or the like.Correlation timing about above-mentioned control signal please refer to Fig. 4.
Because in background technology, sampling capacitor need carry out the conversion of polarity in operation, therefore sampling capacitor only can the lower metal-insulator-metal type (Metal-Insulator-Metal of applying unit area capacitance value, MIM) (Polysilicon-Insulator-Polysilicon, PIP) electric capacity is made for electric capacity or polycrystalline silicon-on-insulator-polysilicon.In comparison, the sampling capacitor in the correlation double sampling circuit of the present invention does not need the conversion of polarity in operation, so the present invention can utilize the higher mos capacitance of unit-area capacitance value to realize.Thus, the present invention can provide higher capacitance in area identical, and the influence of thermal noise (KT/C) when reducing sampling perhaps can be dwindled the area of wafer under the situation of identical capacitance values.Simultaneously, the framework of correlation double sampling circuit of the present invention has used less transistor switch, and the electric charge of being introduced when therefore switching the MOS switch injects noise (Charge injection noise) and also can be reduced significantly.
Please note, back level buffer circuit 33 in the embodiment of the invention only is used as an explanation for example, but not be restriction of the present invention, those skilled in the art be when can realizing by other modes, for example use two groups of buffering gain circuitries to add that a subtraction circuit realizes or the like respectively.In addition, the reference voltage Vref described in the present invention is preferably a ground terminal voltage, and switch then by being realized by MOS switch or CMOS transmission lock, as long as have identical circuit framework, all belongs to scope of the present invention.
In sum, the present invention provides a kind of correlation double sampling circuit of the CMOS of being used for image sensor, it has the circuit framework and the flexible implementation of simplifying, and thermal noise that is produced in the time of more can significantly reducing operation and electric charge inject noise, and then promotes the image quality of CMOS image sensor.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. a complementary metal oxide semiconductor image sensor is characterized in that, described complementary metal oxide semiconductor image sensor includes:
One pel array includes a plurality of picture-element sensors that are arranged in matrix form, and each picture-element sensor is used for sensing incident light intensity, and exports reset signal and light sensing signal in regular turn; And
A plurality of correlation double sampling circuits are respectively coupled to the delegation in the described pel array, are used for described reset signal and described light sensing signal that this row is exported are taken a sample, and the related two sampling units of each of described a plurality of correlation double sampling circuits include:
One signal input part is used for receiving described reset signal and described light sensing signal;
One first sampling capacitor has first end and second end, and described second end is coupled to reference voltage end;
One second sampling capacitor has first end and second end, and described second end is coupled to described reference voltage end;
One first switch, be coupled between described first end of described signal input part and described first sampling capacitor, be used for described first sampling capacitor being coupled to described signal input part the voltage of described reset signal so that described first sampling capacitor is taken a sample in the phase I;
One second switch, be coupled between described first end of described signal input part and described second sampling capacitor, be used for described second sampling capacitor being coupled to described signal input part described light sensing voltage of signals so that described second sampling capacitor is taken a sample in second stage;
One the 3rd switch is coupled to described first end of described first sampling capacitor, is used in the phase III described first sampling capacitor being coupled to first signal output part, so that the voltage that described first sampling capacitor is taken a sample exports described first signal output part to; And
One the 4th switch, be coupled to described first end of described second sampling capacitor, be used for described second sampling capacitor being coupled to the secondary signal output, so that the voltage that described second sampling capacitor is taken a sample exports described secondary signal output in the described phase III;
Wherein, described first signal output part and described secondary signal output are the differential input terminals of back level buffer amplifier circuit.
2. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said first switch and described second switch are controlled by one first clock signal and one second clock signal respectively, described the 3rd switch and described the 4th switch are controlled by one the 3rd clock signal simultaneously, and described first clock signal, described second clock signal and described the 3rd clock signal are non-overlapping phases clock signals.
3. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said back level buffer amplifier circuit is a subtraction circuit.
4. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said first switch, described second switch, described the 3rd switch and described the 4th switch are mos transistor switches.
5. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said first sampling capacitor and described second sampling capacitor are mos capacitances.
6. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said first sampling capacitor and described second sampling capacitor are polysilicon-insulator-polysilicon capacitances.
7. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said first sampling capacitor and described second sampling capacitor are metal-insulator-metal capacitances.
8. complementary metal oxide semiconductor image sensor as claimed in claim 1, wherein said reference voltage end are ground ends.
9. a correlation double sampling circuit that is used for image sensor is used for reset signal and light sensing signal that the one-row pixels of described image sensor is exported are taken a sample, and described correlation double sampling circuit includes:
One signal input part is used in receiving described reset signal and described light sensing signal;
One first sampling capacitor has first end and second end, and described second end is coupled to reference voltage end;
One second sampling capacitor has first end and second end, and described second end is coupled to described reference voltage end;
One first switch, be coupled between described first end of described signal input part and described first sampling capacitor, be used for described first sampling capacitor being coupled to described signal input part the voltage of described reset signal so that described first sampling capacitor is taken a sample in the phase I;
One second switch, be coupled between described first end of described signal input part and described second sampling capacitor, be used for described second sampling capacitor being coupled to described signal input part described light sensing voltage of signals so that described second sampling capacitor is taken a sample in second stage;
One the 3rd switch is coupled to described first end of described first sampling capacitor, is used in the phase III described first sampling capacitor being coupled to first signal output part, so that the voltage that described first sampling capacitor is taken a sample exports described first signal output part to; And
One the 4th switch, be coupled to described first end of described second sampling capacitor, be used for described second sampling capacitor being coupled to the secondary signal output, so that the voltage that described second sampling capacitor is taken a sample exports described secondary signal output in the described phase III;
Wherein, described first signal output part and described secondary signal output are the differential input terminals of back level buffer amplifier circuit.
10. correlation double sampling circuit as claimed in claim 9, wherein said first switch and described second switch are controlled by one first clock signal and one second clock signal respectively, described the 3rd switch and described the 4th switch are controlled by one the 3rd clock signal simultaneously, and described first clock signal, described second clock signal and described the 3rd clock signal are non-overlapped phase place clock signal.
11. correlation double sampling circuit as claimed in claim 9, wherein said back level buffer amplifier circuit is a subtraction circuit.
12. correlation double sampling circuit as claimed in claim 9, wherein said first switch, described second switch, described the 3rd switch and described the 4th switch are mos transistor switches.
13. correlation double sampling circuit as claimed in claim 9, wherein said first sampling capacitor and described second sampling capacitor are mos capacitances.
14. correlation double sampling circuit as claimed in claim 9, wherein said first sampling capacitor and described second sampling capacitor are polysilicon-insulator-polysilicon capacitances.
15. correlation double sampling circuit as claimed in claim 9, wherein said first sampling capacitor and described second sampling capacitor are metal-insulator-metal capacitances.
16. correlation double sampling circuit as claimed in claim 9, wherein said reference voltage end are ground ends.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769721A (en) * | 2011-05-03 | 2012-11-07 | 联咏科技股份有限公司 | Related double sampling device and method for image sensor |
| CN104571645A (en) * | 2013-10-23 | 2015-04-29 | 原相科技股份有限公司 | Image sensor and optical navigation unit with same |
| CN108168695A (en) * | 2018-01-03 | 2018-06-15 | 京东方科技集团股份有限公司 | Optical detecting unit and method, optical detection circuit and method and display device |
| CN111246129A (en) * | 2019-05-03 | 2020-06-05 | 神盾股份有限公司 | Optical sensor and image sensing method |
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2008
- 2008-03-19 CN CN200810086846A patent/CN101540824A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769721A (en) * | 2011-05-03 | 2012-11-07 | 联咏科技股份有限公司 | Related double sampling device and method for image sensor |
| CN102769721B (en) * | 2011-05-03 | 2016-06-22 | 联咏科技股份有限公司 | The correlated double sampler of image sensor and method thereof |
| CN104571645A (en) * | 2013-10-23 | 2015-04-29 | 原相科技股份有限公司 | Image sensor and optical navigation unit with same |
| CN104571645B (en) * | 2013-10-23 | 2017-09-22 | 原相科技股份有限公司 | Image sensor apparatus and the optical navigator using this Image sensor apparatus |
| CN108168695A (en) * | 2018-01-03 | 2018-06-15 | 京东方科技集团股份有限公司 | Optical detecting unit and method, optical detection circuit and method and display device |
| CN108168695B (en) * | 2018-01-03 | 2020-05-19 | 京东方科技集团股份有限公司 | Light detection unit and method, light detection circuit and method, and display device |
| CN111246129A (en) * | 2019-05-03 | 2020-06-05 | 神盾股份有限公司 | Optical sensor and image sensing method |
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Application publication date: 20090923 |