CN202587177U - Image sensor and signal processing circuit thereof - Google Patents
Image sensor and signal processing circuit thereof Download PDFInfo
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- CN202587177U CN202587177U CN 201120169415 CN201120169415U CN202587177U CN 202587177 U CN202587177 U CN 202587177U CN 201120169415 CN201120169415 CN 201120169415 CN 201120169415 U CN201120169415 U CN 201120169415U CN 202587177 U CN202587177 U CN 202587177U
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Abstract
The utility model relates to an image sensor and a signal processing circuit thereof. The signal processing circuit comprises at least two image capacitors configured to controllably obtain image signals of at least one pixel; at least two reset capacitors configured to controllably obtain reset signals of at least one pixel; a first switching unit configured to respond to control signals so as to couple at least one of the at least two image capacitors to at least one pixel in order to obtain image signals and make the at least two image capacitors share the obtained image signals; and a second switching unit configured to respond to the control signals so as to couple at least one of the at least two reset capacitors to at least one pixel in order to obtain reset signals and make the at least two reset capacitors share the obtained reset signals.
Description
Technical field
The utility model relates to the image sensor technologies field, and more specifically, the utility model relates to a kind of signal processing circuit of imageing sensor.
Background technology
Along with development of semiconductor, imageing sensor has been widely used in the field that various needs carry out digital imagery, for example in the electronic product such as digital camera, DV.According to the difference of opto-electronic conversion mode, imageing sensor can be divided into two types usually: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, Cmos image sensor has advantages such as volume is little, low in energy consumption, production cost is low; Therefore, cmos image sensor for example is easy to be integrated in the mancarried electronic aids such as mobile phone, notebook computer, panel computer, uses as the shooting module that the digital imagery function is provided.
Along with the progress of imageing sensor manufacturing process, in the prior art, the resolution of imageing sensor improves greatly, can reach 5,000,000 pixels or higher usually.Yet for the imageing sensor with high-resolution, the data volume that the lifting of image resolution ratio causes needs to be handled inevitably increases, and this can further increase the difficulty of successive image signal processing.For example in preview mode (Preview Mode), if keep image resolution ratio constant, can make that then the frame per second (Frame Rate) that image shows in the preview mode is low excessively, influence the preview effect.
In order to improve the frame per second that image shows in the preview mode; A kind of existing image-signal processing method abandons the part signal in the picture signal that imageing sensor gathers; For example only obtain the picture signal of all even number lines, and omit the picture signal of all odd-numbered lines.Though this image-signal processing method can reach the purpose that reduces the view data treating capacity, yet this tends to cause the excessive loss of image information, thereby can reduce the quality that image shows significantly.
The utility model content
It is thus clear that, a kind of image processing circuit and image processing method of imageing sensor need be provided, when reducing data processing amount and improving the image display frame rate, avoid the decline of image displaying quality as much as possible.
In order to address the above problem, in the embodiment aspect one of the utility model, a kind of signal processing circuit of imageing sensor is provided, comprising: at least two image electric capacity are configured to controllably obtain the picture signal of at least one pixel; At least two reset capacitance are configured to controllably obtain the reset signal of at least one pixel; First switch unit is configured to make in response to control signal in said at least two image electric capacity at least one to be couple to said at least one pixel obtaining picture signal, and makes said at least two image electric capacity share the picture signal of being obtained; And second switch unit; Be configured to make in said at least two reset capacitance at least one to be couple to said at least one pixel obtaining reset signal, and make said at least two reset capacitance share the reset signal of being obtained in response to control signal.
In one embodiment, also comprise amplifying unit, be used to amplify through the shared picture signal and the voltage difference of reset signal.
In one embodiment, said first switch unit also is configured to make in response to control signal in said at least two image electric capacity at least one to be couple to said amplifying unit so that the picture signal through sharing to be provided.
In one embodiment, said second switch unit also is configured to make in response to control signal in said at least two reset capacitance at least one to be couple to said amplifying unit so that the reset signal through sharing to be provided.
In one embodiment; Said first switch unit comprises at least three switches that are connected in series that are coupled between the input node and first output node; The wherein said switch that is connected in series has at least two intermediate nodes that are positioned at switch room, and each in said at least two image electric capacity is respectively coupled between said intermediate node and the reference potential.
In one embodiment; Said second switch unit comprises at least three switches that are connected in series that are coupled between the input node and second output node; The wherein said switch that is connected in series has at least two intermediate nodes that are positioned at switch room, and each in said at least two reset capacitance is respectively coupled between said intermediate node and the reference potential.
In one embodiment, said at least two image capacitance arrangement are to obtain the picture signal of different pixels; Said at least two reset capacitance are configured to obtain the reset signal of different pixels.
In one embodiment, said at least two pixels are positioned at the same row of image sensor pixel array.
In one embodiment, said at least two pixels pixel that is same tones in the image sensor pixel array.
In one embodiment, the capacitance of said at least two image electric capacity equates.
In one embodiment, said reset capacitance all equates with the capacitance of said image electric capacity.
In according to the utility model embodiment on the other hand, a kind of signal processing method of imageing sensor also is provided, comprise the steps: to provide at least two image electric capacity, it is configured to controllably obtain the picture signal of at least one pixel; At least two reset capacitance are provided, and it is configured to controllably obtain the reset signal of at least one pixel; In said at least two image electric capacity at least one is coupled to said at least one pixel to obtain picture signal; In said at least two reset capacitance at least one is coupled to said at least one pixel to obtain reset signal; Between said two image electric capacity, share the picture signal of being obtained at least; And between said two reference capacitances, share the reset signal obtained at least.
Among the embodiment aspect another, a kind of imageing sensor is provided also, has comprised pel array according to the utility model, and the signal processing circuit in the previous embodiment.
Compared with prior art; The mode that the signal processing circuit of the imageing sensor of the utility model adopts pixel to merge (binning) reduces the data volume that needs processing; Owing to can and share by different electric capacity collections from the signal of different pixels in the image sensor pixel array; This has been avoided the excessive loss of image information, thereby improves image displaying quality.In addition, the utility model mode of operation of can also effective compatible picture signal reading line by line.
The above characteristic of the utility model and other characteristics are partly set forth embodiment hereinafter clearly.
Description of drawings
Through with reference to the detailed description of being done below the advantages, can more easily understand characteristic, purpose and the advantage of the utility model to non-limiting example.Wherein, same or analogous Reference numeral is represented same or analogous device.
Fig. 1 shows a kind of 4T dot structure of imageing sensor;
Fig. 2 shows the signal processing circuit according to the imageing sensor of an embodiment of the utility model;
Fig. 3 shows the signal processing circuit according to the imageing sensor of another embodiment of the utility model, wherein further shows a kind of particular circuit configurations of first switch unit and second switch unit;
Fig. 4 shows the sequential chart of the control signal that is used for Fig. 3 signal processing circuit;
Fig. 5 shows the another kind of optional structure of switch unit;
Fig. 6 shows the signal processing method according to the imageing sensor of an embodiment of the utility model.
Embodiment
Go through enforcement and the use of embodiment below.Yet, should be appreciated that the specific embodiment discussed only exemplarily explanation implement and use the ad hoc fashion of the utility model, and the scope of unrestricted the utility model.
Cmos image sensor adopts the dot structure of 3T or 4T usually.The 3T dot structure is meant in each pixel of cmos image sensor pel array, except the photodiode that is used for sensitization, also comprises 3 transistors, is respectively that transistor and row selecting transistor are followed in reset transistor, source.The 4T dot structure has then further increased a transfering transistor on the basis of 3T dot structure.Signal processing circuit and processing method for the utility model; It both can be handled the signal of 3T dot structure imageing sensor; Also can handle the signal of 4T dot structure imageing sensor, among the embodiment below, be that example describes with the 4T dot structure only; But it should be understood that the imageing sensor of the other types that comprise 3T dot structure or other dot structures also belongs to the scope of the utility model.
Fig. 1 shows a kind of 4T dot structure of imageing sensor, comprises that photodiode 101, transfering transistor 102, reset transistor 103, source follow transistor 104 and row selecting transistor 105.
Wherein, photodiode 101 is coupled between the source electrode of first reference potential VSS (for example common electric voltage end or negative power end) and transfering transistor 102, is used to respond to light intensity and changes and formation corresponding charge signal.
The drain electrode of transfering transistor 102 links to each other with the grid that transistor 104 is followed in the source electrode and the source of reset transistor 103; The grid of this transfering transistor 102 is used for receiving transfer control signal TX; Under the control of shifting control signal TX; Transfering transistor 102 corresponding conducting or shutoffs, thus the charge signal that makes photodiode 101 responded to is read into the drain electrode of this transfering transistor 102, and by this drain electrode stored charge signal.
The drain electrode of reset transistor 103 is connected to the second reference potential VDD (for example positive power source terminal); Its grid is used to receive reseting controling signal RST; Under the control of this reseting controling signal RST; Reset transistor 103 corresponding conducting or shutoffs, thus to the grid that transistor 104 is followed in the source reset signal is provided.
The drain electrode that transistor 104 is followed in the source is connected to the second reference potential VDD, and its source electrode is connected to the drain electrode of row selecting transistor 105, is used for converting the charge signal that transfering transistor 102 obtains into voltage signal.The source electrode of row selecting transistor 105 links to each other with bit line BL; Its grid is used to receive array selecting signal RS; Under the control of this row selection signal RS; Row selecting transistor 105 is corresponding to be opened or closed, thus the source that makes follow the drain electrode of transistor 104 and be couple to bit line BL with being selected, and then the signal that transistor 104 conversions are followed in the source is exported by bit line BL.
Fig. 2 shows the signal processing circuit according to the imageing sensor of an embodiment of the utility model.In Fig. 2, also show the partial pixel in the image sensor pixel array, comprise first pixel 211 and second pixel 212.In the present embodiment, first pixel 211 and second pixel 212 are arranged in the same row of image sensor pixel array, and its output is couple to same bit line BL jointly.This signal processing circuit comprises:
The first image electric capacity 201 and the second image electric capacity 202 are configured to controllably obtain the picture signal of at least one pixel in the pel array, for example the picture signal of first pixel 211 and/or second pixel 212;
Need to prove; In practical application, according to the difference of concrete needs, signal processing circuit can also comprise the image electric capacity more than 3; These image electric capacity can obtain the picture signal of different pixels in the pel array respectively, and share the picture signal of being obtained; Similarly, this signal processing circuit can further include the reset capacitance more than 3, and these reset capacitance can be obtained the reset signal of different pixels in the pel array respectively, and shares the reset signal of being obtained.Like this, this signal processing circuit can merge the signal that 3 above pixels are gathered, and reduces image resolution ratio to reduce data processing amount.Be appreciated that for 3 above pixels the mode that its signal merges and 2 picture element signals merge similar.Therefore, in following embodiment, the signal processing circuit or the method that only merge with the signal to 2 pixels describe.Correspondingly, this signal processing circuit has 2 image electric capacity and 2 reset capacitance.
Need to prove that in addition 2 alleged pixels are the operations to a signal merging here.In practical application, signal processing circuit is the cycle to carry out ground to the processing of each pixel in the pel array, for example obtains the signal of each row with the mode of lining by line scan.Signal processing circuit can convert the digital signal of corresponding size into further with this signal amplification and through analog to digital conversion circuit (A/D Converter) after the once merging of accomplishing the signal that obtains; Afterwards, signal processing circuit can be obtained the signal of 2 other pixels (for example, 2 adjacent pixels of aforementioned 2 pixels) again and carry out the merging of the signal that obtains again.
In this article, term " obtains " and is meant between two pole plates of electric capacity and loads electrical potential difference, and so that this electric capacity is charged, said charging should make has stored and the corresponding quantity of electric charge of said electrical potential difference in the electric capacity.
In one embodiment, this signal processing circuit also comprises amplifying unit 207, is used to amplify through the shared picture signal and the voltage difference of reset signal.Therefore, first switch unit 205 also is configured to make in response to control signal in win the image electric capacity 201 and the second image electric capacity 202 at least one to be couple to this amplifying unit 207 so that the picture signal through sharing to be provided.Correspondingly, second switch unit 206 also is configured to make in response to control signal in said first reset capacitance 203 and second reset capacitance 204 at least one to be couple to this amplifying unit 207 so that the reset signal through sharing to be provided.
Particularly, can comprise more than one switch respectively in first switch unit 205 and second switch unit 206, wherein each switch has the control end that is used to receive control signal.Difference based on the reception control signal; Each switch is opened respectively or is closed; Thereby make each image electric capacity or reset capacitance be couple to pel array; And, perhaps make each image electric capacity or reset capacitance be couple to the input of amplifying unit 207, so that picture signal and the reset signal through sharing to be provided to amplifying unit 207 through picture signal or reset signal that bit line BL obtains correspondence.Wherein, bit line BL usually with pel array in a row pixel couple mutually, can obtain the signal that the different rows pixel is provided in this row pixel according to the difference of row selection signal RS.
Next the working method to this signal processing circuit details.
At first, signal processing circuit is gathered the reset signal of first pixel 211.Particularly, based on the control of row selection signal RS, first pixel 211 is selected, row selecting transistor 221 conductings wherein.Then, 222 conductings of reseting controling signal RST control reset transistor, first pixel 211 provides first reset signal to bit line BL.Simultaneously; Second switch unit 206 makes win reset capacitance 203 and/or second reset capacitance 204 be couple to this bit line BL in response to control signal; Thereby obtain this first reset signal, promptly stored the first reset charge Q corresponding in first reset capacitance 203 and/or second reset capacitance 204 with first reset signal
Ref1Be appreciated that during gathering first reset signal second switch unit 206 should make the disconnection that is connected between win reset capacitance 203 and second reset capacitance 204 and the amplifying unit 207.
Then, signal processing circuit is gathered the picture signal of first pixel 211.Particularly, based on the control of row selection signal RS, first pixel 211 is still selected, and row selecting transistor 221 wherein still is in conducting state.Shift 223 conductings of control signal TX control transfering transistor, first pixel 211 provides first picture signal to bit line BL.Simultaneously; First switch unit 205 makes win image electric capacity 201 and/or the second image electric capacity 202 be couple to this bit line BL in response to control signal; Thereby obtain this first picture signal, promptly stored the first image charge Q corresponding in the first image electric capacity 201 and/or the second image electric capacity 202 with first picture signal
Sig1Be appreciated that during gathering first picture signal first switch unit 205 should make the disconnection that is connected between win image electric capacity 201 and the second image electric capacity 202 and the amplifying unit 207; And first reset capacitance 203 and second reset capacitance 204 and bit line BL and with amplifying unit 207 between be connected all and break off.
Next, signal processing circuit is gathered the reset signal of second pixel 212.Particularly, based on the control of row selection signal RS, second pixel 212 is selected, row selecting transistor 226 conductings wherein.Then, 227 conductings of reseting controling signal RST control reset transistor, second pixel 212 provides second reset signal to bit line BL.Simultaneously, first switch unit 205 makes win reset capacitance 203 or second reset capacitance 204 be couple to this bit line BL in response to control signal, thereby obtains this second reset signal.Wherein, if first reset capacitance 203 and second reset capacitance 204 have all been obtained first reset signal, then can obtain second reset signal by in first reset capacitance 203 or second reset capacitance 204 any.If but only have one to obtain first reset signal in this first reset capacitance 203 and second reset capacitance 204, and then only can obtain second reset signal by the reset capacitance of not obtaining first reset signal, lose to avoid first reset signal.Like this, just stored the first reset charge Q in first reset capacitance 203 and second reset capacitance 204 respectively
Ref1And the second reset charge Q corresponding with second reset signal
Ref2Be appreciated that; During gathering second reset signal; Second switch unit 206 should make the disconnection that is connected between win reset capacitance 203 and second reset capacitance 204 and the amplifying unit 207, and the first image electric capacity 201 and the second image electric capacity 202 break off with amplifying unit 207 and with being connected all of bit line BL.
Afterwards, signal processing circuit is gathered the picture signal of second pixel 212.Particularly, based on the control of row selection signal RS, second pixel 212 is still selected, and row selecting transistor 226 wherein still is in conducting state.Shift 228 conductings of control signal TX control transfering transistor, second pixel 212 provides second picture signal to bit line BL.Simultaneously, second switch unit 206 makes win image electric capacity 201 and/or the second image electric capacity 202 be couple to this bit line BL in response to control signal, thereby obtains this second picture signal.Wherein, if the first image electric capacity 201 and the second image electric capacity 202 have all obtained first picture signal, then can obtain second picture signal by in the first image electric capacity 201 or the second image electric capacity 202 any.If but only have one to obtain first picture signal in this first image electric capacity 201 and the second image electric capacity 202, and then only can obtain second picture signal by the image electric capacity that does not obtain first picture signal, lose to avoid first picture signal.Like this, just stored the first image charge Q in the first image electric capacity 201 and the second image electric capacity 202 respectively
Sig1And the second image charge Q corresponding with second picture signal
Sig2Be appreciated that; During gathering second picture signal; First switch unit 205 should make the disconnection that is connected between win image electric capacity 201 and the second image electric capacity 202 and the amplifying unit 207, and first reset capacitance 203 and second reset capacitance 204 and bit line BL and with amplifying unit 207 between be connected all and break off.
Through above-mentioned steps, accomplished obtaining of each pixel image signal and reset signal.Then; First switch unit 205 makes win image electric capacity 201 and the second image electric capacity 202 be connected in parallel in response to control signal, and second switch unit 206 makes win reset capacitance 203 and second reset capacitance 204 be connected in parallel in response to control signal.
Like this, the first image charge Q
Sig1With the second image charge Q
Sig2Between the first image electric capacity 201 and the second image electric capacity 202, share, promptly redistribute, and form new picture signal according to the ratio of capacitance.Obtain second picture signal and the second image electric capacity 202 obtains first picture signal is example with the first image electric capacity 201.After the merging of carrying out said image signal voltage, the voltage of the picture signal on the first image electric capacity 201 and the second image electric capacity 202 should equate, is specially (C
Sig1U
Sig2+ C
Sig2U
Sig1)/(C
Sig1+ C
Sig2), C wherein
Sig1The capacitance of representing the first image electric capacity 201, C
Sig2The capacitance of representing the second image electric capacity 202, U
Sig1The voltage of representing first picture signal, U
Sig2The voltage of representing second picture signal.
In practical application, what the capacitance of the first image electric capacity 201 and the second image electric capacity 202 can be according to application demand is different and different, and promptly first picture signal is different with the weight of second picture signal in signal merges.In an embodiment according to the utility model, this first image electric capacity 201 can equate that with the capacitance of the second image electric capacity 202 like this, the magnitude of voltage of the picture signal after merging is (U
Sig2+ U
Sig1)/2.
Similarly, the first reset charge Q
Ref1With the second reset charge Q
Ref2Between first reset capacitance 203 and second reset capacitance 204, share, and form new reset signal.Be appreciated that in the process that electric charge is shared first switch unit 205 and second switch unit 206 should make the disconnection that is connected between each electric capacity and amplifying unit 207 and the pixel.
Through sharing of charge signal in the electric capacity, realized merging corresponding to the picture signal of different pixels.The caused decrease in image quality of picture signal of traditional omission (skipping) delegation or multirow pixel had both been avoided in the merging of this picture signal; For example crenellated phenomena is serious in the image; Reduced the data volume of successive image signal processing again effectively; Thereby can improve the frame per second that image shows, particularly in the application scenarios of similar preview mode.
Accomplish signal shared (promptly merging) afterwards; Can further picture signal of being shared and reset signal be offered amplifying unit 207; Particularly; First switch unit 205 makes in win the image electric capacity 201 and the second image electric capacity 202 at least one be couple to an input of amplifying unit 207 in response to control signal, so that the picture signal through sharing to be provided; And second switch unit 206 makes in the win reset capacitance 203 and second reset capacitance 204 at least one be couple to another input of amplifying unit 208 in response to control signal, so that the picture signal through sharing to be provided.Wherein, Than the playback mode that two image electric capacity (and two reset capacitance) all is couple to amplifying unit; Only couple one of them image electric capacity (and a reset capacitance) and be equivalent to reduce the capacitance of amplifying unit 207 inputs, thereby make gain amplifier reduce to the playback mode of amplifying unit 207.Especially; In a preferred embodiment; Image electric capacity all equates with the capacitance of reset capacitance, and in this case, the gain amplifier that only couples an image/reset capacitance playback mode only has 1/2 of the gain amplifier that couples two images/reset capacitance playback mode.When outside light intensity was higher, the reduction of gain amplifier can be avoided the image overexposure, thereby improved picture quality.
In the present embodiment, the signal that this signal processing circuit is used to accomplish between the different pixels signal merges, and the pictures different capacitance arrangement is to obtain the picture signal of different pixels, and different reset capacitance is configured to obtain the reset signal of different pixels.But in practical application, this signal processing circuit still can compatible not carried out the mode of operation that signal merges, for example in picture photographing mode.
In addition, because this signal processing circuit has a plurality of controlled image/reset capacitance and come acquired signal, so it can come read output signal with flexible way more.
Particularly, when a pixel is carried out signals collecting, can two image/reset capacitance all be couple to this pixel to obtain corresponding signal; In this case; When read output signal, can two image/reset capacitance all be couple to amplifying unit 207, perhaps only an image/reset capacitance is couple to amplifying unit 207; Wherein, the gain amplifier of preceding kind of playback mode is the latter's a twice.On the other hand, also can only couple an image/reset capacitance and come acquired signal, in this case to pixel; When read output signal; Can between two image/reset capacitance, share the signal of being gathered, and two image/reset capacitance all are couple to amplifying unit 207, because another image/reset capacitance acquired signal not; So reduce half through sharing back voltage of signals value, and the also corresponding reduction of gain amplifier.
Normally, in imageing sensor, the charge signal of pixel in pel array induction is selected by row and is obtained, and therefore, for the first above-mentioned pixel and second pixel, it is two pixels that are positioned at same row in the two capable pixels of pel array.In an embodiment according to the utility model, this imageing sensor is the black and white image transducer, and then first pixel and second pixel are two pixels in the adjacent two row pixels in the pel array.In another embodiment; This imageing sensor is a color image sensor; Baeyer RGB (Bayer RGB) imageing sensor for example, then first pixel and second pixel are the neighbors that the same row of being arranged in of pel array belong to same tone, adjacent two redness (R) pixel in the for example same row.
Need to prove that at least two pixels in the previous embodiment are the pixels that are arranged in the same row of pel array, its shared same bit line comes to an amplifying unit signal to be provided.Two pixels or the signal between more pixels in different lines merge, because it adopts different bit lines to come to different amplifying units signal to be provided, pictures different/reset capacitance is obtained and storage signal and different amplifying units has; Therefore; For the pixel that is arranged in different lines, when read output signal, can corresponding bit lines be interconnected; And then make corresponding image/reset capacitance parallelly connected mutually to share signal, can realize the merging of signal.
Fig. 3 shows the signal processing circuit according to the imageing sensor of another embodiment of the utility model, wherein further shows a kind of particular circuit configurations of first switch unit and second switch unit.As before illustrated, first switch unit and second switch unit can comprise a plurality of series connection and/or the gate-controlled switch that is connected in parallel, and the conducting state of switch makes image/reset capacitance be couple on the different nodes through changing wherein.In practical application, the control signal that gate-controlled switch received can be by control module independently, and for example micro-control unit (MCU) provides.
Particularly, this signal processing circuit comprises the first image electric capacity 301, the second image electric capacity 302, first reset capacitance 303, second reset capacitance 304, first switch unit 312 and second switch unit 313.
Wherein, first switch unit 312 is coupled between the input and first output, comprises first switch 305, second switch 306 and the 3rd switch 307 that are connected in series; Having first intermediate node, 361, the first image electric capacity 301 between first switch 305 and the second switch 306 promptly is coupled between this first intermediate node 361 and the first reference potential VSS; Having second intermediate node, 362, the second image electric capacity 302 between second switch 306 and the 3rd switch 307 promptly is coupled between this second intermediate node 362 and the first reference potential VSS.This first reference potential VSS for example is the common potential end, or negative power end.
Second switch unit 312 is coupled between the input and second output, comprises the 4th switch 308, the 5th switch 309 and the 6th switch 310 that are connected in series; Having the 3rd intermediate node 363, the first reset capacitance 303 between the 4th switch 308 and the 5th switch 309 promptly is coupled between the 3rd intermediate node 363 and the first reference potential VSS; Having the 4th intermediate node 364, the second reset capacitance 304 between the 5th switch 309 and the 6th switch 310 promptly is coupled between the 4th intermediate node 364 and the first reference potential VSS.
Be appreciated that for the image electric capacity more than 3, first switch unit 312 switch more than 4 of can connecting, and make each image electric capacity be respectively coupled between the intermediate node and the first reference potential VSS.Similarly, for the reset capacitance more than 3, second switch unit 313 switch more than 4 of can connecting, and make each reset capacitance be respectively coupled between the intermediate node and first reference potential.
In concrete embodiment; First switch 305, second switch 306, the 3rd switch 307, the 4th switch 308, the 5th switch 309 and the 6th switch 310 all can adopt mos transistor switch; For example nmos transistor switch or PMOS transistor switch; The grid of this MOS transistor is as the control end that receives control signal, and the source electrode of MOS transistor then is used to transmit signal with drain electrode.
Fig. 4 shows the sequential chart of the control signal that is used for Fig. 3 signal processing circuit.Next, in conjunction with Fig. 3 and Fig. 4 the imageing sensor of an embodiment of the utility model and the work of signal processing circuit thereof are further explained.
Each control signal among Fig. 4 is carried in corresponding switch or transistorized control end respectively.Particularly, row selection signal RS is loaded in the grid of the row selecting transistor of each pixel in the pel array; Reset signal RST is loaded in the grid of the reset transistor of each pixel; Shift the grid that control signal TX is loaded in the transfering transistor of each pixel; The first control signal SHR is loaded in the control end of the 4th switch 308; The second control signal SHS is loaded in the control end of first switch 305; The 3rd control signal EQ is loaded in the control end of second switch 306 and the 5th switch 309; The 4th control signal SEL is loaded in the control end of the 3rd switch 307 and the 6th switch 310.
At first, at the first period T1, obtain the first reset signal V of first pixel 321 respectively by the second image electric capacity 302 and second reset capacitance 304
Ref1With the first picture signal V
Sig1
Particularly, the 3rd control signal EQ is remained valid, this makes second switch 306 and the 5th switch 309 keep conducting, and the first image electric capacity 301 and the second image electric capacity 302 are connected in parallel, and first reset capacitance 303 and second reset capacitance 304 are connected in parallel; Simultaneously, 321 corresponding row selection signal RS remain valid with first pixel, and this makes row selecting transistor 345 conductings of the pixel 321 of winning, thereby first pixel 321 is connected to bit line BL.In the case; Again successively reset signal RST, the first control signal SHR, shift control signal TX and the second control signal SHS is set to effectively, thereby turns on reset transistor 343, the 4th switch 308, transfering transistor 342 and first switch 305 successively.
Under above-mentioned SECO, the conducting of reset transistor 343 makes bit line BL receive first reset signal.And then, the conducting of the 4th switch 308 and the 5th switch 309 makes win reset capacitance 303 and second reset capacitance 304 obtain the first reset signal V simultaneously
Ref1, second reset capacitance 304 is able to storage based on the said first reset signal V
Ref1The first reset charge Q that generates
Ref1, i.e. C
Ref2V
Ref1, C wherein
Ref2The capacitance of representing second reset capacitance 304.Afterwards, the conducting of transfering transistor 342 makes bit line BL receive the first picture signal V
Sig1And then, the conducting of first switch 305 and second switch 306 makes win image electric capacity 301 and the second image electric capacity 302 obtain the first picture signal V simultaneously
Sig1, the second image electric capacity 302 is able to storage based on the said first picture signal V
Sig1The first image charge Q that generates
Sig1, i.e. C
Sig2V
Sig1, C wherein
Sig2The capacitance of representing the second image electric capacity 302.
Afterwards, at the second period T2, obtain the second reset signal V respectively by the first image electric capacity 301 and first reset capacitance 303
Ref2With the first picture signal V
Sig2
Particularly, the 3rd control signal EQ is kept invalid, this makes second switch 306 and the 5th switch 309 keep turn-offing, and the first image electric capacity 301 and the second image electric capacity 302 break off, and first reset capacitance 303 and second reset capacitance 304 are broken off; Simultaneously, the row selection signal RS that second pixel 322 is corresponding remain valid, and this makes row selecting transistor 350 conductings of second pixel 322, thereby second pixel 322 is connected to bit line BL.In the case; Again successively reset signal RST, the first control signal SHR, shift control signal TX and the second control signal SHS is set to effectively, thereby turns on reset transistor 348, the 4th switch 308, transfering transistor 347 and first switch 305 successively.
Under above-mentioned SECO, the conducting of reset transistor 348 makes bit line BL receive the second reset signal V
Ref2And then, 308 conductings of the 4th switch make the reset capacitance 303 of winning obtain the second reset signal V
Ref2, first reset capacitance 303 is able to storage based on the said second reset signal V
Ref2The second reset charge Q that generates
Ref2, i.e. C
Ref1V
Ref2, C wherein
Ref1The capacitance of representing second reset capacitance 303.Afterwards, the conducting of transfering transistor 347 makes bit line BL correspondingly obtain the second picture signal V of second pixel 322
Sig2And then, the conducting of first switch 305 makes the image electric capacity 301 of winning obtain the second picture signal V
Sig2, the first image electric capacity 301 is able to storage based on the said second picture signal V
Sig2The second image charge Q that generates
Sig2, i.e. C
Sig1V
Sig2, C wherein
Sig1The capacitance of representing the first image electric capacity 301.
Can find out that after the said first period T1 and the second period T2, the first image electric capacity 301 and the second image electric capacity 302 have obtained respectively based on the second picture signal V
Sig2With the first picture signal V
Sig1The second image charge Q that generates
Sig2With the first image charge Q
Sig1, first reset capacitance 303 and second reset capacitance 304 have then obtained the second reset signal V respectively
Ref2With based on the first reset signal V
Ref1The second reset charge Q that generates
Ref2With the first reset charge Q
Ref1These electric charges have reflected the size of first pixel 321 and second pixel, 322 picture signals and reset signal respectively.
Next, at phase III T3, respectively to the first image electric capacity 301 and the second image electric capacity 302, and first reset capacitance 303 and second reset capacitance 304 are carried out electric charge and are shared.
Particularly, only the 3rd control signal EQ is set to effectively, and this makes win image electric capacity 301 and the second image electric capacity 302 be connected in parallel the first image charge Q that is obtained
Sig1With the second image charge Q
Sig2Redistribute betwixt, and the image electric capacity 301 of winning is equated with magnitude of voltage between the second image electric capacity, 302 two-plates.Similarly, the second image electric capacity 303 and second reset capacitance 304 also are connected in parallel, the first reset charge Q that is obtained
Ref1With the second reset charge Q
Ref2Redistribute betwixt, and the reset capacitance 303 of winning is equated with magnitude of voltage between second reset capacitance, 304 two-plates.
Then, at stage T4, the 4th control signal SEL is by showing effect, and the image/reset signal that makes each row merge is read successively.The 4th control signal SEL is set to effectively make corresponding the 3rd switch 307 and 310 conductings of the 6th switch; The 3rd control signal EQ is set to effectively so that second switch 306 and the 5th switch conduction simultaneously; Thereby make win image electric capacity 301 and the second image electric capacity 302 be connected to an input of amplifying unit 314; And first reset capacitance 303 and second reset capacitance 304 are connected to another input of amplifying unit 314, and then reset signal on it and sub image signal are supplied with amplifying unit 314 indescribably.Amplifying unit 314 amplifies the voltage difference of picture signal and reset signal further, and the output voltage that will pass through amplification offers follow-up signal processing circuit.
Alternatively; At stage T4; Can also be set to invalid (not shown) so that second switch 306 and the 5th switch 309 break off by the 3rd control signal EQ; Thereby make the second image electric capacity 302 and second reset capacitance 304 be connected respectively to two inputs of amplifying unit 314, and reset signal and the picture signal that is obtained is provided.
As aforementioned, if need the signal of different lines pixel be merged, then can when reading, make needs pairing the 4th control signal of the row of merging simultaneously effectively.Like this, image/reset capacitance that each row is corresponding is connected in the input of amplifying unit in parallel, thereby realizes the merging of signal.
Should be appreciated that; The structure of first switch unit and second switch unit is merely example in the utility model, and any other can make each electric capacity be connected respectively to the different pixels of pel array and the switching circuit structure of obtaining image/reset signal all belongs to the scope of the utility model.Fig. 5 promptly shows the another kind of optional structure of switch unit, and two electric capacity that it connected are controlled by a switch of correspondence respectively.Adopt the working method and the previous embodiment of signal processing circuit of switch unit of this kind structure basic identical, repeat no more at this.
With reference to figure 6, show signal processing method according to the imageing sensor of an embodiment of the utility model, may further comprise the steps:
Execution in step S602 provides at least two image electric capacity, and it is configured to controllably obtain the picture signal of at least one pixel;
Execution in step S604 provides at least two reset capacitance, and it is configured to controllably obtain the reset signal of at least one pixel;
Execution in step S606 is coupled to said at least one pixel to obtain picture signal with in said at least two image electric capacity at least one;
Execution in step S608 is coupled to said at least one pixel to obtain reset signal with in said at least two reset capacitance at least one;
Execution in step S610 shares the picture signal of being obtained at least between said two image electric capacity; And
Execution in step S612 shares the reset signal of being obtained at least between said two reference capacitances.
In an embodiment of the utility model, after step S610 and S610, also comprise: in said two image electric capacity at least one is couple to amplifying unit so that the picture signal through sharing to be provided; And in said two reset capacitance at least one be couple to amplifying unit so that the reset signal through sharing to be provided.
In an embodiment of the utility model, said step S606 also comprises: said at least two image electric capacity are coupled to pixels with different to obtain corresponding picture signal; Correspondingly, said step S608 also comprises: said at least two image electric capacity are coupled to pixels with different to obtain corresponding picture signal.
In an embodiment of the utility model, said pixel is positioned at the same row of image sensor pixel array.
In an embodiment of the utility model, said pixel is the pixel of same tone in the image sensor pixel array.
In an embodiment of the utility model, the step of obtaining said reset signal is before the step of obtaining said picture signal, to carry out.
In an embodiment of the utility model, the capacitance of said at least two image electric capacity equates.
In an embodiment of the utility model, said reset capacitance all equates with the capacitance of said image electric capacity.
Although in accompanying drawing and aforesaid description sets forth in detail with the utility model has been described, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The utility model is not limited to above-mentioned execution mode.
The those skilled in the art in those present technique fields can be through research specification, disclosed content and accompanying drawing and appending claims, and understanding and enforcement are to other changes of the execution mode of disclosure.In claim, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number.In the practical application of utility model, the function of a plurality of technical characterictics of being quoted during a part possibility enforcement of rights requires.Any Reference numeral in the claim should not be construed as the restriction to scope.
Claims (12)
1. the signal processing circuit of an imageing sensor is characterized in that, comprising:
At least two image electric capacity are configured to controllably obtain the picture signal of at least one pixel;
At least two reset capacitance are configured to controllably obtain the reset signal of at least one pixel;
First switch unit is configured to make in response to control signal in said at least two image electric capacity at least one to be couple to said at least one pixel obtaining picture signal, and makes said at least two image electric capacity share the picture signal of being obtained; And
Second switch unit is configured to make in response to control signal in said at least two reset capacitance at least one to be couple to said at least one pixel obtaining reset signal, and makes said at least two reset capacitance share the reset signal of being obtained.
2. signal processing circuit according to claim 1 is characterized in that, also comprises amplifying unit, is used to amplify through the shared picture signal and the voltage difference of reset signal.
3. signal processing circuit according to claim 2; It is characterized in that said first switch unit also is configured to make in response to control signal in said at least two image electric capacity at least one to be couple to said amplifying unit so that the picture signal through sharing to be provided.
4. signal processing circuit according to claim 2; It is characterized in that said second switch unit also is configured to make in response to control signal in said at least two reset capacitance at least one to be couple to said amplifying unit so that the reset signal through sharing to be provided.
5. signal processing circuit according to claim 1; It is characterized in that; Said first switch unit comprises at least three switches that are connected in series that are coupled between the input node and first output node; The wherein said switch that is connected in series has at least two intermediate nodes that are positioned at switch room, and each in said at least two image electric capacity is respectively coupled between said intermediate node and the reference potential.
6. signal processing circuit according to claim 1; It is characterized in that; Said second switch unit comprises at least three switches that are connected in series that are coupled between the input node and second output node; The wherein said switch that is connected in series has at least two intermediate nodes that are positioned at switch room, and each in said at least two reset capacitance is respectively coupled between said intermediate node and the reference potential.
7. signal processing circuit according to claim 1 is characterized in that, said at least two image capacitance arrangement are to obtain the picture signal of different pixels; Said at least two reset capacitance are configured to obtain the reset signal of different pixels.
8. signal processing circuit according to claim 1 is characterized in that, said at least two pixels are positioned at the same row of image sensor pixel array.
9. signal processing circuit according to claim 1 is characterized in that, said at least two pixels are pixels of same tone in the image sensor pixel array.
10. signal processing circuit according to claim 1 is characterized in that, the capacitance of said at least two image electric capacity equates.
11. signal processing circuit according to claim 10 is characterized in that, said reset capacitance all equates with the capacitance of said image electric capacity.
12. an imageing sensor is characterized in that, comprises pel array, and according to each described signal processing circuit in the claim 1 to 11.
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| CN 201120169415 CN202587177U (en) | 2011-05-25 | 2011-05-25 | Image sensor and signal processing circuit thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115442548A (en) * | 2021-06-04 | 2022-12-06 | 豪威科技股份有限公司 | Bit line control to support merged mode for pixel arrays with phase detection autofocus and image sensing photodiodes |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115442548A (en) * | 2021-06-04 | 2022-12-06 | 豪威科技股份有限公司 | Bit line control to support merged mode for pixel arrays with phase detection autofocus and image sensing photodiodes |
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