WO2023011092A1

WO2023011092A1 - Image sensor, camera assembly and mobile terminal

Info

Publication number: WO2023011092A1
Application number: PCT/CN2022/104060
Authority: WO
Inventors: 杨鑫
Original assignee: Oppo广东移动通信有限公司
Priority date: 2021-08-04
Filing date: 2022-07-06
Publication date: 2023-02-09
Also published as: CN113676625A; CN113676625B

Abstract

An image sensor, comprising: a pixel array (11), which comprises a plurality of pixels (110), wherein a pixel circuit (111) of each pixel (110) comprises a plurality of photoelectric conversion elements (1111) arranged corresponding to the pixel (110), and the pixel circuit (111) is used for outputting charges generated by the photoelectric conversion elements (1111) corresponding to the same pixel (110); a conversion circuit (141), which comprises a plurality of analog-to-digital converters (1411) respectively connected to the plurality of pixel circuits (111) on a one-to-one basis, wherein each analog-to-digital converter (1411) is configured with output modes of various resolutions, and the conversion circuit (141) is used for converting an analog signal corresponding to the charges into a digital signal; and a processing circuit (15), which is connected to the conversion circuit (141), and is used for performing, according to an output resolution of the analog-to-digital converter (1411) and by taking a preset number of bytes as a coding unit, coding processing on digital signals output from at least two analog-to-digital converters (1411).

Description

Image sensors, camera components and mobile terminals

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 2021108920952 titled "Image sensor, camera assembly and mobile terminal" filed with the China Patent Office on August 4, 2021, the entire contents of which are hereby incorporated by reference in this application .

technical field

The present application relates to the field of image technology, in particular to an image sensor, a camera assembly and a mobile terminal.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute prior exemplary art.

A camera may be installed in a terminal such as a mobile phone to realize a camera function. An image sensor for receiving light may be arranged in the camera.

As demand for image sensors increases, techniques for improving the quality of images generated by the image sensors are being developed. When a general image sensor reads out digital signals of different pixel color components (for example, pixel R, pixel G, pixel B), power consumption is high.

Contents of the invention

According to various embodiments of the present application, an image sensor, a camera assembly, and a mobile terminal are provided.

An image sensor comprising:

A pixel array, including a plurality of pixels, the pixel circuit of each pixel includes a plurality of photoelectric conversion elements corresponding to the pixel, and the pixel circuit is used to output the charge generated by at least one photoelectric conversion element corresponding to the pixel;

A conversion circuit, including a plurality of analog-to-digital converters respectively connected to a plurality of pixel circuits in one-to-one correspondence, each of the analog-to-digital converters is configured with output modes with multiple resolutions, and the conversion circuit is used to convert the charge The corresponding analog signal is converted into a digital signal;

A processing circuit, connected to the conversion circuit, configured to encode the digital signals output by at least two of the analog-to-digital conversion circuits with a preset number of bytes as the encoding unit according to the output resolution of the analog-to-digital converter Perform encoding processing, wherein the byte includes preset bits.

A camera assembly, comprising:

lens; and

In the aforementioned image sensor, the image sensor is capable of receiving light passing through the lens.

A mobile terminal, comprising:

casing; and

In the foregoing camera assembly, the camera assembly is combined with the casing.

The above-mentioned image sensor, camera assembly and mobile terminal, the image sensor includes a pixel array, a conversion circuit and a processing circuit, wherein the pixel array includes a plurality of pixels, and the pixel circuit of each pixel includes a plurality of photoelectric conversion elements corresponding to the pixels, The pixel circuit is used to output the charge generated by at least one of the photoelectric conversion elements corresponding to the pixel; the conversion circuit includes a plurality of analog-to-digital converters, and each of the analog-to-digital converters is configured with outputs of various resolutions mode, the conversion circuit is used to convert the analog signal corresponding to the charge into a digital signal, by configuring the output resolution of each analog-to-digital converter, and based on the output resolution of each analog-to-digital converter, the processing circuit can convert at least The digital signals output by the two analog-to-digital conversion circuits are encoded with a preset number of bytes as the encoding unit, so that the multiplexing of multiple bytes can be realized, thereby reducing the amount of data transmission of the image sensor and Power consumption, and can improve the compression ratio of digital data.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of an image sensor in an embodiment;

Fig. 2 is a schematic diagram of arrangement of a pixel array in an embodiment;

Fig. 3 is a schematic cross-sectional view of a pixel in an embodiment;

Fig. 4 is a schematic circuit diagram of a pixel circuit in an embodiment;

5 is a schematic circuit diagram of a pixel circuit in another embodiment;

6 is a schematic circuit diagram of an image sensor in another embodiment;

Fig. 7 is a schematic diagram of the arrangement of the smallest repeating unit in the pixel array in one embodiment;

8 to 9 are working principle diagrams of pixel units based on conversion units in some embodiments;

FIG. 10 is a schematic diagram of a data structure output based on a full-resolution output mode in an embodiment;

Fig. 11 is a schematic diagram of the data structure after the processing circuit in Fig. 10 encodes the digital signals of the two analog-to-digital converters;

Fig. 12 is a schematic diagram of the data structure output based on the first-level combined output mode in an embodiment;

Fig. 13 is a schematic diagram of the data structure after the processing circuit in Fig. 12 encodes the digital signals of the two analog-to-digital converters;

14 to 15 are working principle diagrams of pixel units based on conversion units in some embodiments;

Fig. 16 is a schematic diagram of conversion from the first-level combined output mode to the second-level combined output mode in one embodiment;

Fig. 17 is a schematic diagram of the data structure after the processing circuit encodes the digital signals of two analog-to-digital converters when the image sensor is in the second-level combined output mode in one embodiment;

Fig. 18 is a working principle diagram of a pixel unit based on a conversion unit in another embodiment;

Fig. 19 is a working principle diagram of a pixel unit based on a conversion unit in another embodiment;

Figure 20 is a schematic diagram of a camera assembly in one embodiment;

Figure 21 is a schematic diagram of a mobile terminal in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first conversion circuit could be termed a second conversion circuit, and, similarly, a second conversion circuit could be termed a first conversion circuit, without departing from the scope of the present application. Both the first conversion circuit and the second conversion circuit are conversion circuits, but they are not the same conversion circuit.

As shown in FIG. 1 , an embodiment of the present application provides an image sensor. The image sensor 10 includes a pixel array 11 , a vertical driving unit 12 , a control unit 13 , a column processing unit 14 and a horizontal driving unit 15 .

Wherein, the image sensor 10 may adopt a complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor) photosensitive element or a charge-coupled device (CCD, Charge-coupled Device) photosensitive element.

As shown in FIG. 2 , the pixel array 11 includes a plurality of pixels 110 arranged two-dimensionally in an array (ie arranged in a two-dimensional matrix), and each pixel 110 may include a plurality of sub-pixels. Specifically, each pixel 110 may include n*m sub-pixels. Wherein, one of n and m is a positive integer greater than or equal to 1, and the other of m and n is a positive integer greater than or equal to 2, wherein n can be understood as the number of rows of sub-pixels in the same pixel 110, m is the column number of sub-pixels in the same pixel 110 . Exemplarily, each pixel 110 includes 4 sub-pixels, and the 4 sub-pixels are arranged in a 2*2 array, that is, m=n=2. In the embodiment of the present application, the value ranges of m and n are not further limited.

Each sub-pixel included in the same pixel 110 has the same color, and each sub-pixel may be one of panchromatic sub-pixel W, first-color sub-pixel A, second-color sub-pixel B, and third-color sub-pixel C. Exemplarily, the sub-pixel A of the first color may be a red sub-pixel R; the sub-pixel B of the second color may be a green sub-pixel G; the sub-pixel C of the third color may be a blue sub-pixel Bu.

The vertical driving unit 12 includes a shift register and an address decoder. The vertical drive unit 12 includes readout scanning and reset scanning functions. The readout scan refers to sequentially scanning the unit pixels 110 row by row, and reading signals from the unit pixels 110 row by row. For example, the signal output by each pixel 110 in the row of pixels 110 that is selected and scanned is transmitted to the column processing unit 14 . The reset scan is for resetting the charge, and the photocharge of the photoelectric conversion element is discarded so that accumulation of new photocharge can be started.

For example, the signal processing performed by the column processing unit 14 is correlated double sampling (CDS) processing. In the CDS process, the reset level and signal level output from each pixel 110 in the row of selected pixels 110 are taken out, and the level difference is calculated. Thus, signals of the pixels 110 in one row are obtained. The column processing unit 14 may have an analog-to-digital (A/D) conversion function for converting an analog pixel 110 signal into a digital format, and a function of performing an averaging operation on a plurality of digital signals after the analog-to-digital conversion.

For example, the horizontal driving unit 15 includes a shift register and an address decoder. The horizontal driving unit 15 sequentially scans the pixel array 11 column by column. Through the selection scanning operation performed by the horizontal driving unit 15, each column of pixels 110 is sequentially processed by the column processing unit 14, and is sequentially output.

For example, the control unit 13 configures timing signals according to the operation mode, and uses various timing signals to control the vertical driving unit 12 , the column processing unit 14 and the horizontal driving unit 15 to work together.

As shown in FIG. 3 , the pixel 110 includes a pixel circuit 111 , a filter 112 , and a microlens 113 . Along the light-receiving direction of the pixel 110 , the microlens 113 , the filter 112 , and the pixel circuit 111 are arranged in sequence. The microlens 113 is used to gather light, and the filter 112 is used to allow light of a certain wavelength to pass through and filter out light of other wavelengths. The pixel circuit 111 is used to convert the received light into an electrical signal, and provide the generated electrical signal to the column processing unit 14 shown in FIG. 1 .

As shown in FIG. 4 and FIG. 5 , the pixel circuit 111 in FIG. 4 and FIG. 5 can be applied in each pixel 110 in the pixel array 11 shown in FIG. 2 . The working principle of the pixel circuit will be described below with reference to FIG. 2 to FIG. 5 .

The pixel circuit 111 is used to transfer the charge accumulated and generated by at least one photoelectric conversion element 1111 in the same pixel 110 to the floating diffusion region FD, and selectively turn on at least one of the output terminals according to the accumulated charge to output the An analog signal corresponding to the charge in the floating diffusion FD. The pixel circuit 111 includes a plurality of photoelectric conversion elements 1111 corresponding to sub-pixels one by one, a plurality of transfer transistors 1112 and a readout circuit 1113 .

The number and arrangement of the photoelectric conversion elements 1111 are the same as the number and arrangement of the sub-pixels. Each photoelectric conversion element 1111 converts light into charges according to the intensity of light incident thereon. The number of transfer transistors 1112 is equal to the number of photoelectric conversion elements 1111 . The plurality of transfer transistors 1112 are respectively connected to the plurality of photoelectric conversion elements 1111 in one-to-one correspondence. A plurality of photoelectric conversion elements 1111 in the same pixel 110 share the floating diffusion FD in the pixel circuit 111 . For example, the photoelectric conversion element 1111 includes a photodiode, the anode of the photodiode is connected to the ground, for example, and the cathode of the photodiode is connected to the floating diffusion region FD via the transfer transistor 1112, and the transfer transistor 1112 is used to transfer the charge generated by each of the photoelectric conversion elements 1111 to transferred to the floating diffusion FD.

The input terminal of the readout circuit 1113 is connected to the floating diffusion region FD, and is used for outputting the charge transferred into the floating diffusion region FD to the column processing unit 14 . Specifically, the readout circuit 1113 includes a reset transistor 11131 , an amplification transistor (also referred to as a follower transistor) 11132 , and a selection transistor 11133 . Wherein, the reset transistor 11131 is connected to the floating diffusion region FD, and is used to reset the floating diffusion region FD; the amplification transistor 11132 is connected to the floating diffusion region FD, and is used to amplify the charge in the floating diffusion region FD , to obtain the amplified charge; the selection transistor 11133, connected to the amplifying transistor 11132, is used to read the amplified charge to the output circuit.

For ease of description, the pixel 110 includes four sub-pixels arranged in 2*2 as an example for description. Specifically, the pixel circuit 111 may include four photoelectric conversion elements 1111 , four transfer transistors 1112 , a floating diffusion region FD, a reset transistor 11131 , an amplification transistor 11132 , and a selection transistor 11133 . The pixel circuit 111 can also be configured with four exposure control lines for providing exposure control signals, and each exposure control line can be correspondingly connected to gates ( TG1 , TG2 , TG3 , TG4 ) of four transfer transistors 1112 . When a pulse of an active level (for example, VPIX level) is transmitted to the gate of the transfer transistor 1112 through the exposure control line, the transfer transistor 1112 is turned on, and the transfer transistor 1112 transfers the charge photoelectrically converted by the photodiode to the floating diffusion region FD.

The drain of the reset transistor 11131 is connected to the pixel 110 power supply VPIX. The source of the reset transistor 11131 is connected to the floating diffusion FD. Before the charge is transferred from the photodiode to the floating diffusion FD, a pulse of effective reset level is transmitted to the gate RG of the reset transistor 11131 via the reset line, and the reset transistor 11131 is turned on. The reset transistor 11131 resets the floating diffusion FD to the pixel 110 power supply VPIX.

The gate of the amplification transistor 11132 is connected to the floating diffusion FD. The drain of the amplification transistor 11132 is connected to the pixel 110 power supply VPIX. After the floating diffusion FD is reset by the reset transistor 11131 , the amplifying transistor 11132 outputs an analog signal corresponding to the reset level and the charge through the output terminal via the selection transistor 11133 . After the charge of the photodiode is transferred by the transfer transistor 1112 , the amplification transistor 11132 outputs an analog signal through the output terminal via the selection transistor 11133 .

Each pixel circuit 111 may be configured with a column control line COL. The gate SEL of the selection transistor 11133 is used to receive the selection control signal, the drain of the selection transistor 11133 is connected to the source of the amplification transistor 11132, and the drain of the selection transistor 11133 is connected to the column processing unit 14 in FIG. 1 via the column control line COL . When the pulse of the selection control signal is transmitted to the gate of the selection transistor 11133, the selection transistor 11133 is turned on. The signal output by the amplification transistor 11132 is transmitted to the column processing unit 14 through the selection transistor 11133 .

If the exposure control signal TG received by the gates TG1, TG2, TG3, and TG4 of the four transfer transistors 1112 makes the four transfer transistors 1112 turn on at the same time, the charges generated by the four photoelectric conversion elements 1111 are respectively transferred to the corresponding floating diffusion region FD and accumulate in the floating diffusion region FD; if the exposure control signal TG received by the gates TG1 and TG3 of the first and third transfer transistors 1112 makes the corresponding transfer transistors 1112 simultaneously turned on, the correspondingly connected first Charges generated by the first and third photoelectric conversion elements 1111 are respectively transferred to the corresponding floating diffusion regions FD, and accumulated in the floating diffusion regions FD.

It should be noted that the structure of the pixel 110 of the pixel circuit 111 in the embodiment of the present application is not limited to the structure shown in FIG. 5 . For example, the pixel circuit 111 may also have a three-transistor pixel structure, wherein the functions of the amplification transistor 11132 and the selection transistor 11133 are performed by one transistor.

Please continue to refer to FIG. 4 , the column processing unit 14 in FIG. 1 may include a conversion circuit 141 . The conversion circuit 141 is used for converting the analog signal corresponding to the charge into a digital signal. The conversion circuit 141 includes a plurality of analog-to-digital converters 1411 respectively connected to the plurality of pixel circuits 111 in a one-to-one correspondence, and each of the analog-to-digital converters 1411 is configured with output modes of various resolutions. It can be understood that the amount of charge generated by each photoelectric conversion element 1111 in the pixel circuit 111 is proportional to the amount of light it receives, and the charge is read as an analog signal, which is converted by the analog-to-digital converter 1411 into Corresponding digital signal, the value of the digital signal can be understood as the pixel value of the corresponding pixel. Wherein, each analog-to-digital converter 1411 included in the conversion circuit 141 can support different output resolutions, for example, 6bit, 8bit, 10bit, 12bit, 14bit. Each analog-to-digital converter 1411 can be correspondingly provided with multiple output modes, and the mapping relationship between the output mode and the output resolution of the analog-to-digital converter 1411 can be preset. One output mode corresponds to one output resolution, and its output Different modes have different output resolutions.

As shown in FIG. 6 , the image sensor further includes a processing circuit 15 connected to the conversion circuit 141, which is used to convert at least two of the output resolutions of the analog-to-digital converter 141 according to the output resolution of the analog-to-digital converter 1411. Digital signals are coded in the manner of multiplexing preset byte units. The processing circuit 15 may include an encoder to encode the digital signal output by each analog-to-digital converter 1411 . Specifically, when the processing circuit 15 encodes the digital signal output by the conversion circuit 141, it can obtain the output resolution of each analog-to-digital converter 1411 in advance, and convert at least two The digital signal output by the analog-to-digital conversion circuit 141 is encoded with a preset number of bytes as an encoding unit. That is, the processing circuit 15 can perform encoding processing on the digital signals output by each analog-to-digital converter 1411 according to a preset encoding strategy. Wherein, the preset encoding strategy may be to encode each digital signal output by at least two analog-to-digital converters 1411 in a manner of multiplexing encoding units, the encoding unit may include a preset number of bytes, and each byte may include a preset Set bits, for example, 8bit. Wherein, the preset number is associated with the output resolution of each analog-to-digital converter 1411 . Exemplarily, the output resolution of the first analog-to-digital converter in each analog-to-digital converter 1411 can be preconfigured to be 6 bits, and the output resolution of the second analog-to-digital converter in each analog-to-digital converter 1411 can be 10 bits, so , the total bits of the digital data output by the first analog-to-digital converter and the digital data output by the second analog-to-digital converter are 16 bits. The processing circuit 15 can encode the received digital data with two bytes as a coding unit, wherein the total digital data received by the processing circuit 15 only takes up two bytes, so that it is possible to avoid It needs to occupy three bytes, which can reduce the data transmission volume and power consumption of the image sensor, and can improve the compression rate of digital data.

In the embodiment of the present application, the image sensor includes a pixel array, a conversion circuit, and a processing circuit 15, wherein the pixel array includes a plurality of pixels, and the pixel circuit of the pixel includes a plurality of photoelectric conversion elements corresponding to the pixels, and the pixel The circuit is used to output the charge generated by the photoelectric conversion element corresponding to the same pixel; the conversion circuit includes a plurality of analog-to-digital converters, and each of the analog-to-digital converters is configured with multiple resolution output modes, and the conversion circuit For converting the analog signal corresponding to the charge into a digital signal, by configuring the output resolution of each analog-to-digital converter, and based on the output resolution of each analog-to-digital converter, the processing circuit 15 can convert at least two of the analog-to-digital converters into digital signals. The digital signal output by the digital conversion circuit is encoded with a preset number of bytes as the encoding unit, so that the multiplexing of multiple bytes can be realized, thereby reducing the data transmission volume and power consumption of the image sensor, and can Improves the compression ratio for digital data.

Fig. 7 is a schematic diagram of the arrangement of pixels in a pixel array according to some embodiments of the present application. The pixels 110 include two types, one is panchromatic pixels W, and the other is color pixels. Among other things, color pixels have a narrower spectral response than panchromatic pixels. Specifically, a panchromatic pixel may include multiple panchromatic sub-pixels W, and a color pixel may include multiple sub-pixels with the same single color.

The pixel array 11 can be formed by duplicating the smallest repeating unit multiple times in rows and columns. Each minimum repeating unit is composed of multiple panchromatic pixels W and multiple color pixels. Each minimum repeating unit includes a plurality of pixel units U. Each pixel unit U includes a plurality of single-color pixels and a plurality of panchromatic pixels W.

Specifically, FIG. 7 is a schematic diagram of the arrangement of pixels in the smallest repeating unit according to an embodiment of the present application. Wherein, the minimum repeating unit is 16 pixels in 4 rows and 4 columns, and the pixel unit U is 4 pixels in 2 rows and 2 columns. The arrangement is as follows:

W represents a panchromatic pixel; A represents a first color pixel among the plurality of color pixels; B represents a second color pixel among the plurality of color pixels; C represents a third color pixel among the plurality of color pixels.

For each pixel unit U, panchromatic pixels W and single-color pixels are arranged alternately.

As shown in FIG. 7 , the categories of the pixel units U include three categories. Among them, the first type of pixel unit UA includes a plurality of panchromatic pixels W and a plurality of first color pixels A; the second type of pixel unit UB includes a plurality of panchromatic pixels W and a plurality of second color pixels B; the third type of pixels The unit UC includes a plurality of panchromatic pixels W and a plurality of third color pixels C. Each minimum repeating unit includes four pixel units U, which are one first-type pixel unit UA, two second-type pixel units UB, and one third-type pixel unit UC. Among them, one first-type pixel unit UA and one third-type pixel unit UC are arranged in the first diagonal direction D1 (for example, the direction connecting the upper left corner and the lower right corner in FIG. 7 ), and two second-type pixel units UB are arranged In the second diagonal direction D2 (for example, the direction connecting the upper right corner and the lower left corner in FIG. 7 ). The first diagonal direction D1 is different from the second diagonal direction D2. For example, the first diagonal and the second diagonal are perpendicular. Exemplarily, in the minimum repeating unit, the pixel A of the first color may be a red pixel R; the pixel B of the second color may be a green pixel G; and the pixel C of the third color may be a blue pixel Bu.

As shown in FIG. 8 , for the convenience of description, the following embodiments all take the first type of pixel unit UA as an example for description. Wherein, the first type of pixel unit UA may include a first pixel 110-1, a second pixel 110-2, a third pixel 110-3 and a fourth pixel 110-4 arranged in a 2*2 array, wherein the first pixel One pixel 110-1 and the fourth pixel 110-4 are panchromatic pixels and are arranged in the first diagonal direction, and the second pixel 110-2 and the third pixel 110-3 are color pixels and are arranged in the first diagonal direction. Two diagonal directions.

It should be noted that, in other embodiments, the first diagonal direction D1 may also be the direction connecting the upper right corner and the lower left corner, and the second diagonal direction D2 may also be the direction connecting the upper left corner and the lower right corner. In addition, the "direction" here is not a single point, but can be understood as the concept of "straight line" indicating the arrangement, and there can be two-way pointing at both ends of the line.

The conversion circuit includes a plurality of conversion units 1410 , wherein the plurality of conversion units can be respectively connected to the plurality of pixel units in one-to-one correspondence. Specifically, each conversion unit may include four analog-to-digital converters, specifically, the first analog-to-digital converter ADC1, the second analog-to-digital converter ADC2, the third analog-to-digital converter ADC3, and the fourth analog-to-digital converter ADC4. Wherein, the first analog-to-digital converter ADC1 is connected to the pixel circuit of the first pixel 110-1; the second analog-to-digital converter ADC2 is connected to the pixel circuit of the second pixel 110-2; the third analog-to-digital converter ADC3 is connected to the pixel circuit of the third pixel 110-3; the fourth analog-to-digital converter ADC4 is connected to the pixel circuit of the fourth pixel 110-. Specifically, the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 can correspondingly receive the analog signal corresponding to the charge generated by the panchromatic pixel W, and convert the analog signal into a digital signal output; the second analog-to-digital converter The converter ADC2 and the third analog-to-digital converter ADC3 can receive analog signals corresponding to the charges generated by the color pixels (R, G, Bu), and convert the analog signals into digital signals for output.

In one of the embodiments, the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 are the same, and the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter are The output resolution of ADC4 is the same. That is, the output resolutions of the analog-to-digital converters used for analog-to-digital conversion of the charges generated by pixels of the same color are the same, which can improve the color uniformity of the image sensor.

In one of the embodiments, the output resolution of the second analog-to-digital converter ADC2 is greater than the output resolution of the first analog-to-digital converter ADC1. Meanwhile, the output resolution of the third analog-to-digital converter ADC3 is greater than the output resolution of the fourth analog-to-digital converter ADC4. In the embodiment of the present application, because the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 used for analog-to-digital conversion of the charges generated by the color pixels are set to be larger than those used for the full The output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 for analog-to-digital conversion of the charge generated by the color pixel W can improve the color reading accuracy of the color pixel.

It should be noted that, in the embodiment of the present application, the charge data generated by the panchromatic pixel W may be used for signal-to-noise ratio noise reduction.

In the embodiment of the present application, the processing circuit 15 can configure the output resolution of each analog-to-digital converter according to the working mode of the image processor. Wherein, the working mode may include a low power consumption mode in a low power consumption state and a noise reduction mode in a good noise reduction state.

Exemplarily, in the low power consumption mode, the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 can be set to 10 bits, and the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter can be set to 10 bits. The output resolution of the digital converter ADC4 is set to 6bit. That is to say, in the low power consumption mode, the high requirement of color accuracy can also be met. In the noise reduction mode, the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 can be set to 10bit, and the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 can be set to The output resolution is set to 8bit, that is to say, it can not only meet the medium level of signal-to-noise ratio noise reduction, but also meet the high requirements of color accuracy.

In one of the embodiments, the resolutions of the ADCs are equal, that is, the first ADC1, the second ADC2, the third ADC3 and the fourth ADC The output resolutions of ADC4 are equal. Exemplarily, the output resolutions of the first analog-to-digital converter ADC1, the second analog-to-digital converter ADC2, the third analog-to-digital converter ADC3, and the fourth analog-to-digital converter ADC4 can all be configured as 10 bits, so that both Under the premise of satisfying the ultimate signal-to-noise ratio and noise reduction, it can also meet the high requirements of color accuracy, and can further improve the imaging effect of the image processor.

In one embodiment, the processing circuit 15 is further configured to configure the resolution of each of the analog-to-digital converters according to the shooting scene, and the shooting scene includes a night scene mode and a landscape mode. Wherein, when the scene mode is landscape mode, the processing circuit 15 configures the resolution of the output mode of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 to be greater than or equal to the first analog-to-digital converter The resolution of the output modes of the converter ADC1 and the fourth analog-to-digital converter ADC4. Of course, the landscape mode can also be replaced by colorful modes such as gourmet mode.

When the scene mode is the night scene mode, the processing circuit 15 configures the resolution of the output mode of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 to be smaller than or equal to the resolution of the first analog-to-digital converter Resolutions of the output modes of ADC1 and the fourth analog-to-digital converter ADC4. That is, when in the night scene mode, the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 that can be configured to perform analog-to-digital conversion on the charges generated by the color pixels are set to be less than or equal to those used for The output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 that perform analog-to-digital conversion on the charge generated by the panchromatic pixel W. Exemplarily, the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 can be configured as 12bit, and the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 Both are configured as 10bit to improve the signal-to-noise ratio of the image and improve the image effect of night scene shooting.

Optionally, in the night scene mode, and the image sensor is in the working mode of the low power consumption mode, the processing circuit 15 configures the resolution of the output mode of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 to be greater than Resolutions of the output modes of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4. Exemplarily, the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 can be configured as 8bit, and the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 Both are configured as 10bit.

It should be noted that, in the embodiment of the present application, the configuration of the output resolution of each analog-to-digital converter may be comprehensively set according to the working mode of the image sensor and the shooting scene selected during the shooting process. Wherein, the specific value of the output resolution of each analog-to-digital converter is not limited to the foregoing examples.

In one of the embodiments, the sum of the resolutions corresponding to the output modes of the analog-to-digital converters in the same conversion unit 1410 is n times the preset bit, where n is a positive integer greater than 2.

In the embodiment of the present application, for the convenience of description, the preset bit is 8 bits, the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 are the same, and the output resolutions of the second analog-to-digital converter ADC2 and the third The output resolutions of the analog-to-digital converters ADC3 are the same, and the output resolution of the first analog-to-digital converter ADC1 is smaller than the output resolution of the second analog-to-digital converter ADC2 as an example for illustration. Wherein, if the sum of the output resolutions of the analog-to-digital converters in the same conversion unit 1410 is configured to be n times the preset bit, the processing circuit 15 can use n bytes for the digital signal output by the conversion unit 1410 Encoding processing for encoding units.

Specifically, the processing circuit 15 is configured to convert the first analog-to-digital converter and the second analog-to-digital converter ADC2 according to the output resolutions of the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 The output digital signal is coded in a manner of multiplexing m byte units. Correspondingly, the processing circuit 15 is further configured to convert the third analog-to-digital converter and the fourth analog-to-digital converter according to the output resolutions of the third analog-to-digital converter ADC3 and the fourth analog-to-digital converter ADC4 The digital signal output by the converter ADC4 is encoded in a manner of multiplexing m byte units. Wherein, m is a positive integer greater than 1, and n is twice m, and the preset bits are 8 bits.

Exemplarily, if the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 are configured to be 10 bits, the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 are both configured It is 6bit. When the circuit processing unit encodes the digital signals output by the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2, it can just share two bytes (including 16 bits); correspondingly, when the third analog-to-digital converter When the digital signals output by the converter ADC3 and the fourth analog-to-digital converter ADC4 are encoded, exactly two bytes (including 16 bits) can be shared. In this way, it is possible to avoid occupying too many bytes (for example, 6 bytes are required in the related art) in the encoding process, and at the same time, the output data volume and power consumption of the image sensor can also be reduced, and the processing of digital data can be improved. the compression rate.

In one of the embodiments, the processing circuit 15 is further configured to output the first digital signal output by the first modular converter and the second digital signal output by the second modular converter in accordance with a preset sequence. Sorting encoding is carried out in m byte units, wherein, if the number of bits of the first digital signal is less than 8 bits and the number of bits of the second digital signal is greater than 8 bits, part of the data of the second digital signal Supplement to the first byte where the first digital signal is located, occupy the first byte, and encode the remaining second digital signal in the second byte. Exemplarily, if the output resolution of the first analog-to-digital converter ADC1 is 6 bits, and the output resolution of the second analog-to-digital converter ADC2 is 10 bits, the processing circuit 15 may convert the 6-bit output resolution of the first analog-to-digital converter ADC1 to A digital signal can be preferentially encoded in the 6 consecutive bits of the first byte, and then the high-order 2 bits of the 8-bit second digital signal output by the second analog-to-digital conversion are added to the 6-bit first byte in the first byte The left side or the right side of a digital signal. In this way, the 6-bit first digital signal and the 8-bit second digital signal can be multiplexed into two-byte encoding units.

Optionally, in the process of encoding the first digital signal and the second digital signal, the processing circuit 15 may also select 6 bits from the 16 bits of the encoding unit to encode the first digital signal, and in the encoding unit The remaining 10 bits are used to encode the second digital signal. The 6-bit first digital signal can be randomly encoded in the 6 bits of the encoding unit, and the 10-bit second digital signal can also be randomly encoded in the remaining 10 bits of the encoding unit.

It should be noted that, in the embodiment of the present application, during the process of encoding the first digital signal and the second digital signal, the processing circuit 15 can multiplex the encoding unit according to a preset codec protocol, the first The arrangement order of the digital signal and the second digital signal in the coding unit is not further limited, nor limited to the foregoing examples.

In one of the embodiments, if the sum of the resolutions corresponding to the output modes of the analog-to-digital converters in the same conversion unit 1410 is not n times the preset bit, the processing circuit 15 is further configured to The sum of the output resolutions of each of the analog-to-digital converters in the conversion unit 1410, and the encoding unit is determined according to the least common multiple of the sum of the resolutions and the preset bits, wherein the encoding unit The total bits of are equal to the least common multiple. Specifically, the processing circuit 15 can perform encoding processing on the digital signals corresponding to the output of each analog-to-digital converter in a manner of multiplexing q bytes according to the output resolution of each analog-to-digital converter in the conversion unit 1410, where q> m. Specifically, the processing circuit 15 can obtain the sum p of the output resolutions of the analog-to-digital converters of each conversion unit 1410, obtain the least common multiple of p and preset bits, and use the least common multiple as the Total number of bits.

Exemplarily, if the output resolutions of the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3 are configured to be 12 bits, the output resolutions of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 are both configured is 6 bits, then the processing circuit 15 can perform encoding processing on the digital signals correspondingly output by each analog-to-digital converter in a manner of multiplexing 9 bytes. Specifically, the encoding unit may include 72 bits, that is, the encoding unit includes 9 bytes, wherein the processing circuit 15 may encode the digital signals output by every two conversion units 1410 in a manner of multiplexing one encoding unit deal with.

In the embodiment of the present application, by configuring the output resolutions of the analog-to-digital converters used to process the charge data of pixels of different colors, the processing circuit can, based on the output resolutions of the respective analog-to-digital converters, convert at least two The digital signal output by the analog-to-digital conversion circuit is encoded with a preset number of bytes as the encoding unit, so that the multiplexing of multiple bytes can be realized, and the data transmission volume and power consumption of the image sensor can be reduced. And can improve the compression ratio of digital data.

As shown in FIG. 9, in one embodiment, the pixel unit is configured with a first column control line COL1, a second column control line COL2, a third column control line COL3, and a fourth column control line COL4. The pixel circuit 111 of a pixel 110-1 is connected to the first column control line COL1 through the first switch S1, and the pixel circuit 111 of the second pixel is connected to the third column control line COL3 through the second switch S2, The pixel circuit 111 of the third pixel is connected to the second column control line COL2 through the third switch S3, and the pixel circuit 111 of the fourth pixel is connected to the fourth column control line COL4 through the fourth switch S4, Wherein, the first column control line COL1, the second column control line COL2, the third column control line COL3, and the fourth column control line COL4 are respectively connected with the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 , the third analog-to-digital converter ADC3 , and the fourth analog-to-digital converter ADC4 are connected in one-to-one correspondence.

Please continue to refer to FIG. 4 and FIG. 9, the conversion circuit 141 is also used to read out the converted digital signal together with the pixel circuit 111 based on the full-resolution output mode or the first-level combined output mode, wherein the full-resolution mode It is used to read out the digital signal in units of the sub-pixels, and the first-level combined output mode is used to read out the digital signals in units of the pixels. Specifically, the full resolution mode is used to read out the charge in the pixel by the sub-pixel as a unit. That is, the conversion circuit 141 and the pixel circuit 111 can jointly output the digital signal corresponding to the charge generated by a single photodiode in the same pixel. The first-stage combined output mode is used to read out the charge in the pixel in units of the pixel, that is, the conversion circuit 141 and the pixel circuit 111 can jointly compare the charges generated by the four photoelectric conversion elements 111 in the same pixel. The summed and/or averaged processed digital signals are combined for output.

Specifically, if the charge accumulated in the floating diffusion region FD within the same exposure time is the charge of one photoelectric conversion element 1111, the pixel circuit 111 can store the charges corresponding to each of the photoelectric conversion elements 1111 The analog signal is output to the conversion circuit 141 in time division, so that the conversion circuit 141 executes the full-resolution output mode for a plurality of the analog signals. Wherein, the time-sharing output can be understood as the time-sharing output of charges accumulated by different photoelectric conversion elements 1111 within different exposure times. Exemplarily, the charge accumulated by the first photoelectric conversion element within the first exposure time can be output at the first moment; the charge accumulated by the second photoelectric conversion element within the second exposure time can be output at the second moment, wherein, The time points of the first moment and the second moment are different.

In one of the embodiments, the first-stage combined output mode includes an addition mode for reading out after analog-to-digital conversion the total charges accumulated in the floating diffusion area of all sub-pixels in the same pixel. If the charge accumulated in the floating diffusion region FD within the same exposure time is the charge of all the photoelectric conversion elements 1111 in the same pixel, the pixel circuit 111 can output the analog signal corresponding to the accumulated charge to all The conversion circuit 141 is configured so that the conversion circuit 141 performs the operation of the addition mode on the analog signal.

For the convenience of description, taking the image sensor shown in FIGS. 8 and 9 as an example, the working principle of the addition mode in the full-resolution output mode and the first-level combined output mode will be described. Among them, the pixel unit is configured with exposure control lines TG1-TG8 for transmitting exposure control signals, multiple reset control lines RST for transmitting reset control signals, and multiple column control lines COL1-COL4, each column control line It can be connected corresponding to each mode converter in the conversion circuit 141 .

Full resolution output mode: Exposure control lines TG1, TG5 input high level, the transfer transistors corresponding to sub-pixels W1, R1, R5, W5 are turned on, and the charges generated by sub-pixels W1, R1, R5, W5 are transferred respectively Into the corresponding floating diffusion area, then the exposure control lines TG1 and TG5 input low level, the transfer transistors of the corresponding sub-pixels W1, R1, R5, W5 are turned off, and are closed by controlling the switches S1, S2, S3, S4. Among them, the charge transferred from the sub-pixel W1 to the floating diffusion region FD1 is converted into an analog signal through the amplifying transistor SF1 and input to the analog-to-digital converter ADC1 through the column control line COL1; the charge transferred from the sub-pixel R1 to the floating diffusion region FD2 is passed through The analog signal converted by the following transistor SF2 is input to the analog-to-digital converter ADC2 through the column control line COL2, and the charge transferred from the sub-pixel R5 to the floating diffusion region FD3 is converted by the following transistor SF3 into the analog signal through the column control line COL3. The digital converter ADC3, the charge transferred from the sub-pixel W5 to the floating diffusion area FD4 is followed by the transistor SF4, and the analog signal formed by the following transistor SF4 is input to the analog-to-digital converter ADC4 through the column control line COL4 to read out each sub-pixel W1, R1, R5, W5 The resulting charge corresponds to a digital signal. Then, the exposure control lines TG1 and TG5 input a high level, which is similar to the readout method of the subpixels W1, R1, R5, and W5, and the digital signals corresponding to the charges generated by the subpixels W2, R2, R6, and W6 can be read out. By analogy, the digital signal corresponding to the charge generated by each sub-pixel in the pixel unit U can be correspondingly read out, referring to FIG. 10 .

In this embodiment, the output resolution of each analog-to-digital converter in the conversion unit 1410 may be configured based on the configuration manner of configuring the output resolution of each analog-to-digital converter in any of the preceding embodiments. Exemplarily, by configuring the output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 to be 6 bits, the data output of the full-color pixel W can be output; configuring the second analog-to-digital converter ADC2, the fourth The output resolution of the three analog-to-digital converters ADC3 is 10 bits, and it can output data of color pixels (for example, R, G or B pixels). In this way, if the image sensor is in the full-resolution output mode, as shown in FIG. R, G, or B pixels) can share two bytes, which can reduce the data transmission amount and power consumption of the image sensor, and can improve the compression rate of digital data.

The addition mode in the first-stage combined output mode: the exposure control lines TG1-TG4 input high level at the same time, the transfer transistors corresponding to the sub-pixels W1-W4 and R1-R4 are turned on, and the charges of the four sub-pixels W1-W4 are transferred to the common In the floating diffusion region FD1, the charges of the four sub-pixels R1-4 are transferred to the common floating diffusion region FD2. Then, the exposure control lines TG1-TG4 input a low level at the same time, the transfer transistors corresponding to the sub-pixels W1-W4 and R1-R4 are in the off state, and the charges generated by the four sub-pixels W1-W4 are accumulated and superimposed in the floating diffusion region FD1 to form The first charge is converted into an analog signal after passing through the amplifying transistor SF1, and then closed by controlling the switch S1, and output to the analog-to-digital converter ADC1 through the column control line COL1. The charges generated by the four sub-pixels R1-R4 are accumulated and superimposed in the floating diffusion region FD2 to form the second charge, which is converted into an analog signal after passing through the follower transistor SF2, and then closed by controlling the switch S2, and output to the analog-to-digital converter through the column control line COL2 ADC2. Correspondingly, at the same time, the exposure control lines TG5-TG8 also input a high level at the same time, so that the charge signals of the four sub-pixels R5-R8 can be transferred to the floating diffusion area FD3, and the signals of the four sub-pixels W5-W8 can be transferred to the floating diffusion area In FD4, then, by controlling the exposure control lines TG5-TG8 to input a low level at the same time, after being converted into an analog voltage signal by the amplifying transistor SF3, by controlling the switch S3 to close, the third charge accumulated in the floating diffusion area FD3 is controlled by column The line COL3 is output to the analog-to-digital converter ADC3; after being converted into an analog voltage signal by the amplifying transistor SF4, the fourth charge accumulated in the floating diffusion area FD4 is output to the analog-to-digital converter ADC4 through the column control line COL4 by controlling the switch S4 to be closed , refer to Figure 12.

In this embodiment, the image sensor may configure the output resolution of each analog-to-digital converter in the conversion unit 1410 based on the configuration manner of configuring the output resolution of each analog-to-digital conversion in any of the foregoing embodiments. Exemplarily, by configuring the output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 to be 6 bits, the data output of the full-color pixel W can be output; configuring the second analog-to-digital converter ADC2, the fourth The output resolution of the three analog-to-digital converters ADC3 is 10 bits, and it can output data of color pixels (for example, R, G or B pixels). In this way, if the image sensor is in the addition mode of the first combined output mode, as shown in FIG. Pixels (eg, R, G, or B pixels) can share two bytes, which reduces data transfer and power consumption of the image sensor, and improves compression of digital data.

As shown in FIGS. 14 and 15 , in one embodiment, the conversion unit 1410 further includes a first switch unit 1412 connected to the output terminals of each analog-to-digital converter. Specifically, its first switch unit 1412 may include four switches S17, S18, S19, and S20. Wherein, the switch S17 is connected between the first analog-to-digital converter ADC1 and the third analog-to-digital converter ADC3, the switch S18 is connected between the second analog-to-digital converter ADC2 and the fourth analog-to-digital converter ADC4, and the switch S19 is connected between Between the first ADC1 and the second ADC2, the switch S19 is connected between the third ADC3 and the fourth ADC4. Wherein, the conversion circuit 141 is also used for reading out digital signals based on the second-level combined output mode, wherein the second-level combined output mode is used for the first diagonal or the second diagonal direction All of the pixels as a unit read out the digital signal. That is, the second-level combined output mode is used to read out the digital signal in units of 2 pixels in the pixel unit, wherein the 2 pixels are located in the pixel unit The first diagonal or the second diagonal. Exemplarily, the second-level combined output mode can be understood as the first digital signal output by the first-level combined output mode for the first pixel 110-1 and the fourth digital signal output by the first-level combined output mode for the fourth pixel 110-4. signal, and then perform an averaging operation on the first digital signal and the fourth digital signal again to read out the digital average signal of all pixels 110 on the first diagonal; meanwhile, the first stage can also be used for the second pixel 110-2 The second digital signal output in the combined output mode and the third pixel 110-3 adopt the third digital signal output by the first stage combined output, and perform an average operation on the second digital signal and the third digital signal again to read out the second diagonal Digitally averaged signal of all pixels on the line.

For the convenience of description, the working principle of the second-level combined output mode will be described by taking the image sensor shown in FIGS. 14 and 15 as an example.

The second level combined output mode: take eight sub-pixels W1-W4, W5-W8 as an example for illustration. For example, the output results of the first-stage combined output mode (addition mode) of the four sub-pixels W1-W4 can be read through the analog-to-digital converter ADC1, and the first-stage combined output mode (addition mode) of the four sub-pixels W5-W8 ) can be read through the analog-to-digital converter ADC4; then, by controlling the switch S19 to close and the switch S17 to open, the analog-to-digital converters ADC1 and ADC4 are short-circuited, so that the analog-to-digital converter ADC1 can be read The average of the first digital signal read out by the analog-to-digital converter ADC4 and the fourth digital signal read out by the analog-to-digital converter ADC4 can realize the readout of charges in units of all pixels 110 on the first diagonal line. Correspondingly, by controlling the switch S20 to be closed and the switch S18 to be opened, the analog-to-digital converters ADC2 and ADC3 are short-circuited, so that the second digital signal read by the analog-to-digital converter ADC2 and the analog-to-digital converter ADC3 can be read The output third digital signal is averaged, so as to realize the readout of charges in units of all pixels 110 on the second diagonal line. As shown in FIG. 16, in the embodiment of the present application, the image sensor may combine the charge data of each pixel in the pixel array 11 by using the second-level combined output mode on the basis of the output result of the first-level combined output mode. output. Therefore, the image sensor in the embodiment of the present application can support the readout of the charge data of each sub-pixel in each pixel unit in the full-resolution output mode, the first-level combined output mode and the second-level combined output mode, and can expand The flexibility of the output mode of the image sensor can be applied to more usage scenarios.

In this embodiment, the image sensor may configure the output resolution of each analog-to-digital converter in the conversion unit 1410 based on the configuration manner of configuring the output resolution of each analog-to-digital conversion in any of the foregoing embodiments. Exemplarily, by configuring the output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 to be 6 bits, the data output of the full-color pixel W can be output; configuring the second analog-to-digital converter ADC2, the fourth The output resolution of the three analog-to-digital converters ADC3 is 10 bits, and it can output data of color pixels (for example, R, G or B pixels). In this way, if the image sensor is in the second combined output mode, as shown in FIG. R, G, or B pixels) can share two bytes, which can reduce the data transmission amount and power consumption of the image sensor, and can improve the compression rate of digital data.

As shown in Figure 18, in one of the embodiments, the conversion unit 1410 may include eight analog-to-digital converters, that is, on the basis of Figure 15, it may also include a fifth analog-to-digital converter ADC5, a sixth analog A digital converter ADC6, a seventh analog-to-digital converter ADC7, and an eighth analog-to-digital converter ADC8. Correspondingly, the pixel unit is further configured with a fifth column control line COL5 , a sixth column control line COL6 , a seventh column control line COL7 and an eighth column control line COL8 . Wherein, the pixel circuit of the first pixel 110-1 is connected to the fifth column control line COL5 through the fifth switch S5, and the pixel circuit of the second pixel 110-2 is connected to the sixth column control line COL5 through the sixth switch S6. The column control line COL6 is connected, the pixel circuit of the third pixel 110-3 is connected to the seventh column control line COL7 through the seventh switch S7, and the pixel circuit of the fourth pixel 110-4 is connected to the pixel circuit through the eighth switch S8. The eighth column control line COL8 is connected; wherein, the fifth column control line COL5, the sixth column control line COL6, the seventh column control line COL7 and the eighth column control line COL8 are respectively connected to the fifth analog-to-digital conversion The ADC5, the sixth ADC6, the seventh ADC7 and the eighth ADC8 are connected in one-to-one correspondence.

Among them, the first analog-to-digital converter ADC1 and the fifth analog-to-digital converter ADC5 can be used to receive the analog signal corresponding to the charge generated by the first pixel 110-1, and convert it into a digital signal, that is, the first analog-to-digital converter The ADC1 and the fifth analog-to-digital converter ADC5 can be used to perform analog-to-digital conversion on the analog quantity corresponding to the charge generated by the full-color pixel W. Correspondingly, the second analog-to-digital converter ADC2 and the sixth analog-to-digital converter ADC6 can be used to receive the analog signal corresponding to the charge generated by the second pixel and convert it into a digital signal. The third analog-to-digital converter ADC3 and the seventh analog-to-digital converter ADC7 can be used to receive the analog signal corresponding to the charge generated by the third pixel and convert it into a digital signal. The fourth analog-to-digital converter ADC4 and the eighth analog-to-digital converter ADC8 can be used to receive the analog signal corresponding to the charge generated by the fourth pixel and convert it into a digital signal.

Wherein, the first switch unit 1412 may include eight switches, namely switches S17, S18, S19, S20, S21, S22, S23, and S24. Wherein, the conversion circuit 141 is also used for reading out digital signals based on the first-level combined output mode. Specifically, the first-stage combined output mode may include at least one of an addition mode and a mixing mode.

Among them, the mixing mode can be understood as: the first digital signal output after analog-to-digital conversion of the first analog signal accumulated in the floating diffusion area by the first part of sub-pixels in the same pixel, and the second part of sub-pixels in the same pixel The second analog signal accumulated in the floating diffusion area is subjected to analog-to-digital conversion and then output as a second digital signal for averaging and then read out; wherein the first part of sub-pixels and the second part of sub-pixels jointly constitute the pixel. If the charge accumulated in the floating diffusion region FD within the first exposure time is the first accumulated charge accumulated in the photoelectric conversion element corresponding to the first sub-pixel, or, the floating diffusion region FD is in the second The charge accumulated during the exposure time is the second accumulated charge accumulated by the corresponding photoelectric conversion elements of the second part of the sub-pixels, then the pixel circuit turns on a plurality of the output terminals to respectively connect the The analog signals corresponding to the first accumulated charge and the second accumulated charge are time-divisionally output to the conversion circuit, so that the conversion circuit performs the mixed mode operation on the analog signal. Exemplarily, if the pixel includes two columns of sub-pixels, the first part of sub-pixels includes the sub-pixels in the first column, and the second part of sub-pixels includes the sub-pixels in the second column.

For ease of description, the image sensor shown in FIG. 18 is taken as an example to describe the working principle of the hybrid mode in the first-stage combined output mode.

Mixed mode in the first-stage combined output mode: Exposure control lines TG1 and TG3 input high level at the same time, the transfer transistors corresponding to sub-pixels W1, W3, R1 and R3 are turned on, and the charges of the two sub-pixels W1 and W3 are transferred to the shared In the floating diffusion region FD1, the charges of the two sub-pixels R1, R3 are transferred to the common floating diffusion region FD2. Then, the exposure control lines TG1, TG3, TG5, and TG7 input low levels at the same time, the transfer transistors corresponding to the sub-pixels W1, W3, R1, and R3 are in the off state, and the charges generated by the two sub-pixels W1, W3 are in the floating diffusion area FD1 The first charge is accumulated and superimposed to form the first charge, which is converted into an analog signal through the amplifying transistor SF1, and then is output to the analog-to-digital converter ADC1 through the column control line COL1 by controlling the switch S1 to be closed and the switch S5 to be opened. Correspondingly, the charges generated by the two sub-pixels R1 and R3 are accumulated and superimposed in the floating diffusion region FD2 to form a second charge, which is converted into an analog signal after passing through the follower transistor SF2, and then controlled by the control switch S2 to close and the switch S6 to open. Line COL2 is output to the analog-to-digital converter ADC2.

The reset control line RST inputs a high level to reset the reset transistor and clear the charges accumulated in the floating diffusion regions FD1 and FD2. Then, the exposure control lines TG2 and TG3 first input a high level, and then input a low level, so as to accumulate and superimpose the charges generated by the two sub-pixels W2 and W3 in the floating diffusion region FD1 to form a third charge, and the two sub-pixels R2, The charges generated by R3 are accumulated and superimposed in the floating diffusion region FD1 to form fourth charges. By controlling the switch S5 to close and the switch S1 to open, the third charge is output to the analog-to-digital converter ADC5 via the column control line COL5, the control switch S6 is closed, and the switch S2 is open, and the fourth charge is output to the analog-to-digital converter via the column control line COL6. Digital converter ADC6. At the same time, by controlling the switch S21 in the first switch unit 1412 to be closed, the digital signal of the first charge read by the ADC1 and the digital signal of the third charge read by the ADC5 are averaged. By controlling the switch S22 in the first switch unit 1412 to be closed, the digital signal of the second charge read by the analog-to-digital converter ADC2 and the digital signal of the fourth charge read by the analog-to-digital converter ADC6 are averaged. During this process, the switches S23 and S24 of the third first switch unit 1412143 are in the off state.

In this embodiment, the image sensor may configure the output resolution of each analog-to-digital converter in the conversion unit 1410 based on the configuration manner of configuring the output resolution of each analog-to-digital conversion in any of the foregoing embodiments. Exemplarily, by configuring the output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 to be 6 bits, the data output of the full-color pixel W can be output; configuring the second analog-to-digital converter ADC2, the fourth The output resolution of the three analog-to-digital converters ADC3 is 10 bits, and it can output data of color pixels (for example, R, G or B pixels). In this way, if the image sensor is in the hybrid mode of the first combined output mode, when the processing circuit 15 encodes the digital signal output by the conversion circuit 141, the digital signal of a panchromatic pixel W and a color pixel (for example, R, G or B pixels) can share two bytes, which can reduce the data transmission amount and power consumption of the image sensor, and can improve the compression rate of digital data.

It should be noted that, based on the image sensor as shown in Figure 18, through the on-off control of the switches S1-S8, and the switches S17-S14, the image sensor can be read in the mixed mode of the first combined output mode. Reading out the digital signal corresponding to each pixel can also make the image sensor read out the digital signal corresponding to each pixel in the full resolution mode, the addition mode of the first combined output mode and the readout mode of the second combined output mode, which For the specific readout control manner, reference may be made to the foregoing embodiments, and details will not be repeated in this embodiment.

It should be noted that the output mode of the first level combination of each pixel in the pixel array is the same. The second level combined output mode also includes addition mode and mixing mode. Wherein, the combined output mode of the first level is the same as the combined output mode of the second level.

As shown in FIG. 19, in one embodiment, on the basis of the embodiment shown in FIG. 18, the conversion unit 1410 further includes: a plurality of storage averaging units, the first of the plurality of storage averaging units The ends are respectively connected to a plurality of analog-to-digital converters through the first switch unit in one-to-one correspondence, and the second end of the storage averaging unit is connected to the processing circuit for all storing the digital signals in partitions, and performing an averaging operation on the digital signals stored in partitions. Wherein, the number of storage averaging units 1413 may be equal to the number of analog-to-digital converters in the converting unit 1410 . Specifically, the storage averaging unit 1413 may include two storage capacitors C1, C2, a ninth switch S9 and a tenth switch S10. Wherein, the first end of the ninth switch S9 is connected to the output end of the analog-to-digital converter, and the two second ends of the ninth switch S9 are respectively connected to the first ends of the storage capacitors C1 and C2 in a one-to-one correspondence. The first end of the tenth switch S10 is connected to the processing circuit 15 , and the two second ends of the tenth switch S10 are respectively connected to the second ends of the storage capacitors C1 and C2 in a one-to-one correspondence. Exemplarily, both the ninth switch S9 and the tenth switch S10 may be single-pole double-throw switches.

The conversion circuit 141 is also used for reading out the converted digital signal together with the pixel circuit based on the digital average mode. The digital averaging mode can be understood as performing analog-to-digital conversion on the charges generated by each sub-pixel in the same pixel in time division, and averaging the converted digital signals before reading them out. Specifically, if the charge accumulated in the floating diffusion region within the same exposure time is the charge of one photoelectric conversion element, then the pixel circuit turns on all the output terminals, so that each of the photoelectric conversion elements The analog signal corresponding to the charge is time-divisionally output to the conversion circuit, so that the conversion circuit performs a digital average mode operation on a plurality of the analog signals.

For ease of description, the image sensor shown in FIG. 19 is taken as an example to describe the working principle of the digital average mode in the first-level combined output mode.

The digital average mode in the first-level combined output mode: take the sub-pixels W1, W2, W3, and W4 as an example for illustration. During the first exposure time, the charges generated by the sub-pixel W1 are transferred to the corresponding floating diffusion region FD1, and the charges in the floating diffusion region FD1 are converted into analog signals after passing through the amplifying transistor SF1. At the same time, by controlling the switch S1 to be closed and the switch S5 to be opened, the analog signal is input into the analog-to-digital converter ADC1 through the first column control line COL1, and the analog-to-digital converter ADC1 can be turned on by controlling the ninth switch S9 to be turned on. The digital signal output after digital conversion is transmitted to the storage capacitor C1 for storage. Correspondingly, after the high-level reset of the reset transistor, the charge in the floating diffusion region FD1 is cleared, and the analog signal corresponding to the charge generated by the sub-pixel W2 can be input into the analog-to-digital converter ADC5 during the second exposure time, and controlled The ninth switch S9 is turned on, and after the analog-to-digital conversion by the analog-to-digital converter ADC5 , the digital signal corresponding to the sub-pixel W2 is output to the storage capacitor C1 for storage. Correspondingly, the digital signal corresponding to the charge generated by the sub-pixel W3 can be transmitted to the storage capacitor C2 connected to the analog-to-digital converter ADC1 for storage; the digital signal corresponding to the charge generated by the sub-pixel W4 can be transmitted to the analog-to-digital converter The storage capacitor C2 connected to ADC5 is used for storage. Then, by controlling the tenth switch S10 to be turned on, the average output of four digital signals corresponding to the four sub-pixels W1 , W2 , W3 , W4 is realized. In the digital average output mode, after the last sub-pixel charge is read out, the charge stored in the current floating diffusion region FD1 needs to be cleared before the next sub-pixel charge can be read out.

In this embodiment, the image sensor may configure the output resolution of each analog-to-digital converter in the conversion unit 1410 based on the configuration manner of configuring the output resolution of each analog-to-digital conversion in any of the foregoing embodiments. Exemplarily, by configuring the output resolution of the first analog-to-digital converter ADC1 and the fourth analog-to-digital converter ADC4 to be 6 bits, the data output of the full-color pixel W can be output; configuring the second analog-to-digital converter ADC2, the fourth The output resolution of the three analog-to-digital converters ADC3 is 10 bits, and it can output data of color pixels (for example, R, G or B pixels). In this way, if the image sensor is in the digital average mode of the first combined output mode, when the processing circuit 15 encodes the digital signal output by the conversion circuit 141, the digital signal of a panchromatic pixel W and a color pixel (for example, R, G or B pixels) can share two bytes, which can reduce the data transmission amount and power consumption of the image sensor, and can improve the compression rate of digital data.

It should be noted that, based on the image sensor as shown in Figure 19, through the on-off control of the switches S1-S8 and switches S17-S14, the image sensor can be read in the digital average readout mode of the first combined output mode. Reading out the digital signal corresponding to each pixel can also make the image sensor read out the digital signal corresponding to each pixel in the full resolution mode, the mixed mode of the first combined output mode, the addition mode and the second combined output mode. For the specific readout control method of the signal, reference may be made to the foregoing embodiments, and details are not repeated in this embodiment.

It should be noted that the output mode of the first level combination of each pixel in the pixel array is the same. The first-level combined output mode is the same as the second-level combined output mode. That is, the second-level combined output mode also includes an addition mode, a mixing mode and a digital average mode.

In the embodiment of the present application, for the convenience of description, Table 1 is an analysis and comparison table of advantages of the full-resolution output mode, the first-level combined output mode, and the second-level combined output mode.

Table 1 is an analysis and comparison table of the advantages of the full-resolution output mode, the first-level combined output mode and the second-level combined output mode

Based on the advantage analysis table of each output mode shown in Table 1, it can be seen that different output modes can be applied in different usage scenarios.

Exemplarily, for a picture shooting scene, when it is necessary to capture images of high-definition scenes (for example, scenes with more textures, such as grass, etc.) or high-brightness scenes (for example, outdoors on a sunny day), the image sensor can be controlled to operate in full-resolution mode Data is read out from the pixel array for full-size image capture. When it is necessary to collect images of low-brightness scenes (for example, indoor scenes or outdoors on cloudy days), the image sensor can be controlled to read out the data of the pixel array in a medium-resolution output mode (for example, the first-level combined output mode) to perform Picture shooting; when it is necessary to collect an image of a dark scene (for example, at night), the image sensor can be controlled to read out the output mode of the pixel array with a high light input amount and a high signal-to-noise ratio (for example, the second-level combined output mode) data for image capture.

Exemplarily, for a video shooting scene, when you need to shoot 4K2K video, you can switch to the first-level combined output mode to read out the data of the pixel array; when you need to shoot 1080P video, you can switch to the second-level combined output mode to read out Data for the pixel array. As for the general preview mode, the data of the pixel array can be read out in the second-level combined output mode.

Further, the selection of the addition mode, the mixing mode and the average mode in the first-level combined output mode and the second-level combined output mode can follow the following principles:

When high signal-to-noise ratio scenes are required, such as low-light scenes and night scenes; or low-power consumption scenes are required, such as long-term preview or video shooting; or high frame rate scenes are required, such as HDR video shooting or HDR preview or slow shooting For motion video, data from the pixel array can be read out in additive mode.

When the resolution and signal-to-noise ratio need to be taken into account, such as indoor scenes (shopping malls), cloudy and most other scenes, the mixed mode can be used to read out the data of the pixel array.

When a scene with a high dynamic range is required, such as an outdoor scene on a sunny day, the data of the pixel array can be read out by using a digital average or an analog average mode.

As shown in FIG. 20 , the embodiment of the present application also provides a camera assembly. Wherein, the camera assembly 20 includes the image sensor 10 and the lens 21 of any embodiment of the present application. The lens 21 is used to image the image on the image sensor 10 , for example, the light of the subject is imaged to the image sensor 10 through the lens 21 , and the image sensor 10 is arranged on the focal plane of the lens 21 . The camera assembly 20 may also include circuit components 22 . The circuit part 22 is used to obtain electric energy and transmit data with the outside, for example, the circuit part can be connected with the power supply of my department to obtain electric energy, and can also be connected with a memory or a processor to transmit image data or control data.

Wherein, the camera assembly 20 can be arranged on the back of the mobile phone as a rear camera. Understandably, the camera assembly 20 can also be arranged on the front of the mobile phone as a front camera.

As shown in FIG. 21 , the embodiment of the present application also provides a mobile terminal. The mobile terminal 100 includes the camera assembly 20 and the casing 80 of any embodiment of the present application. The camera assembly 20 is combined with the casing 80 . Specifically, the camera assembly 20 is arranged on the casing 80, the casing 80 includes a middle frame and a backboard, and the camera assembly 20 is fixedly arranged on the middle frame or the backboard.

The mobile terminal 100 also includes a processor and a memory connected through a system bus. Among them, the processor is used to provide computing and control capabilities to support the operation of the entire electronic device. The memory may include non-volatile storage media and internal memory. Nonvolatile storage media store operating systems and computer programs. The internal memory provides a high-speed running environment for the operating system computer program in the non-volatile storage medium. The electronic device can be any terminal device such as mobile phone, tablet computer, PDA (Personal Digital Assistant, personal digital assistant), POS (Point of Sales, sales terminal), vehicle-mounted computer, wearable device, etc.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims

An image sensor comprising:

A pixel array, including a plurality of pixels, the pixel circuit of each pixel includes a plurality of photoelectric conversion elements corresponding to the pixel, and the pixel circuit is used to output the charge generated by at least one photoelectric conversion element corresponding to the pixel;

A conversion circuit, including a plurality of analog-to-digital converters respectively connected to a plurality of pixel circuits in one-to-one correspondence, each of the analog-to-digital converters is configured with output modes with multiple resolutions, and the conversion circuit is used to convert the charge The corresponding analog signal is converted into a digital signal;

A processing circuit, connected to each of the analog-to-digital converters, for converting the digital signals output by at least two of the analog-to-digital conversion circuits into a preset number of bytes according to the output resolution of the analog-to-digital converters Encoding processing is performed for a coding unit, wherein the byte includes preset bits.
The image sensor according to claim 1, wherein the pixel array includes a plurality of pixel units, and the same pixel unit includes a first pixel, a second pixel, a third pixel and a fourth pixel arranged in a 2*2 array Pixels, wherein the first pixel and the fourth pixel are panchromatic pixels and are arranged in the first diagonal direction, and the second pixel and the third pixel are color pixels and are arranged in the second diagonal direction ; the color pixel has a narrower spectral response than the panchromatic pixel, and the first diagonal direction is different from the second diagonal direction; wherein,

The conversion circuit includes a plurality of conversion units respectively connected to a plurality of the pixel units in one-to-one correspondence, and the conversion unit includes a first analog-to-digital converter connected to the pixel circuit of the first pixel, and a first analog-to-digital converter connected to the second pixel unit. A second analog-to-digital converter connected to the pixel circuit of the second pixel, a third module converter connected to the pixel circuit of the third pixel, and a fourth analog-to-digital converter connected to the fourth pixel.
The image sensor according to claim 2, wherein the resolution of the second analog-to-digital converter and the third analog-to-digital converter are the same, and the resolution of the first analog-to-digital converter and the fourth analog-to-digital converter The resolution of the device is the same.
The image sensor according to claim 3, wherein the resolution of the second analog-to-digital converter is greater than or equal to the resolution of the first analog-to-digital converter.
The image sensor according to claim 3, wherein the sum of the output resolutions corresponding to the analog-to-digital converters in the same conversion unit is n times the preset bit, where n is greater than A positive integer of 2.
The image sensor according to claim 3, wherein the processing circuit is configured to convert the first analog-to-digital converter to the output resolution of the first and second analog-to-digital converters. performing encoding processing in a manner of multiplexing m byte units with the digital signal output by the second analog-to-digital converter;

The processing circuit is further configured to output the third analog-to-digital converter and the fourth analog-to-digital converter according to the output resolutions of the third analog-to-digital converter and the fourth analog-to-digital converter The digital signal is coded by multiplexing m byte units; wherein, m is a positive integer greater than 1, and n is twice m, and the preset bits are 8 bits.
The image sensor according to claim 5, wherein the processing circuit is further configured to output the first digital signal output by the first modular converter and the first digital signal output by the second modular converter according to a preset order The two digital signals are sorted and encoded within m byte units, wherein, if the number of digits of the first digital signal is less than 8 bits and the number of digits of the second digital signal is greater than 8 bits, the second digit Part of the data of the signal is added to the first byte where the first digital signal is located, and the remaining second digital signal is encoded in the second byte.
The image sensor according to claim 3, wherein, if the sum of the resolutions corresponding to the output modes of the analog-to-digital converters in the same conversion unit is not n times the preset bit, the processing circuit further uses The encoding unit is determined according to the sum of the output resolutions of the analog-to-digital converters in the same conversion unit, and according to the least common multiple of the sum of the resolutions and the preset bits, wherein the The total bits of the coding unit are equal to the least common multiple.
The image sensor according to claim 2, wherein the processing circuit is further configured to configure the resolution of each of the analog-to-digital converters according to a preset scene, and the preset scene includes at least one of a night scene mode and a landscape mode kind;

When the scene mode is landscape mode, the processing circuit configures the resolution of the output mode of the second analog-to-digital converter and the third analog-to-digital converter to be greater than or equal to the resolution of the first analog-to-digital converter and the fourth analog-to-digital converter the resolution of the output mode of the analog-to-digital converter;

When the scene mode is the night scene mode, the processing circuit configures the resolution of the output mode of the second analog-to-digital converter and the third analog-to-digital converter to be smaller than or equal to the resolution of the first analog-to-digital converter and the fourth analog-to-digital converter The resolution of the output mode of the analog-to-digital converter.
The image sensor according to any one of claims 1-9, wherein the pixel includes a plurality of sub-pixels, wherein each of the sub-pixels in the same pixel shares the same floating diffusion region; the pixel circuit includes a plurality of photoelectric conversion elements one-to-one corresponding to the sub-pixels, the pixel circuit is used to transfer the charge generated by at least one photoelectric conversion element in the same pixel to the floating diffusion area for accumulation, and output the an analog signal corresponding to the charge in the floating diffusion;

The conversion circuit is further used to read out the converted digital signal together with the pixel circuit based on a full-resolution output mode or an addition mode, wherein the full-resolution mode is used to read out the converted digital signal in units of the sub-pixels The digital signal, the addition mode is used to read out after analog-to-digital conversion the total charges accumulated in the floating diffusion region of all sub-pixels in the same pixel in units of the pixel.
The image sensor according to any one of claims 2-9, wherein the pixel includes a plurality of sub-pixels, wherein each of the sub-pixels in the same pixel shares the same floating diffusion area; the pixel circuit includes a plurality of photoelectric conversion elements one-to-one corresponding to the sub-pixels, the pixel circuit is used to transfer the charge generated by at least one photoelectric conversion element in the same pixel to the floating diffusion area for accumulation, and output the an analog signal corresponding to the charge in the floating diffusion;

The conversion unit includes a fifth analog-to-digital converter connected to the pixel circuit of the first pixel, a sixth analog-to-digital converter connected to the pixel circuit of the second pixel, and a sixth analog-to-digital converter connected to the pixel circuit of the third pixel A seventh module converter connected and an eighth analog-to-digital converter connected to the fourth pixel; wherein,

The conversion unit also includes a first switch unit connected to the output terminals of each of the analog-to-digital converters, and the conversion circuit is also used to work with the pixel circuit based on the full-resolution output mode or the first-stage combined output mode to read out the converted digital signal, wherein the full resolution mode is used to read out the digital signal in the unit of the sub-pixel, and the first-stage combined output mode is used to read out the digital signal in the unit of the pixel The digital signal is read out.
The image sensor according to claim 11, wherein when the converting unit includes four analog-to-digital converters, the pixel unit is configured with a first column control line, a second column control line, a third column control line and The fourth column control line, the pixel circuit of the first pixel is connected to the first column control line through the first switch, the pixel circuit of the second pixel is connected to the third column control line through the second switch, The pixel circuit of the third pixel is connected to the second column control line through the third switch, and the pixel circuit of the fourth pixel is connected to the fourth column control line through the fourth switch, wherein the first The column control line, the second column control line, the third column control line, and the fourth column control line are respectively connected with the first analog-to-digital converter, the second analog-to-digital converter, the third analog-to-digital converter, and the fourth analog-to-digital converter. The converters are connected in one-to-one correspondence.
The image sensor according to claim 12, wherein when the converting unit includes eight analog-to-digital converters, the converting unit further includes a fifth analog-to-digital converter, a sixth analog-to-digital converter, a seventh analog-to-digital converter converter, an eighth analog-to-digital converter; wherein,

The pixel unit is also configured with a fifth column control line, a sixth column control line, a seventh column control line, and an eighth column control line, and the pixel circuit of the first pixel is controlled by the fifth switch and the fifth column. The pixel circuit of the second pixel is connected to the control line of the sixth column through the sixth switch, and the pixel circuit of the third pixel is connected to the control line of the seventh column through the seventh switch. The pixel circuit of four pixels is connected to the eighth column control line through the eighth switch; wherein, the fifth column control line, the sixth column control line, the seventh column control line and the eighth column control line are connected to the eighth column control line respectively. The fifth analog-to-digital converter, the sixth analog-to-digital converter, the seventh analog-to-digital converter, and the eighth analog-to-digital converter are connected in one-to-one correspondence.
The image sensor according to claim 13 , wherein the first stage combined output mode comprises at least one of an additive mode and a mixed mode, wherein,

The adding mode is: read out after performing analog-to-digital conversion on the total charges accumulated in the floating diffusion area of all sub-pixels in the same pixel;

The mixing mode is: the first digital signal output after analog-to-digital conversion of the first analog signal accumulated in the floating diffusion area by the first part of sub-pixels in the same pixel, and the first digital signal output by the second part of sub-pixels in the same pixel The second analog signal accumulated in the floating diffusion area is subjected to analog-to-digital conversion and output as a second digital signal for averaging and then read out; wherein the first part of sub-pixels and the second part of sub-pixels jointly constitute the pixel.
The image sensor according to claim 13, wherein the converting unit further comprises:

A plurality of storage averaging units, the first ends of the plurality of storage averaging units are respectively connected to a plurality of analog-to-digital converters through the first switch unit, and the second terminals of the storage averaging units are connected to the The processing circuit is connected to store the digital signals output by the analog-to-digital converter in partitions, and perform an average operation on the digital signals stored in partitions; wherein,

The conversion circuit is also used to read out the converted digital signal based on the digital average mode together with the pixel circuit.
The image sensor according to claim 15, wherein the digital average mode is: respectively performing analog-to-digital conversion on the charges generated by each sub-pixel in the same pixel in time division, and converting each of the converted digital signals Read out after averaging.
The image sensor according to claim 11, wherein the conversion circuit is further configured to read out a digital signal based on a second-level binning output mode, wherein the second-level binning output mode is used in the pixel unit in The digital signal is read out in units of 2 pixels, wherein the 2 pixels are located on the first diagonal line or the second diagonal line of the pixel unit.
The image sensor according to claim 17, wherein the conversion unit further includes a first switch unit connected to the output terminals of each analog-to-digital converter, wherein the first switch unit includes four switches, one switch connected Between the first analog-to-digital converter and the third analog-to-digital converter, another switch is connected between the second analog-to-digital converter and the fourth analog-to-digital converter, and another switch is connected to Between the first analog-to-digital converter and the second analog-to-digital converter, another switch is connected between the third analog-to-digital converter and the fourth analog-to-digital converter, so that the conversion circuit A digital signal is read out based on the second stage combined output pattern.
The image sensor according to claim 2, wherein the pixel unit comprises a pixel array of 2 rows and 2 columns, arranged in the following manner:

W A

A W

W represents a panchromatic pixel; A represents a first color pixel among the plurality of color pixels.
A camera assembly, comprising:

lens; and

The image sensor according to any one of claims 1-18, wherein the image sensor is capable of receiving light passing through the lens, and cooperates with the lens to form an image.
A mobile terminal, comprising:

casing; and

The camera assembly of claim 20, said camera assembly being combined with said housing.