CN101272446A - Capacitance storage mode row reading circuit used for image sensor - Google Patents
Capacitance storage mode row reading circuit used for image sensor Download PDFInfo
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- CN101272446A CN101272446A CNA2007100569563A CN200710056956A CN101272446A CN 101272446 A CN101272446 A CN 101272446A CN A2007100569563 A CNA2007100569563 A CN A2007100569563A CN 200710056956 A CN200710056956 A CN 200710056956A CN 101272446 A CN101272446 A CN 101272446A
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- 238000000034 method Methods 0.000 claims abstract description 5
- 230000003071 parasitic effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 11
- 238000005070 sampling Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The invention introduces a column readout circuit used on a CMOS image sensor. The circuit stores photoelectrical signals and reset signals through an MOS capacitance and then redistributes the electric charge through a signal bus and a reset bus in order to re-demarcate the voltage output. By adopting the method, the column readout circuit replaces the original column preamplifier, obviously reduces the column fix mode noise caused by the column amplifier and improves the image quality.
Description
Affiliated technical field---
The present invention relates to the application of cmos image sensor, the signal that can be used to be similar to two-dimensional array is more widely read the demarcation again with signal level.
Background technology---
The cmos image sensor chip is a kind of low-power consumption " camera system on the sheet " at a high speed.Imageing sensor comes images acquired by two-dimentional photosensitive pixel array in large scale, light signal is converted to after the signal of telecommunication of simulation, the amplifier of being read in the treatment circuit by signal amplifies, and is directly changed into corresponding digital signal and correspondence then and reverts to image output.
Cmos image sensor has two-dimentional photosensitive pixel array in large scale, and its reading circuit generally is an one dimensional linear array.Generally, for the imageing sensor that adopts the rolling type exposure, the shared public output memory node of the pixel of same row.Like this when the row selector gating during certain delegation, each row picture element signal in this delegation is exported simultaneously, and carries out the output and the amplification of signal at the output node of every row, then row selector gating next line again, so move in circles, the signal in all pixels is all exported.
In cmos image sensor, generally also utilize row reading circuit to eliminate the thermal noise of pixel, fixed pattern noise and some other noise.This is a basic principle of having used two samplings (Double Sample) technology, in the sampled pixel integrated signal, the reset signal of in the reset cycle, also sampling, in row reading circuit, deduct reset signal then, so just the fixed pattern noise in the pixel is eliminated substantially with the light induced signal.
In row reading circuit, need sample with electric capacity and store photoinduction signal and reset signal, generally adopt polysilicon or metal to form these capacitors, but such electric capacity have bigger area usually, can increase the cost of entire chip.And adopt the metal-oxide-semiconductor capacitor can effectively reduce area, save cost.If but the mos capacitance of employing PMOS type, power supply noise can be coupled and direct interference signal with signal; If adopt the mos capacitance of NMOS type, need ask the voltage of photoinduction signal and reset signal to be higher than the threshold voltage of metal-oxide-semiconductor, so can consider to adopt the NMOS pipe of low threshold value to do the electric capacity use.
Simultaneously, in modern technologies, general demarcation again or the amplification of adopting column amplifier that the photosignal and the reset signal of the collection of row reading circuit are carried out level, thus further eliminate the noise of row reading circuit and provide the signal level that needs for the input of analog to digital converter.One of the every row of column amplifier adopt the structure of fully differential usually, and amplifier of each row should be identical in the ideal case, so just can not cause the row fixed pattern noise.And in fact because the restriction of technological level can't accomplish that all column amplifiers are same fully.For example the offset voltage of each column amplifier all is not quite similar, and will cause row fixed pattern noise (Column FPN) like this.The row fixed pattern noise can produce longitudinal stripe on image, thereby influences the quality of image.
Therefore, need improve the performance of column amplifier technically, reduce its offset voltage, thereby reduce the row fixed pattern noise, but this can increase the complexity of circuit.Therefore need a kind ofly can demarcate output signal level again, have the row reading circuit of less row fixed pattern noise again.
Summary of the invention---
In existing technology, the signal read circuit structure of using column amplifier adopts the switching capacity in-phase amplifier shown in figure one, and input links to each other with the output of two samplings.The basic functional principle circuit is divided into two groundwork states, state one, and S1=1, circuit passes through C
1Long integral output signal Vsig samples; State two, S1=0, the short integral output signal Vrst of circuit sampling enters amplification stage simultaneously with output signal V
Out=V
Ref-(V
Rst-V
Sig) C
1/ C
2Delivering to the back one-level handles.Promptly, both voltage differences are delivered on the sampling capacitance of ADC by two samplings.Consider the offset voltage of column amplifier self, the transmission equation of the circuit after promptly X and X ' point does not wait is as follows:
(V
sig-N
PIXEL-V′
ref)C
1+(V
ref-V′
ref)C
2＝(V
rst-N
PIXEL-V′
ref)C
1+(V
out-V′
ref)C
2
N wherein
PIXELFixed pattern noise (Pixel FPN) for pixel: output signal is:
Comprise the row fixed pattern noise that constitutes by the column amplifier offset voltage as can be seen in this formula, reduced signal to noise ratio.
By top analysis as can be seen, adopt the signal read circuit of column amplifier can cause the row fixed pattern noise inevitably.If reduce or eliminate the row fixed pattern noise, then need increase noise canceller circuit, make structure complicated more undoubtedly, carry out difficulty more.
Therefore the invention provides a kind of be used to read the photoinduction signal that produces by pixel and the row reading circuit of reset signal.This circuit can be demarcated output signal level again, and it is simple to have less row fixed pattern noise and structure and implementation again.
The technical solution adopted for the present invention to solve the technical problems is: this circuit mainly contains two parts and forms.The one, the reset signal branch road, it comprises the mos capacitance device that is used for storage reset signal and the partial reset bus of the first order, between first order storage capacitance and the pixel, and and second level reset bus between connect with switch respectively, last output is connected to the digital programmable gain amplifier (DPGA) of next stage by buffering buffer; The 2nd, the photosignal branch road, its structure and reset signal branch road are in full accord, and the purpose of doing like this is exactly in order to eliminate the influence of row fixed pattern noise as far as possible fully.This structure gets on except producing main modular---the column amplifier of row fixed pattern noise from design.Adopted the structure of capacitor array and bus to substitute column amplifier, the level value that has utilized electric capacity in the capacitor array and bus capacitance signal charge to be reallocated again demarcation signal.
This invention can substitute the row preamplifier module in the general cmos image sensor system configuration, thereby avoided the influence of the row fixed pattern noise of column amplifier introducing, therefore can eliminate the respectively difference between the row that circuit brings, being reflected on the imageing sensor is exactly the row fixed pattern noise that has reduced image, can not produce the row striped on the image.In addition, structurally also than using column amplifier to come simply, it is convenient to carry out, and is easier to realize.
Description of drawings---
By the execution mode explanation, and be described in detail in conjunction with the accompanying drawings, will understand more easily, simultaneously the advantage of better understanding above-mentioned feature of the present invention and having.
Fig. 1 is the reading circuit modular structure schematic diagram of the employing column amplifier in the existing technology.
Fig. 2 is the schematic diagram that adopts the reading circuit of capacitor array storage among the present invention.
Fig. 3 is the sequencing control figure that adopts the reading circuit of capacitor array among the present invention.
In Fig. 2, M1～M4 pipe is the pixel elemen-tary units structure, and wherein M1～M3 pipe is three pipe active pixel structures, and the M4 pipe is that the offset of pixel, D are anti-inclined to one side photodiode.Rst1 and Sig1 are the gating switch of pixel to the capacitance stores array, and Rst2 and Sig2 are for to be connected the gating switch of capacitance stores array to reset bus and signal bus, and Rst3 and Sig3 are respectively the reset switch of reset bus and signal bus.C1 and C2 are respectively the capacitor array of storage reset signal and the capacitor array of storage photoinduction signal, all adopt the implementation of MOS switching capacity; C3 and C4 are respectively the capacitance that reset bus and signal bus produce.Buf1 and Buf2 are respectively the output buffer of reset signal and photoinduction signal, and DPGA is the digital programmable gain amplifier.
Embodiment---
The structure of the reading circuit of employing capacitor array storage as shown in Figure 2.Its residing position in system for convenience of explanation, this figure gives the structure of front pixel elemen-tary units, i.e. M1～M4 pipe.
According to sequencing control shown in Figure 3, adopt the basic functional principle of the signal read circuit of capacitance storage mode to be: Sig1 is at first closed, and signal voltage is sampled on the capacitor C 2, and pixel resets then, and the Rst1 closure samples resetting voltage on the capacitor C 2.Be strict with sampling capacitance C1=C2, two bus capacitance Crstbus=Csigbus in the design.Wherein Crstbus represents reset bus electric capacity, Csigbus representation signal bus capacitance.In sampling, reset bus and signal bus also reset to ground level by switch Rst3 and Sig3.Rst2 and Sig2 closure then, the electric capacity that reset capacitance C1 goes up charge stored and reset bus carries out electric charge reallocates, and reaches the output voltage that resets when stablizing and is:
Signal output voltage
For example if the fruit signal voltage is 1V, sampling capacitance is 1PF, and bus capacitance is 2PF, and then output voltage is 1/3V.
The bus output voltage is by electric charge reallocation decision, and whenever reading a pixel data all needs bus is carried out reset operation.Require the bus coupling in the design as far as possible, can on domain, adopt corresponding techniques to reduce to greatest extent not match.For example to guarantee two residing surrounding environment unanimities of bus as much as possible, reduce the influence of parasitic parameter like this bus capacitance.
Claims (9)
1. be used to read and go forward side by side that line level is demarcated the photoinduction signal of pixel output and the row reading circuit of reset signal comprises:
The reset signal branch road, it comprises the mos capacitance device that is used for storage reset signal of the first terminal and the reset bus of second terminal, between the first end storage capacitance and the pixel, and and the second end reset bus between connect with switch respectively, simultaneously reset bus by switch optionally ground connection reset; And
The photosignal branch road, what it comprised the first terminal is used to store the mos capacitance device of photosignal and the signal bus of second terminal, between the first end storage capacitance and the pixel, and and the second end signal bus between connect with switch respectively, the synchronous signal bus by switch optionally ground connection reset.
2. the reading circuit of claim 1, described pixel cell are meant three pipe active pixel structures, and it comprises reset transistor, separator tube and gate tube.
3. the reading circuit of claim 1, the electric capacity that is used to store photosignal and reset signal adopts the mos capacitance device of N pipe, wherein the NMOS pipe has low threshold voltage, and the level value of photosignal and reset signal must be higher than the threshold voltage of the first terminal mos capacitance device.
4. the reading circuit of claim 1 further is included in the output buffer (buffer) that is provided with between described second terminal and the lead-out terminal.
5. the reading circuit of claim 1, described reset bus is two metal wires that its length is consistent with the pel array width with signal bus, and two various attribute unanimities of bus, and surrounding environment unanimity of living in.
6. the reading circuit of claim 1 further comprises the digital programmable gain amplifier (DPGA) that is used to receive from the output signal of reset signal branch road and photosignal branch road.
7. read the photosignal of pixel and the method for reset signal is from row reading circuit:
Described photosignal and reset signal are stored in respectively on two mos capacitance devices of the first terminal;
Then signal bus and reset bus being carried out ground connection resets;
Finish and reset, the mos capacitance of storage photosignal and reset signal is connected with the electric capacity of signal bus and reset bus respectively, finish the reallocation of electric charge, again the level value of the nominal light signal of telecommunication and reset signal;
Output to the input of follow-up DPGA by the output buffer of two bars branch roads.
8. the method for claim 8 wherein require the mos capacitance device to be operated in linear zone, and the voltage of photosignal and reset signal is higher than the threshold value of mos capacitance device.
9. the method for claim 8, the parasitic capacitance of signal bus and the parasitic capacitance of reset bus are mated fully and with the mos capacitance of the first terminal same order are arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100569563A CN101272446A (en) | 2007-03-20 | 2007-03-20 | Capacitance storage mode row reading circuit used for image sensor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100569563A CN101272446A (en) | 2007-03-20 | 2007-03-20 | Capacitance storage mode row reading circuit used for image sensor |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605201B (en) * | 2008-12-24 | 2011-06-22 | 昆山锐芯微电子有限公司 | Image sensor and column processing circuit thereof |
| CN102164251A (en) * | 2011-05-25 | 2011-08-24 | 格科微电子（上海）有限公司 | Signal processing circuit and signal processing method for image sensor |
| CN104079840A (en) * | 2013-03-28 | 2014-10-01 | 恒景科技股份有限公司 | Image sensor |
| CN106454163A (en) * | 2011-04-19 | 2017-02-22 | 阿尔塔传感器公司 | Image sensor with hybrid heterostructure |
| CN106791507A (en) * | 2016-11-30 | 2017-05-31 | 上海集成电路研发中心有限公司 | High dynamic cmos pixel unit and its signal acquisition method |
-
2007
- 2007-03-20 CN CNA2007100569563A patent/CN101272446A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605201B (en) * | 2008-12-24 | 2011-06-22 | 昆山锐芯微电子有限公司 | Image sensor and column processing circuit thereof |
| CN106454163A (en) * | 2011-04-19 | 2017-02-22 | 阿尔塔传感器公司 | Image sensor with hybrid heterostructure |
| CN102164251A (en) * | 2011-05-25 | 2011-08-24 | 格科微电子（上海）有限公司 | Signal processing circuit and signal processing method for image sensor |
| CN102164251B (en) * | 2011-05-25 | 2014-04-02 | 格科微电子（上海）有限公司 | Signal processing circuit and signal processing method for image sensor |
| CN104079840A (en) * | 2013-03-28 | 2014-10-01 | 恒景科技股份有限公司 | Image sensor |
| CN104079840B (en) * | 2013-03-28 | 2017-05-17 | 恒景科技股份有限公司 | Image sensor |
| CN106791507A (en) * | 2016-11-30 | 2017-05-31 | 上海集成电路研发中心有限公司 | High dynamic cmos pixel unit and its signal acquisition method |
| CN106791507B (en) * | 2016-11-30 | 2019-08-20 | 上海集成电路研发中心有限公司 | High dynamic cmos pixel unit and its signal acquisition method |
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Open date: 20080924 |