JP5106596B2 - Imaging device - Google Patents

Description

  The present invention relates to a bias signal supply method for impedance conversion means.

  As a conventional solid-state imaging device, each signal charge generated in each pixel is not read as it is, but after converting these signal charges into voltage or current in each pixel and amplifying each signal voltage or signal current, Reading from a pixel via a scanning circuit has been proposed, and this is called an amplifying solid-state imaging device. FIG. 8 shows an amplification type MOS sensor configuration which is this conventional amplification type solid-state imaging device.

  In FIG. 8, the signal charge accumulated in the photodiode 1 disposed in the photoelectric conversion cell is read as a voltage to the vertical output line 8 by the amplification transistor 4. At this time, since the source follower circuit is formed by the amplification transistor 2 and the load transistor 9 as a constant current source, a voltage corresponding to the signal charge amount of the photodiode 1 is read from the vertical output line 8. Here, the photoelectric conversion cell includes a reset transistor 3 for resetting the photodiode 1 and a selection MOS transistor 5 for selecting a cell to be read to the vertical output line 8 in addition to the above.

  In the solid-state imaging device in which the photoelectric conversion cells having such a configuration are two-dimensionally arranged, fixed pattern noise corresponding to the threshold variation of the amplification transistor 4 is generated and the image quality is deteriorated. A circuit has been proposed. The configuration and operation of the noise cancellation circuit will be described with reference to the timing chart of FIG.

  By applying the pulse 101 to the selection signal line 10-1 from the vertical shift register 91, the row of the amplification transistors 4-1-1, 4-1-2,. Activate. At this time, the output signal voltage corresponding to the signal charge accumulated in the photodiodes 1-1-1, 1-1-2,... Is output to the vertical output line 8 (8-1, 8-2,...). Is read out. While the pulse activating each cell of the solid-state imaging device is at the “H” level (pulse 101), the “H” voltage is applied to the gate of the clamp transistor 14 (14-1, 14-2,...). (Pulse 102) is applied, the clamp transistor is turned on, and the vertical output lines 15 (15-1, 15-2,...) Are clamped to the clamp voltage 22.

  Thereafter, by applying a voltage “H” (pulse 104) to the reset signal line 6 (6-1, 6-2,...), The photodiode 1 (1-1-1, 1-1) is applied. 2) is reset. Since this reset voltage appears on the vertical output line 8 (8-1, 8-2,...), This voltage is applied to the vertical output line 15 (on the clamp capacitor 13 (13-1, 13-2,...). 15-1, 15-2, ...). By aligning the base voltage for each photoelectric conversion cell with this clamp voltage, variations in the threshold voltage of the MOS transistor can be suppressed.

  Next, by turning on the sample-hold transistors 92 (92-1, 92-2,...), Signals are transmitted to the vertical output lines 16 (16-1, 16-2,...). Then, the selection pulses 105, 106,... From the horizontal shift register 99 sequentially select the horizontal selection transistors 17 (17-1, 17-2,...), Whereby the signal voltage of the selected row is read out. .

  Thus, only the voltage change of the vertical output line 8 after resetting the photodiode 1 can be taken out to the vertical output line 16, so that the influence of the threshold variation of the amplification transistor 4 can be suppressed. In particular, by removing noise components from the output voltage of each solid-state imaging device that eliminates the influence of variations in threshold voltage, it is possible to obtain only the output of signal components from which variations have been eliminated on the horizontal output line.

  However, in the conventional example, when the signal of each sensor cell is to be read out at high speed, the amplification transistor 4 of each photoelectric conversion cell needs to drive the clamp capacitor at high speed. It is necessary to reduce the output impedance of the source follower circuit composed of the amplification transistor 4 and the load transistor 9 to some extent.

  For this purpose, it is necessary to increase the ratio (W / L) of the gate width (W) and gate length (L) of the amplification transistor 4 and to increase the bias drain current by the load transistor 9. Since the amplification transistor 4 exists in each photoelectric conversion cell, an increase in the gate width leads to an increase in the chip area of the solid-state imaging device, which is not preferable. An increase in the bias drain current due to the load transistor 9 is also a problem because it naturally increases the power consumption.

  If the clamp capacitance is reduced, high speed driving is possible without causing the above problem. However, if the capacitance value of the clamp capacitance is reduced, random noise generated between the sensor cell and the readout circuit including the clamp capacitance is achieved. However, since it is proportional to √1 / C (C is the capacitance value of the clamp capacitor) (the description is omitted here), the problem of an increase in random noise occurs. Further, the smaller the clamp capacitance, the more easily affected by the parasitic capacitance depending on the layout in the chip, leading to an increase in variations in sensor signals.

In order to solve the above problem, impedance conversion means provided with pixels each having a photoelectric conversion unit and an amplification transistor for amplifying a signal generated in the photoelectric conversion unit arranged in a matrix and provided for each column of the pixels And first switch means for switching between a supply state and a supply stop state of the bias to the impedance conversion means,
A capacitor disposed in an electrical path between the impedance conversion unit and the pixel; a second switch unit that controls conduction between the pixel and the capacitor; the first switch unit; and the second switch unit. Drive means for controlling the operation of the switch means, and the drive means supplies bias to the impedance conversion means by the first switch means before conducting the second switch means. From the first state in which the bias is supplied to the impedance conversion unit, the impedance conversion unit includes a transistor, a bias current source that supplies a bias current to the transistor, A switch disposed between a drain of the transistor and a power source for supplying a drain voltage to the drain, and the switch Said first switching means to provide an imaging apparatus characterized that you operate synchronously.

  In the present invention, it is possible to read a signal from the photoelectric conversion unit at a high speed and obtain a signal with less noise components.

It is a figure showing the whole equivalent circuit of a solid-state image sensor. It is a figure showing the electric potential change of 15 of FIG. It is a figure showing a part of solid-state image sensor. It is a figure showing a part of solid-state image sensor. It is a figure showing a part of solid-state image sensor. FIG. 6 is a diagram illustrating a timing chart for operating the circuit of FIG. 5. It is a figure showing an imaging device. It is a figure showing the conventional solid-state image sensor. It is a figure showing the timing chart for operating the conventional solid-state image sensor.

  FIG. 1 shows a solid-state imaging device in which photoelectric conversion cells are two-dimensionally arranged in a horizontal direction and a vertical direction.

  1 is a photodiode which is a photoelectric conversion unit, 2 is a transfer switch, 3 is a reset switch, 4 is an amplification transistor, 5 is a selection switch, 6 is a reset signal line driven from a vertical shift register, 7 is a transfer signal line, 9 Is a constant current transistor for supplying a bias current of the amplification transistor 4, and 10 is a selection signal line.

  Reference numerals 11 and 28 denote source follower circuits which are impedance conversion means for performing impedance conversion of the sensor signal appearing on the vertical signal line 8 and drive the clamp capacitor 13, and 11 is a source which receives the sensor signal at the gate and outputs from the source. A follower transistor (drive transistor), 28 is a constant current transistor (load element) for supplying a bias current to the source follower transistor 11, 12 is a switch for ON / OFF control of the current of the constant current transistor 28, and 14 is a clamp capacitor 13 In addition, a clamp switch for supplying a reference voltage applied to the terminal 22, 17 a horizontal transfer switch, 18 a common horizontal output line, and 19 for converting a signal charge sent to the common horizontal output line 18 into a voltage. , 20 is an output amplifier, 21 is an output terminal, 23, 2 Is a constant current circuit for supplying a voltage to the constant current transistor 28, 25 and 26 are similarly circuits for supplying a reference voltage to the 9 constant current transistors, and 27 is a switch 12 for switching a bias current supplied by the constant current transistor. Is a pulse voltage input terminal for driving.

  The switch 12 is turned on only when the source follower circuits 11 and 28 need to drive the clamp capacitor 13, and supplies the current of the constant current circuits 23 and 24 to the source follower circuit 11, so that the constant current circuit 23, Compared with the case where 24 currents are supplied, the power consumed here can be greatly reduced.

  As described above, when the switch 12 is turned on at the timing when the source follower circuit 11 drives the capacitor 13, the change in the potential of the node 15 after the switch 12 is turned off is shown in FIG. The time t0 is when the switch 12 is turned from ON to OFF, and the source follower transistor 11 has its drain connected to the power supply, so that the source follower transistor 11 has a voltage corresponding to the signal voltage applied to its gate terminal. The node 15 is charged with a time constant determined by the sub-threshold region characteristics, and the potential increases.

  One terminal of the clamp capacitor 13 is in a high impedance state until the horizontal transfer switch to which the terminal is connected is turned on, so that the charge of the capacitor is preserved. Therefore, the node 16 also has the same potential fluctuation as the node 15 and rises. To do.

  The potential of the common horizontal output line is kept at the reference voltage applied to the terminal 22 because the virtual ground in the amplifier 20 is established in the circuit configuration.

  t1 is the time when a certain horizontal transfer switch (for example, 17-1 in FIG. 1) is turned on, t2 is the time when another horizontal transfer switch (for example, 17-2) is turned on, and the same time constant from t0. Thus, the potentials of the nodes 15-1 and 15-2 rise, but the transfer switches 17-1 and 17-2 are turned on at different timings. The change in voltage at the time of transition to is different between the nodes 16-1 and 16-2, the difference in potential change also appears at the node 15, and the parasitic capacitance between the gate and source of the source follower transistor 11 shown in FIG. Due to the coupling by Cgs, the change in the signal potential appearing on the vertical output lines 8 (8-1, 8-2) is also different.

  Therefore, even when the same signal potential is applied to the two vertical output lines 8-1 and 8-2, the output impedance of the amplification transistor 4 in the electric conversion cell is not low, and therefore occurs when the horizontal transfer switch is turned on / off. The change in potential cannot be suppressed, and the output signal potential fluctuates, generating noise called fixed pattern noise.

  FIG. 4 shows a circuit configuration in which the above-described effect appears more prominently. A sample / hold circuit is inserted between the photoelectric conversion cell and the vertical output line source follower 11.

  Other element numbers are the same as those in FIG. The potential change that occurs when the horizontal transfer switch is turned on is that the signal potential stored in the hold capacitor changes by a value determined by the charge division between the gate-source parasitic capacitance Cgs of the source follower 11 and the hold capacitor of the sample / hold circuit. End up.

  As shown in FIG. 4, when a sample / hold circuit is inserted between the sensor cell and the vertical signal line source follower, the gate-source parasitic capacitance Cgs of the source follower transistor is a part of the hold capacitance of the S / H circuit. The Cgs differs depending on the operation region of the MOS transistor. When the timing of turning on the bias current supply switch 12 of the source follower is set to be after the S / H switch is turned off, the operation of the Cgs is performed. When the bias current switch is turned on, the gate potential of the source follower fluctuates by an amount corresponding to the variation depending on the region. Since this Cgs varies due to manufacturing variations in the gate oxide film process, there is a case where fixed pattern noise occurs in the gate potential.

  Therefore, by inserting a switch between the drain terminal of the vertical output line source follower transistor 11 and the power supply, and driving in synchronization with the ON / OFF timing of the bias current supply switch, the bias current supply switch is turned OFF. In this case, the current supply source for charging the node 15 is eliminated, and the potentials of the nodes 15 and 16 do not rise until the horizontal transfer switch ON timing, so that a signal with less noise components can be obtained.

  Further, the ON timing of the bias current switch is set to be before the ON timing of the S / H circuit provided between the photoelectric conversion cell and the vertical output line source follower in FIG. Cgs when the vertical line source follower is ON is added to the hold capacity of the S / H circuit, and a signal with less noise component is obtained.

  The above point will be specifically described below.

  FIG. 5 shows only the portion from the vertical output line to the common horizontal output line in FIG. 1, and in particular, a sample and hold circuit (sample and hold circuit) is provided between the vertical output line 8 and the source follower transistor 11. A switch 31 and a sample hold capacitor 32) are inserted.

  A switch 29 is inserted between the source follower transistor 11 and the power supply line 32. Then, the switch 29 is driven by the same clock line 27 ′ (synchronization means) as that for driving the bias current supply switch 12 so that the drive of the switch 29 and the bias current supply switch is synchronized.

  By doing so, when the supply of the bias current of the source follower transistor 11 is stopped, the drain of the source follower 11 is simultaneously disconnected from the power supply line 32 and there is no current path for charging the node 15.

  FIG. 6 particularly shows the relationship between the ON / OFF timing of the switches 12 and 29 and the timing of other switches.

  In the figure, 30 indicates a pulse for driving the S / H switch, 27 indicates a pulse applied to the terminal 27 for driving the switches 12 and 29, and 31 indicates a pulse for driving the horizontal transfer switch 17.

  Before the pulse 101 for turning on the S / H switch becomes HI, the pulse 102 is applied to the terminal 27, the switches 12 and 29 are turned on, and the Cgs of the source follower 11 is fixed to the value when the transistor is turned on. After the S / H switch is turned off, the switches 12 and 29 are also turned off. Next, before the horizontal transfer switch 17 is turned on, the switches 12 and 29 are turned on again by the pulse 103, and the switch 17 is turned on by the pulse 104. The clamp capacitor 13 can be driven.

  FIG. 5 shows a case where the source follower transistor 11 is an NMOS. In the case of a PMOS, the switch 29 can be easily inserted between its drain terminal and GND (or a low potential power supply line). It is.

  As shown above, in the case of an NMOS source follower transistor, a switch is inserted between the drain terminal and the high potential voltage source, and in the case of a PMOS source follower transistor, a switch is inserted between the drain terminal and the low potential voltage source. The source follower output terminal potential when the bias current supply is stopped by turning off the switch by performing ON / OFF control almost in synchronization with the switch for controlling the supply of the bias current to the source follower, The rise due to parasitic capacitance charging was eliminated, and the fluctuation of fixed pattern noise was suppressed.

  In addition, when an S / H circuit is inserted between the vertical output line and the source follower, the S / H switch OFF → ON timing is relative to the bias current supply control switch OFF → ON timing. The generation of the fixed pattern noise was suppressed by delaying the ON / OFF timing of the S / H switch earlier than the bias current switch OFF → ON.

  Based on FIG. 7, an imaging apparatus using the solid-state imaging device described above will be described.

  In FIG. 7, 101 is a barrier that serves as a lens switch and a main switch, 102 is a lens that forms an optical image of a subject on the solid-state image sensor 104, 103 is a diaphragm for changing the amount of light passing through the lens 102, and 104 is A solid-state imaging device 105 for capturing a subject imaged by the lens 102 as an image signal, a gain variable amplifier unit 105 that amplifies an image signal output from the solid-state imaging device 104, and a gain correction circuit for correcting a gain value An image signal processing circuit including a unit, 106 is an A / D converter that performs analog-to-digital conversion of an image signal output from the solid-state image sensor 104, and 107 is a variety of image data output from the A / D converter 106. A signal processing unit 108 that corrects the data and compresses the data; D converter 106, timing generation unit for outputting various timing signals to signal processing unit 107, 109 is an overall control / arithmetic unit for controlling various calculations and the entire still video camera, and 110 is for temporarily storing image data The memory unit 111 includes an interface unit for performing recording or reading on a recording medium, 112 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 113 is for communicating with an external computer or the like. It is an interface part.

  Next, the operation of the still video camera at the time of shooting in the above configuration will be described.

  When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the imaging system circuit such as the A / D converter 6 is further turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state imaging device 4 is converted by the A / D converter 106 and then sent to the signal processing unit 107. Entered.

  Based on this data, exposure calculation is performed by the overall control / calculation unit 109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

  Next, based on the signal output from the solid-state image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / calculation unit 109.

  Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Further, the image processing may be performed by directly entering the computer or the like through the external I / F unit 113.

11 Source follower transistor 12 Bias current supply switch 13 Clamp capacitance 28 Constant current transistor 29 Switch 31 Sample hold switch 32 Sample hold capacitance

Claims (5)

Pixels having photoelectric conversion units and amplification transistors that amplify signals generated in the photoelectric conversion units are arranged in a matrix,
Impedance conversion means provided for each column of pixels;
First switch means for switching between a supply state and a supply stop state of bias to the impedance conversion means;
A capacitor disposed in an electrical path between the impedance converter and the pixel;
Second switch means for controlling conduction between the pixel and the capacitor;
Drive means for controlling the operation of the first switch means and the second switch means;
The driving means includes
Before the second switch means is turned on, the first switch means starts supplying the bias to the impedance converting means from the first state in which the supply of the bias to the impedance converting means is stopped. Change to the state of 2 ,
The impedance converting means includes
A transistor,
A bias current source for supplying a bias current to the transistor;
A switch disposed between the drain of the transistor and a power source for supplying a drain voltage to the drain;
Imaging device and the said switch first switching means is characterized that you operate synchronously. The driving means includes
After the second state, before the third state in which the supply of the bias to the impedance conversion unit is stopped, the second switch unit completes the sample and hold operation to the capacitor. The imaging apparatus according to claim 1, wherein the imaging apparatus is characterized. The imaging apparatus according to claim 1, wherein the impedance conversion unit is a source follower circuit.   The imaging apparatus according to claim 1, wherein a capacitor that receives a signal from the impedance conversion unit is provided in an output unit of the impedance conversion unit. A lens for imaging light on the photoelectric conversion unit;
An analog / digital conversion circuit for converting a signal from the impedance conversion means into a digital signal;
A signal processing circuit for performing signal processing of a signal from the analog-digital conversion circuit;
The imaging apparatus according to any one of claims 1 to 4, characterized in that it has a.

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