JP2006033816A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize low power consumption and a small area in a reading circuit capable of reading at a high S/N ratio. <P>SOLUTION: This solid-state image pickup device has a plurality of pixels arranged in an array, and performs a reading operation of pixel signals in parallel via a pixel amplifier. The device further has reading circuits CL-i having a plurality of holding capacitances C2i for each holding signal outputs of a plurality of pixel amplifiers, and a common inverted amplifier A1 for reading the signals held in the plurality of holding capacitances while sequentially selecting the signals. The reading circuits are each provided with a switching means SW2i configured so as to be able to connect/disconnect one end of the holding capacitance and a signal output, a second switching means SW4i configured so as to be able to connect/disconnect one end of the holding capacitance and the inverse amplifier output, and a third switching means SW3 configured so as to be able to connect/disconnect the input/output of the inverted amplifier. The other end of the plurality of holding capacitances are commonly connected to the input of the inverted amplifier. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a readout circuit formed on a solid-state imaging device, and particularly to provide a readout circuit that can be realized with a small area and can reduce power consumption in a pixel amplification type CMOS image sensor. .

  As an XY address type solid-state imaging device in which pixels are arranged two-dimensionally, an amplification type imaging device capable of reading an amplified output corresponding to a signal photoelectrically converted for each pixel is known. In particular, pixel amplification type CMOS image sensors that can be realized by a CMOS process are widely applied.

  FIG. 7 shows the configuration of an XY address type solid-state imaging device, and its operation will be described. The pixels 101 are arranged in an array, and each pixel is connected to a row selection line 102 which is a control signal line for row selection and a column signal line 103 for reading out the selected row. These row selection lines are sequentially selected by the vertical selection shift register 104, and the pixel signals of the selected row are read out in parallel to a noise removal circuit 105 provided on each column signal line 103, and temporarily held there. Is done. The output signal of the noise removal circuit is sequentially read out from the video line 108 via the horizontal selection switch 107 controlled by the horizontal selection shift register 106. As described above, in the XY address type solid-state imaging device, it is a general reading method that the pixels selected in units of rows are temporarily held in the noise removal circuit and then sequentially read while selecting the columns. Yes.

  FIG. 8 shows a configuration example of a pixel in a pixel amplification type CMOS image sensor. In FIG. 8, one pixel is formed by three transistors, a photodiode PD, an amplifying transistor M1, a reset transistor M2, and a selection transistor M3. The photodiode PD is connected to a power source via a reset transistor M2, Turning on M2 initializes the photodiode potential. Thereafter, the photodiode potential decreases due to the accumulation of charges generated in response to the incident light, and the signal voltage corresponding to the photodiode potential is amplified as output by the amplification transistor M1 whose gate is connected to the photodiode PD via the selection transistor M3. Read from the vertical signal line 103. As can be seen from this figure, the pixel is connected with two row selection lines 102, a row selection line controlled by Φreset for resetting and a row selection line controlled by Φread for reading. Is done.

  Thus, in a solid-state imaging device having an amplifying element for each pixel, noise caused by variations in characteristics of transistors constituting the pixel becomes a problem, and thus a noise removal circuit for removing this noise component is necessary. This noise removal circuit is based on the operating principle of removing the offset voltage component caused by transistor variation by taking the difference between the pixel signal voltage immediately after reset in each pixel and the pixel signal voltage in the state where photocharge is accumulated. FIG. 9 shows an example of a noise removal circuit, and a specific operation will be described with reference to the timing chart of FIG.

  In FIG. 9, a portion surrounded by a broken line shows an example of the noise removal circuit 105 in FIG. 7, and the same elements as those in FIG. 7 are denoted by the same reference numerals. This configuration is disclosed in Japanese Patent Application Laid-Open No. 64-2354, IEEE Trans. ON ED, Vol. 35, No. 5, May, 1988, "A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensors." It is a noise removal circuit using the clamp circuit described in the above. This noise elimination circuit holds two capacitors C1 and C2 connected in series, a clamp switch SW1 controlled by ΦCL for applying a reference voltage to the midpoint of the capacitors C1 and C2, and the potential VO of C2. The sample-and-hold switch SW2 is controlled by a control signal ΦSH provided between the capacitors C1 and C2.

The operation of this circuit will be described together with the operation of the pixel based on the timing chart shown in FIG. In the timing chart, the control signal is “H” to turn on the switch, and “L” to turn off the switch. The timing period is divided into three. In the period T1, the integrated pixel signal is read, in the period T2, the pixel is reset, and in the period T3, the pixel signal is read immediately after the reset. If the output signal voltages of the pixels in the periods T1 and T3 are V1 and V2, and the charge amounts of the capacitors C1 and C2 in the period T1 are Q1 and Q2, respectively, SW1 and SW2 are both on in the period T1, and Vo = Since it is Vref, Q1 and Q2 are expressed as follows.
Q1 = C1 ・ (Vref−V1) (1)
Q2 = C2 ・ Vref (2)

Next, after performing the reset operation of the pixel in period T2, Q1 'and Q2 when the charges of the capacitors C1 and C2 when the pixel signal voltage V2 is applied to C1 in period T3 are Q1' and Q2 ', respectively 'Is expressed as Equation (3) and Equation (4).
Q1 '= C1 ・ (Vo−V2) (3)
Q2 '= C2 ・ Vo ・ ・ ・ （４）

Since Q1 + Q2 = Q1 '+ Q2' holds according to the law of conservation of charge, the voltage Vo of the capacitor C2 in the period T3 is expressed by Equation (5), and the differential voltage between the pixel signal voltages V1 and V2 with respect to Vref is gain C1 / (C1 + Output in C2). When the signal voltage of this equation (5) is read while the selection switch 107 is sequentially turned on after holding ΦSH in the capacitor C2 and sequentially turning on the selection switch 107, a differential signal from which the noise voltage caused by the variation of the pixel transistor is removed is obtained from the video line. be able to.
Vo = Vref + (V2-V1) ・ C1 / (C1 + C2) (5)
JP-A 64-2354 Japanese Patent No. 2965777

  By using the noise elimination circuit in this way, the difference between the integrated signal voltage V1 and the reset signal voltage V2 is obtained, so that a signal component that is not affected by the offset voltage of the pixel amplifier is output. In the configuration of the noise removal circuit using the clamp circuit shown in FIG. 9, the signal from which noise has been removed is held in a capacitor, and the signal charge held in the capacitor is directly connected to the video line and read. It has the following disadvantages.

  Usually, since the selection switch 107 is connected to the video line 108 by the number of columns, a very large parasitic capacitance exists. Since the parasitic capacitance in this video line becomes a factor that degrades the S / N of the readout output when reading the signal charge of the capacitor C2, it is desirable that the capacitance value C2 be as large as the parasitic capacitance of the video line. When the number of pixels increases and the parasitic capacitance increases, there is a problem that the areas of the capacitors C1 and C2 increase. Furthermore, when the reading speed must be increased, increasing the capacitance C2 requires a reduction in the on-resistance of the selection switch 107 in order to reduce the time constant of the reading circuit. For this purpose, the switch size is increased. Must. However, if the switch size is increased, the parasitic capacitance increases. Therefore, in the readout circuit in which the capacitance as shown in FIG. 9 is directly connected to the video line and read out, the S / N is secured when the number of pixels increases. In addition, there is a problem that the reading speed cannot be increased.

  In addition to the noise removal circuit having the clamp circuit configuration shown in FIG. 9, a noise removal circuit using an inverting amplifier as shown in FIG. 11 is disclosed in Japanese Patent No. 2965777. This noise elimination circuit uses the property that a capacitively coupled inverting amplifier circuit outputs a differential voltage of the input, and stores and compensates for the offset voltage in the inverting amplifier at the time of reset, so that the integrated pixel signal voltage V1 The differential voltage of the pixel signal voltage V2 immediately after the reset is a signal voltage that does not include an offset voltage, and the capacity is read as an amplified output instead of being directly connected to the video line.

In FIG. 11, one end of the capacitor C1 is connected to the pixel output VS side from the column signal line, and the other end of the capacitor C1 is connected to the input of the inverting amplifier A1. A switch SW5 controlled by a control signal ΦR and a capacitor C2 are provided in parallel between the input and output of the inverting amplifier. When the control signal ΦR is 'H', the reference voltage is applied to the inverting amplifier output side terminal of the capacitor C2. , 'L', switch SW6 connected to the inverting amplifier output terminal is connected. The control signal ΦR of the inverting amplifier circuit may be operated at exactly the same timing as ΦCL shown in FIG. By turning ΦR from ON to OFF at the same time as ΦCL in FIG. 10 at the time of reading the pixel signal in the period T1, the pixel signal voltages V1 and SW5 in the ON state (period T1) are in the OFF state (period T3). The pixel signal voltage V2 is inverted and amplified as a differential voltage signal obtained by multiplying the pixel signal voltage V2 by C2 / C1. Here, by applying the reference voltage Vref to the output terminal side of the capacitor C2 at the time of resetting by the operation of the switch SW6, the initial voltage of the inverting amplifier becomes Vref without depending on the offset voltage of the inverting amplifier. The inverting amplifier output Vo has a voltage value shown in Expression (6). By holding this voltage and reading it through the inverting amplifier, the differential voltage from which the noise voltage has been removed can be read out as in the clamp circuit of FIG. 9, and the S / N generated in the read format of FIG. The problem of deterioration can be avoided.
Vo = Vref- (V2-V1) ・ C2 / C1 (6)

  When the video line is driven by the amplifier circuit using the noise removal circuit using the amplifier shown in FIG. 11, the signal output can be read out without being affected by the parasitic capacitance of the video line by increasing the drive capability of the amplifier circuit. Thus, it is possible to read out a high S / N while reducing the capacitances C1 and C2. However, since the configuration shown in FIG. 11 requires an inverting amplifier for each column, if all the inverting amplifiers drive the parasitic capacitance of the video line and can read out at high speed, the power consumption becomes very large. The transistor size of the inverting amplifier must also be increased. In particular, when the number of pixels is large and the parasitic capacitance of the video line is large, it has become clear that even if the capacitances C1 and C2 can be reduced, the chip size cannot be reduced so much by increasing the area of the inverting amplifier.

  As described above, in the readout circuit configuration to the video line used in the conventional noise elimination circuit, the number of columns increases in the readout circuit having an amplifier for each column capable of high S / N. As a result, the power consumption of the amplifier increases and the area occupied by the amplifier also increases. In view of this problem, an object of the present invention is to realize a readout circuit with a small current consumption and a small area while using an amplified output readout method capable of readout with high S / N.

  In order to solve the above problems, a solid-state imaging device according to the present invention includes a plurality of pixels arranged in an array, and performs a pixel signal read operation in parallel via a pixel amplifier. A readout circuit further comprising: a plurality of holding capacitors each holding a signal output of the pixel amplifier; and a common inverting amplifier for sequentially reading out the signals held in the plurality of holding capacitors. The first switching means (SW21 to SW2n) configured to be able to intermittently connect between one end of the storage capacitor and the signal output, and intermittently between the one end of the storage capacitor and the output of the inverting amplifier. Second switching means (SW41 to SW4n) configured to be capable of being connected and third switching means (SW3) configured to be capable of being intermittently connected between the input and output of the inverting amplifier. The other end of the holding capacitor is commonly connected to the input of the inverting amplifier.

  By adopting such a configuration, the held signal output is read out to the readout line via the inverting amplifier, so that a high S / N can be realized. Furthermore, since the number of inverting amplifiers is 1 / n of the number of columns (number of signal outputs output in parallel) (n is the number of holding capacitors connected to a common inverting amplifier), it is occupied by the inverting amplifier. The area can be reduced and the power consumption of the entire inverting amplifier can be reduced. If the number of inverting amplifiers is 1 / n, the number of read selection switches connected on the readout line is also reduced to 1 / n, and the parasitic capacitance of the readout line is reduced. Therefore, the bias current of each inverting amplifier is reduced. It becomes possible to do. Therefore, with such a configuration, it is possible to realize a readout circuit that can perform readout with a high S / N, which is the object of the present invention, and has a small current consumption and a small area.

  In the present invention, a first readout circuit and a first readout circuit each having the storage capacitor, the first switching unit, the second switching unit, the third switching unit, and the inverting amplifier for each signal output Preferably, two readout circuits are provided, and the first readout circuit and the second readout circuit are configured to be able to read out outputs corresponding to the signal outputs of the pixels at different times in parallel. In this manner, by taking the difference between the signal outputs of the first readout circuit and the second readout circuit, noise caused by the pixel offset voltage can be removed, and the first readout circuit and the second readout circuit can be removed. Since the output voltage on the read line output from the read circuit can be increased, the S / N ratio can be greatly improved.

  In addition, the configuration of the inverting amplifier in the present invention is a two-stage configuration of a source grounded inverting amplification unit and a source follower type buffer, and the third switching means is provided between the input and output of the source grounded inverting amplification unit, Further, it is preferable that a connection point on the output terminal side of the inverting amplifier of the second switching means is connected to the output terminal of the source follower type buffer. Since such an inverting amplifier can realize high-speed reading with a small bias current by the source follower type buffer, it has a great effect on reduction of power consumption and occupation area.

  According to the present invention, it is possible to realize a small current consumption and a small area while using a high S / N readout circuit having a column amplifier.

[First Embodiment]
FIG. 1 shows a configuration in which the present invention is applied to a clamp circuit type noise elimination circuit. In the conventional readout circuit in which an amplifier is provided for each column, amplifiers are provided for all columns, but in FIG. 3, two capacitors C1i (coupling capacitance) connected in series to n column signal lines. , C2i (holding capacitor) (i = 1 to n), and a switch SW1i configured to connect and disconnect a connection point between the capacitors Cli and C2i with respect to the reference potential Vref, and connected to one end of the capacitor C2i. Are provided for each column signal line, and clamp circuits CL-1 to CL-n each comprising a switch (first switching means) SW2i (i = 1 to n) configured to be intermittent can be provided. On the other hand, one inverting amplifier A1 having a switch (third switching means) SW3 between the input and output is provided, and the other ends of the plurality of capacitors C2i (i = 1 to n) are shared by the input of the inverting amplifier A1. N is connected between the one end of the capacitor C2i (i = 1 to n) and the output terminal of the inverting amplifier A1. Switch (second switching means) SW4i (i = 1~n) is in the configuration provided in parallel.

  Here, since the switches SW2i (i = 1 to n) and the switch SW3 in FIG. 1 operate at different timings, the control signals are ΦSH and ΦSHR, respectively. Since the switch SW4i (i = 1 to n) is driven at a different timing for each column in accordance with the read timing, each control signal is set to ΦROi (i = 1 to n).

  The operation in such a configuration will be described with reference to the timing chart of FIG. The timing is roughly divided into four periods. In the period T1, the integrated pixel signal is read, the pixel is reset in the period T2, and the pixel signal is read immediately after the reset in the period T3. The noise removal operation is executed. The signal from which noise has been removed is read out in period T4. In the period T1 to T3, because the input / output terminal of the inverting amplifier is short-circuited due to ΦSHR = 'H', the terminal on the inverting amplifier input side connected in common to the capacitor C2i of the clamp circuits CL-1 to CL-n Since the side voltage is a constant value, each of the clamp circuits CL-1 to CL-n performs the same operation as the clamp circuit of FIG. 9, and the midpoint terminal voltage Vci of the capacitor C2i is the signal voltage of the period T1 in each column. The difference voltage between V1i and the signal voltage V2i in the period T3 is held in the same manner as in the equation (5).

  The voltages Vc1 to Vcn held in the capacitors C2i (i = 1 to n) of the clamp circuits CL-1 to CL-n in the operation of the periods T1 to T3 are set to the switch SW4i to “H”, and the input / output of the inverting amplifier By connecting in between, the voltage Vci can be read from the output of the inverting amplifier. Therefore, in a state in which the horizontal selection switch 107 is turned on in the period T4, the voltage Vc1 is output as ΦSHR = 'L', ΦRO1 = 'H', and then the voltage Vc2 is set as ΦRO1 = 'L', ΦRO2 = 'H'. Are repeated, the voltages Vc1 to Vcn can be read from the video line 108 as inverting amplifier outputs. In this configuration, an example in which the readout circuit of the present invention is applied to a noise removal circuit using a clamp circuit has been shown. However, when the fixed pattern noise of a pixel is removed by an external memory or the like, the capacitor C1i (i = 1 to 1) is used. n) and the switch SW1i (i = 1 to n) are removed, and the signal voltage V1 during the period T1 in the timing chart of FIG. 3 is directly sampled into the capacitor C2i (i = 1 to n) and the signal is read out. It is good also as a structure.

  In a configuration in which each column signal line does not have an inverting amplifier and a plurality of column signal lines share one inverting amplifier as shown in FIG. 1, the driving method shown in FIG. 3 is performed. After the signal voltage from which the fixed pattern noise of the pixel is removed is held in the capacitor C2i (i = 1 to n), the output corresponding to the signal voltage of the capacitor C2i can be sequentially read out from the video line via the inverting amplifier.

In the configuration shown in FIG. 1, since only one inverting amplifier is required per n columns, the current consumption of the entire inverting amplifier can be reduced by reducing the number of inverting amplifiers. Further, as the number of inverting amplifiers is reduced to 1 / n, the total number of horizontal selection switches 107 connecting the video line 108 and the inverting amplifier is also reduced to 1 / n compared to the case where each column is provided with an amplifier. Since the parasitic capacitance of the video line that becomes the load capacitance during the read operation of the inverting amplifier is also greatly reduced, the bias current of the inverting amplifier alone can be made very small. In this way, the number of inverting amplifiers can be reduced to 1 / n, and the single bias current can also be reduced to 1 / n at the maximum. It can be reduced to 1 / n ² at the maximum. In addition, since the number of inverting amplifiers is reduced, the area occupied by the entire inverting amplifier is reduced, and since the capacitance driven at the time of reading is small and the bias current can be reduced, the transistor size of the inverting amplifier alone can be reduced, and not only the current consumption The chip area can also be reduced. Therefore, it is possible to realize a readout circuit with a small current consumption and a small area while using the amplification output readout method capable of readout with high S / N, which is an object of the present invention.

  FIG. 2 shows an example of an inverting amplifier used in the present invention. In FIG. 2, the inverting amplifier is composed of vertically stacked PMOS transistors M1 and M2 and NMOS transistors M3 and M4. The gate of the inverting amplifier is an NMOS transistor M4 which operates as a common source amplification transistor at the input terminal Vin of the inverting amplifier. In order to increase the open-loop gain, the gate is connected to the bias voltage Vb3 in order to increase the open-loop gain to the CMOS-type inverting amplifier composed of the PMOS transistor M1 that is connected to the bias voltage Vb1 and whose source is connected to the power supply. The NMOS transistor M3 connected to is connected to the drain of the NMOS transistor M4, and M2 whose gate is connected to the bias voltage Vb2 is cascode-connected to the drain of the PMOS transistor M1. Even with such an inverting amplifier having a simple configuration, a high open loop gain can be obtained by cascode connection, so that a readout (noise removal) circuit with sufficient characteristics can be realized.

[Second Embodiment]
In the first embodiment, the signal voltage obtained by removing the pixel offset voltage from the pixel signal line to the sampling capacitor (holding capacitor) C2i (i = 1 to n) of each column via the coupling capacitor C1i (i = 1 to n). FIG. 4 shows a configuration in which pixel signals are directly sampled and read out as a second embodiment. In this configuration, instead of removing the capacitor C1i (i = 1 to n) and the switch SW1i (i = 1 to n) in FIG. 1, two sampling capacitors Cai and Cbi (i = 1 to n) are provided on one signal line. Provided is a configuration in which the integrated pixel signal voltage and the pixel signal voltage immediately after reset are sampled separately, and the difference voltage is obtained when the difference is read on the video line while reading them on the two video lines 108a and 108b. Is. In FIG. 4, as an example, a plurality of readout circuits that process n signal outputs with one inverting amplifier (processing Vs1 to Vsn in the drawing and Vs (n + 1) to Vs (2n) in the drawing are illustrated. What is processed) is shown.

  In FIG. 4, as in FIG. 1, one inverting amplifier A1a is provided for a sampling circuit composed of n sampling switches SW2ai (i = 1 to n) and Cai (i = 1 to n), and one end of the capacitor is provided. Are connected to the inverting amplifier input in common and the other end connected to the sampling switch SW2ai (i = 1 to n) is provided with a read switch SW4ai (i = 1 to n) connected to the inverting amplifier output at the time of reading. ing. As in the embodiment of FIG. 1, a switch SW3a controlled by ΦSHR is provided between the input and output of the inverting amplifier. By providing two systems corresponding to the inverting amplifiers A1a and A1b with the readout circuit system of n capacitors and one inverting amplifier configured as described above, it is possible to sample two signal voltages in each column.

  Next, the operation of the circuit of FIG. 4 will be described using the timing chart of FIG. Similarly to the first embodiment, the timing is roughly divided into four periods. In the period T1, the integrated pixel signal is read, in the period T2, the pixel is reset, and in the period T3, the pixel signal is read immediately after the reset. Is called. In the first embodiment, noise is removed by the operation during the period T1 to T3. Here, the switch SW2ai (i = 1 to n) are turned on to directly sample the capacitor Cai (i = 1 to n), and the sampling signal ΦSHb is set to “Hi” in the period T3, so that the switch SW2bi (i = 1 to n) Is conducted to the capacitor Cbi (i = 1 to n). The voltages held in the two capacitors are read out in parallel through the two video lines 108a and 108b in the period T4. Then, by taking the difference from the two read signals, noise due to the offset voltage of the pixel is removed. In the period T4, the horizontal selection switches 107a and 107b are simultaneously turned on and ΦRO1 = 'H' in the state where ΦSHR = 'L', and the signal voltages Va1 and Vb1 in the first column are read simultaneously, and then ΦRO1 = “L”, ΦRO2 = “H” and the signal voltage voltages Va2 and Vb2 in the second column are output simultaneously, and the difference voltage between the two read signals is obtained by repeating the operation such as It is possible to obtain a signal from which noise is removed for the number of columns.

  In the configuration shown in FIG. 4, since only one inverting amplifier per n columns is required for one video line, the number of inverting amplifiers can be reduced, and current consumption in the entire inverting amplifier can be reduced. Further, as the number of inverting amplifiers is reduced to 1 / n, the total number of horizontal selection switches 107a and 107b connecting the video lines 108a and 108b and the inverting amplifiers A1a and A1b is also compared with the case where the amplifiers are provided in all columns. Therefore, since the parasitic capacitance of the video line, which is a load capacitance during the read operation of the inverting amplifier, is significantly reduced, the bias current of the inverting amplifier alone can be made extremely small. In addition, since the number of inverting amplifiers is reduced, the area occupied by the entire inverting amplifier is reduced, and since the capacitance driven at the time of reading is small and the bias current can be reduced, the transistor size of the inverting amplifier alone can be reduced, and not only the current consumption The chip area can also be reduced. Therefore, it is possible to realize a readout circuit with a small current consumption and a small area while using the amplification output readout method capable of readout with high S / N, which is an object of the present invention.

  The configuration shown in FIG. 4 requires twice as many inverting amplifiers as the configuration shown in FIG. 1, so the configuration shown in FIG. 1 is more advantageous in terms of current consumption. As shown in (5), the differential voltage is reduced to C1 / (C1 + C2), whereas in the circuit format of FIG. 4, the signal voltage is directly sampled without being reduced, and video Since the signal voltage on the line can be increased, the format of FIG. 4 is superior from the viewpoint of S / N.

  In the above embodiment, the pixel amplification type CMOS image sensor shown in FIG. 8 has been described. However, the present invention can be applied to various pixel amplification type image sensors. For example, the present invention can be applied to a pixel amplifier sharing type image sensor in which one pixel amplifier is provided in common to four photodiodes, or an image sensor using an amplifier other than a CMOS. Also, even if it is used for a sensor that reads by providing a column amplifier on the column signal line, this noise elimination circuit is provided after the amplifier to obtain the difference between the two signal components at the time of resetting and reading the column amplifier. Thus, noise such as offset voltage of the column amplifier can be removed. Even if the amplifier is not provided in units of pixels or columns, it is also effective as a readout circuit used for a noise removal circuit in a solid-state imaging device configured to read out by providing amplifiers in parallel in units of blocks.

[Third Embodiment]
As a specific circuit configuration of the inverting amplifier in the embodiments so far, it is possible to use the one-stage inverting amplifier shown in FIG. 2, but inversion that can reduce current consumption in high-speed reading. The configuration of the amplifier is shown in FIG. 6 as a third embodiment. FIG. 6 is a circuit diagram in which the inverting amplifier according to the third embodiment is applied to the embodiment shown in FIG. In FIG. 6, the configuration other than the inverting amplifier is exactly the same as that shown in FIG. 1, and only the configuration of the inverting amplifier is embodied.

  The inverting amplifier shown in FIG. 6 is connected to the output of a cascode-connected source-grounded inverting amplifier composed of vertically stacked PMOS transistors M1, M2 and NMOS transistors M3, M4 having the same circuit configuration as the inverting amplifier shown in FIG. It has a two-stage configuration in which a source follower-type buffer composed of transistors M5 and M6 is connected. This source follower type buffer includes an NMOS transistor M5 having a drain connected to a power supply and a gate serving as an input terminal, and an NMOS transistor M6 connected to the source of the NMOS transistor M6 operating as a constant current source load with a bias voltage Vb4 applied to the gate. It is configured. The feature of this source follower circuit is that the voltage gain is about 1, but the output impedance is low and the driving capability for a capacitive load is high even with a small bias current.

  When the video line capacitance is directly driven using the one-stage source-grounded inverting amplifier shown in FIG. 2, a large bias current is required to widen the band in order to perform reading quickly. This is necessary not only for the time but also for the noise removal operation (periods T1 to T3 in FIG. 3). On the other hand, in the case of using the two-stage configuration with the cascode configuration of the cascode configuration of FIG. 6 and the source follower configuration output buffer, since the load of the first-stage inverting amplifier is only the gate capacitance of the source follower, a small bias current However, high-speed reading is possible. In addition, the source follower circuit in the subsequent stage can perform high-speed reading even with a small bias current, and this bias current is unnecessary during the noise removal operation, and it only needs to flow only when reading a signal to the video line. High-speed reading can be performed with current.

  The switch SW3 between the input and output of the inverting amplifier of FIG. 1 is shown as an NMOS transistor M7 between the input and output of the first stage cascode configuration source grounded inverting amplifier circuit in the two-stage inverting amplifier of FIG. There is no operational problem even if one end of this switch is connected to the output terminal of the source follower circuit instead of the output terminal of the common source inverting amplifier. However, by providing the switch M7 between the input and output of the first-stage source grounded inverting amplifier circuit in this way, there is an advantage that it is not necessary to pass a bias current through the source follower circuit during the noise elimination operation.

  In the configuration of FIG. 6, when the switching NMOS transistor M7 is provided between the input terminal of the first stage and the source follower output terminal of the subsequent stage, M7 is turned on unless a bias current is supplied to the source follower circuit during the noise elimination operation. Although the correct threshold voltage of the inverting amplifier is not output, if M7 is provided between the input and output of the first-stage grounded source inverting amplifier circuit, the correct threshold voltage of the inverting amplifier is not required even if a bias current is passed through the source follower circuit. Is output. Note that the threshold voltage value in these operations is almost the same voltage value even when the source-follower circuit is connected or when the source-follower circuit is connected alone if the open-loop gain of the first-stage source-grounded inverting amplifier circuit is large. Regardless of which switch transistor M7 is provided, the noise elimination operation is not affected. Therefore, it can be said that the configuration in which a switch is provided between the input and output of the first-stage common-source inverting amplifier shown in FIG. 6 is more advantageous in reducing current consumption. Therefore, by using the configuration of the inverting amplifier shown in the third embodiment, it is possible to further promote the realization of a small current consumption, which is one of the objects of the present invention.

  As described above, in each of the above embodiments, the sampling capacitor (holding capacitor), the sampling switch (first switching unit), and the readout switch (second switching unit) are provided for each column, and one column is provided for each n column. Two inverting amplifiers are provided, and the other ends of the sampling capacitors are commonly connected to the inverting amplifier inputs in units of n columns. With such a configuration, the sampling switch is turned on in parallel during signal sampling and the signal is held in each capacitor, and the readout switch is sequentially connected during readout to obtain a serialized readout signal. As a result, the number of inverting amplifiers can be reduced to 1 / n, and the parasitic capacitance of the video line (readout line) can be reduced, so that power consumption and area can be reduced.

It is a schematic block diagram which shows the read-out circuit of 1st Embodiment of this invention. 2 is a configuration example of an inverting amplifier in FIG. 1. FIG. 6 is a timing chart for explaining the operation of the first embodiment. It is a schematic block diagram which shows the read-out circuit of 2nd Embodiment of this invention. It is a timing diagram for demonstrating operation | movement of 2nd Embodiment of this invention. 4 is a noise removal circuit of a third embodiment specifically showing the inverting amplifier of FIG. 1. It is the circuit diagram which showed the structure of the solid-state imaging device in this invention. It is the circuit diagram which showed an example of the pixel of the solid-state imaging device of FIG. It is a circuit diagram which shows an example of the conventional reading (noise removal) circuit. FIG. 10 is a timing chart for explaining the operation of FIG. 9. It is a circuit diagram which shows the other example of the conventional noise removal circuit.

Explanation of symbols

C1 1st capacity
C2 Second capacity
SW1 and SW1i Clamp switch
SW2 and SW2i sampling switch (first switching means)
SW3 Reset switch (third switching means)
SW4 and SW4i read switch (second switching means)
A1 inverting amplifier
Vs Input signal terminal and input signal voltage
Vo Output signal terminal and output signal voltage
Vb1, Vb2, Vb3, Vb4 constant voltage source and its voltage value
M1, M6 Load transistor
M2, M3 Cascode transistor
M4 Common source transistor
M5 source follower transistor
M7 Reset transistor

Claims (3)

In a solid-state imaging device having a plurality of pixels arranged in an array and performing a pixel signal readout operation in parallel via a pixel amplifier,
A read circuit having a plurality of holding capacitors respectively holding the signal outputs of the plurality of pixel amplifiers, and a common inverting amplifier for sequentially reading out the signals held in the plurality of holding capacitors;
The readout circuit includes first switching means (SW21 to SW2n) configured to be able to intermittently connect between one end of the storage capacitor and the signal output, and one end of the storage capacitor and an output of the inverting amplifier. Second switching means (SW41 to SW4n) configured to be able to be intermittently connected, and third switching means (SW3) configured to be capable of being intermittently connected between the input and output of the inverting amplifier are provided,
The other end of the plurality of holding capacitors is commonly connected to an input of the inverting amplifier.   A first readout circuit and a second readout circuit each having the storage capacitor, the first switching unit, the second switching unit, the third switching unit, and the inverting amplifier for each signal output The output corresponding to the signal output of the pixel at different time points can be read in parallel by the first readout circuit and the second readout circuit. The solid-state imaging device described in 1. The inverting amplifier has a two-stage configuration of a source grounded inverting amplifier and a source follower type buffer, the third switching means is provided between the input and output of the source grounded inverting amplifier, and the second 3. The solid-state imaging device according to claim 1, wherein a connection point of the switching means on the output terminal side of the inverting amplifier is connected to an output terminal of the source follower type buffer.

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