CN106331434B - Image processing apparatus and method - Google Patents
Image processing apparatus and method Download PDFInfo
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- CN106331434B CN106331434B CN201610802701.6A CN201610802701A CN106331434B CN 106331434 B CN106331434 B CN 106331434B CN 201610802701 A CN201610802701 A CN 201610802701A CN 106331434 B CN106331434 B CN 106331434B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/741—Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
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Abstract
The invention belongs to technical field of image processing, provide a kind of image processing apparatus and method, the image processing apparatus successively exports the first optimization photoreceptor signal by the big pixel photoreceptor signal that input module exports image after the first analog storage module carries out storage and the first amplification module amplifies processing, the small pixel photoreceptor signal of the image of input module output simultaneously successively carries out storage by the second analog storage module and the second amplification module amplifies the second optimization of output photoreceptor signal after handling, then synthesis module synthesizes the first optimization photoreceptor signal and the second optimization photoreceptor signal, and wide dynamic images signal is exported by output module.Thus WDR synthesis is carried out to size pixel photoreceptor signal using binary channels, not the bottleneck of the shooting speed of frame rate reduction processing;Same image is handled, there is no delay, solve the problems, such as existing image composing technique reduce there is delay, frame per second and had when shooting mobile target smear cause it is blurred image.
Description
Technical field
The invention belongs to technical field of image processing, more particularly to a kind of image processing apparatus and method.
Background technique
In recent years, the wide dynamic of existing single-chip (hereinafter referred to as WDR, Wide Dynamic Range) technology generallys use
DSP (Digital Signal Processing, Digital Signal Processing) synthesizes the multiple image of different exposure time,
This sequential frame image for synthesis usually has a biggish delay, therefore has smear when shooting mobile target and lead to figure
As fuzzy problem.Secondly, final output frame rate can be reduced to the half or less of original frame per second by the WDR image of synthesis,
In the target that shooting fast moves, frame per second can be a bottleneck.
Therefore, existing image composing technique is reduced and is had when shooting mobile target there is delay, frame per second and drags
Shadow leads to blurred image problem.
Summary of the invention
The purpose of the present invention is to provide a kind of image processing apparatus and methods, it is intended to solve existing image composing technique
Reducing there is delay, frame per second and have smear when shooting mobile target leads to blurred image problem.
The present invention provides a kind of image processing apparatus, described image processing unit includes:
Input module, the first analog storage module, the second analog storage module, the first amplification module, the second amplification module,
Synthesis module and output module;
The output end of the input module connects the first receiving end and second of first analog storage module respectively simultaneously
Receiving end and the first receiving end and the second receiving end of the second analog storage module, the first of first analog storage module
Output end and second output terminal connect the first input end and the second input terminal of first amplification module, second simulation respectively
The first output end and second output terminal of memory module connect first input end and the second input of second amplification module respectively
End, the output of first amplification module terminate the first input end of the synthesis module, the output of second amplification module
The second input terminal of the synthesis module is terminated, the output of the synthesis module terminates the output module;
The big pixel photoreceptor signal of the input module output image is successively carried out by first analog storage module
Storage and first amplification module amplify output the first optimization photoreceptor signal after processing;
The small pixel photoreceptor signal of the input module output image is successively carried out by second analog storage module
Storage and second amplification module amplify output the second optimization photoreceptor signal after processing;
The synthesis module synthesizes the first optimization photoreceptor signal and the second optimization photoreceptor signal, and leads to
Cross the output module output wide dynamic images signal.
The present invention also provides a kind of image processing method based on image processing apparatus described above, at described image
Reason method the following steps are included:
A. the input module is used to export the big pixel photoreceptor signal and small pixel photoreceptor signal of image;
B. first analog storage module is for storing the big pixel photoreceptor signal, while second mould
Analog storage module is for storing the small pixel photoreceptor signal;
C. first amplification module is used to amplify the big pixel photoreceptor signal the first optimization of output after processing
Photoreceptor signal, while second amplification module is excellent for output second after amplifying processing to the small pixel photoreceptor signal
Allelopathic optical signal;
D. the synthesis module is used to close the first optimization photoreceptor signal and the second optimization photoreceptor signal
At, and wide dynamic images signal is exported by the output module.
In conclusion the image processing apparatus passes through input mould the present invention provides a kind of image processing apparatus and method
The big pixel photoreceptor signal of block output image successively passes through the first analog storage module and carries out storage and the progress of the first amplification module
The first optimization of output photoreceptor signal after enhanced processing, while the small pixel photoreceptor signal of input module output image successively passes through the
Two analog storage modules carry out storage and the second amplification module amplifies output the second optimization photoreceptor signal after processing, then close
The first optimization photoreceptor signal and the second optimization photoreceptor signal are synthesized at module, and exported by output module
Wide dynamic images signal.Thus WDR synthesis is carried out to big pixel photoreceptor signal and small pixel photoreceptor signal using binary channels, do not had
The bottleneck of the shooting speed of frame rate reduction processing;Secondly, handling same image, there is no delay phenomenons, solve existing
Image composing technique reduce there is delay, frame per second and have smear when shooting mobile target and lead to blurred image ask
Topic.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of image processing apparatus provided in an embodiment of the present invention.
Fig. 2 is the exemplary circuit figure of image processing apparatus provided in an embodiment of the present invention.
Fig. 3 be another embodiment of the present invention provides image processing method step flow chart.
Specific embodiment
In order to which technical problems, technical solutions and advantageous effects to be solved by the present invention are more clearly understood, below in conjunction with
Accompanying drawings and embodiments, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
Image processing apparatus provided in an embodiment of the present invention and method are the senses using binary channels parallel processing size pixel
Optical signal, the output bus of common column pixel, on serial samples photoreceptor signal to corresponding sampling capacitance, then parallel to sampling electricity
Signal in appearance carries out operation and amplification, by the weighting processing circuit of rear class, realizes the analog synthesis of wide dynamic images signal,
And the not no bottleneck of frame rate reduction processing.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments.
Fig. 1 shows the structure of image processing apparatus provided in an embodiment of the present invention, for ease of description, illustrate only with
The relevant part of the embodiment of the present invention, details are as follows:
The image processing apparatus includes input module 101, the first analog storage module 102, the second analog storage module
103, the first amplification module 104, the second amplification module 105, synthesis module 106 and output module 107.
The output end of input module 101 connects the first receiving end of the first analog storage module 102 and second simultaneously respectively and connects
The first receiving end and the second receiving end of receiving end and the second analog storage module 103, the first of the first analog storage module 102
Output end and second output terminal connect the first input end and the second input terminal of the first amplification module 104, the second analog storage respectively
The first output end and second output terminal of module 103 connect the first input end and the second input terminal of the second amplification module 105 respectively,
The output end of first amplification module 104 is bonded into the first input end of module 106, the output end engagement of the second amplification module 105
At the second input terminal of module 106, the output of synthesis module 106 terminates output module 107.
The big pixel photoreceptor signal that input module 101 exports image successively passes through the first analog storage module 102 and is deposited
Storage and the first amplification module 104 amplify output the first optimization photoreceptor signal after processing;
The small pixel photoreceptor signal that input module 101 exports image successively passes through the second analog storage module 103 and is deposited
Storage and the second amplification module 105 amplify output the second optimization photoreceptor signal after processing;
Synthesis module 106 synthesizes the first optimization photoreceptor signal and the second optimization photoreceptor signal, and passes through output mould
Block 107 exports wide dynamic images signal.
As an embodiment of the present invention, the input module 101 is to big pixel photoreceptor signal and small pixel photoreceptor signal point
It after indescribably taking, is exported, will be deposited on serial samples photoreceptor signal to corresponding sampling capacitance using twin-channel form
Storage, then operation and amplification are carried out to the signal on sampling capacitance parallel, then by operational amplifier to the big photosensitive letter of pixel
Number and small pixel photoreceptor signal be weighted processing and synthesize, export wide dynamic images signal.The big pixel photoreceptor signal
Pixel value be greater than 10,000,000 pixels, the pixel value of the small pixel photoreceptor signal is less than 10,000,000 pixels.
Fig. 2 has gone out the exemplary circuit of image processing apparatus provided in an embodiment of the present invention, for ease of description, illustrates only
Part related to the embodiment of the present invention, details are as follows:
As an embodiment of the present invention, which includes:
First switch tube M1, second switch M2, third switching tube M3, the 4th switching tube M4, the 5th switching tube M5, big picture
Plain photoelectric tube PL, small pixel photoelectric tube PS, reset capacitance CFD;
The input of first switch tube M1 terminates main control signal RX, the output end of first switch tube M1 and the 4th switching tube M4
Output end connection, the output of the control terminal of first switch tube M1 and the output end of second switch M2 and third switching tube M3
End connection, the control terminal of the charge output termination second switch M2 of big pixel photoelectric tube PL, the input terminal of second switch M2
Connect first control signal TXL, the control terminal of the charge output termination third switching tube M3 of small pixel photoelectric tube PS, third switching tube
The input of M3 terminates second control signal TXS, the first end of reset capacitance CFD and the control terminal and the 4th of first switch tube M1
The input terminal of switching tube M4 connects, and the second end ground connection of reset capacitance CFD, the control of the 4th switching tube M4 terminates the 5th switching tube
The control terminal of M5, the input of the 5th switching tube M5 terminate reset signal RS, and the output end of the 5th switching tube M5 is input module 101
Output end.Reset capacitance CFD can be integrated capacitor, be also possible to the parasitic capacitance as caused by ghost effect.Make
For one embodiment of the invention, first switch tube M1, second switch M2, third switching tube M3, the 4th switching tube M4, the 5th are opened
Closing pipe M5 can also be replaced using triode or field-effect tube, as long as can play the role of and the embodiment of the present invention.
As an embodiment of the present invention, which includes:
First switch SHRL, second switch SHSL, the first sampling capacitance CLr and the first storage capacitance CLs;
The first end of first switch SHRL is the first receiving end of the first analog storage module 102, first switch SHRL's
Second end is connect with the first end of the first sampling capacitance CLr and the first output end as the first analog storage module 102, and first
The second end of sampling capacitance CLr is grounded, and the first end of second switch SHSL is the second reception of the first analog storage module 102
End, the second end of second switch SHSL connect with the first end of the first storage capacitance CLs and as the first analog storage modules 102
Second output terminal, the first storage capacitance CLs second end ground connection.
As an embodiment of the present invention, which includes:
Third switch SHRS, the 4th switch SHSS, the second sampling capacitance CSr and the second storage capacitance CSs;
The first end of third switch SHRS is the first receiving end of the second analog storage module 103, third switch SHRS's
Second end is connect with the first end of the second sampling capacitance CSr and the first output end as the second analog storage module 103, and second
The second end of sampling capacitance CSr is grounded, and the first end of the 4th switch SHSS is the second reception of the second analog storage module 103
End, the second end of the 4th switch SHSS connect with the first end of the second storage capacitance CSs and as the second analog storage modules 103
Second output terminal, the second storage capacitance CSs second end ground connection.
As an embodiment of the present invention, which includes the first operational amplifier COMP1, the first operation
Normal phase input end, inverting input terminal and the output end of amplifier COMP1 is respectively the first input of the first amplification module 104
End, the second input terminal and output end.
As an embodiment of the present invention, which includes second operational amplifier COMP2, the second operation
Normal phase input end, inverting input terminal and the output end of amplifier COMP2 is respectively the first input of the second amplification module 105
End, the second input terminal and output end.
As an embodiment of the present invention, which includes third operational amplifier COMP3, third operation amplifier
Normal phase input end, inverting input terminal and the output end of device COMP3 be respectively the first input end of synthesis module 106, second defeated
Enter end and output end.
The step process that Fig. 3 shows image processing method provided in an embodiment of the present invention is only shown for ease of description
Part related to the embodiment of the present invention, details are as follows:
A kind of image processing method based on image processing apparatus described above, which is characterized in that described image processing
Method the following steps are included:
S101. the input module is used to export the big pixel photoreceptor signal and small pixel photoreceptor signal of image;
S102. first analog storage module is for storing the big pixel photoreceptor signal, while described the
Two analog storage modules are for storing the small pixel photoreceptor signal;
S103. output first is excellent after first amplification module is used to amplify the big pixel photoreceptor signal processing
Allelopathic optical signal, while second amplification module is used to export second after amplifying processing to the small pixel photoreceptor signal
Optimize photoreceptor signal;
S104. the synthesis module is used to carry out the first optimization photoreceptor signal and the second optimization photoreceptor signal
Synthesis, and wide dynamic images signal is exported by the output module.
It is illustrated below in conjunction with working principle of the Fig. 1 and Fig. 2 to above-mentioned image processing apparatus and method:
Firstly, first switch tube M1 is opened, to reset capacitance when pixel reading circuit works by main control signal RX
CFD is resetted, this resetting voltage VRL by the 4th switching tube M4, the 5th switching tube M5 and first switch SHRL sample to
First sampling capacitance CLr, the second switch M2 of big pixel photoelectric tube PL connection are opened by first control signal TXL, this signal
Reset capacitance CFD is reached, the voltage VSL of this signal passes through the 4th switching tube M4, the 5th switching tube M5 and second switch SHSL
It stores to the first storage capacitance CLs;
Likewise, controlling first switch tube M1 to multiple by main control signal RX when carrying out signal-obtaining to small pixel PS
Position capacitor CFD is resetted, this resetting voltage VRS is adopted by the 4th switching tube M4, the 5th switching tube M5 and third switch SHRS
Sample is opened by second control signal TXS to the second sampling capacitance CSr, the switching tube M3 of small pixel photoelectric tube PS connection, this signal
Reset capacitance CFD is reached, the voltage VSS of this signal passes through the 4th switching tube M4, the 5th switching tube M5 and the 4th switch SHSS
It stores to the second storage capacitance CSs.
Particularly, VRL-VSL is known as big pixel photoreceptor signal, VRS-VSS is known as small pixel photoreceptor signal, is then led to
It crosses WDR synthesizer and synthesis is weighted to big pixel photoreceptor signal and small pixel photoreceptor signal, export WDR picture element signal Vout.
Wherein weighting coefficient is by the pro rate of big pixel photoreceptor signal and small pixel photoreceptor signal, such as its weight coefficient can be set to
0.5, i.e. WDR picture element signal Vout=0.5* (VRL-VSL)+0.5* (VRS-VSS).
In conclusion the image processing apparatus passes through the embodiment of the invention provides a kind of image processing apparatus and method
The big pixel photoreceptor signal of input module output image successively passes through the first analog storage module and carries out storage and the first amplification mould
Block amplifies output the first optimization photoreceptor signal after processing, while the small pixel photoreceptor signal of input module output image is successively
The second optimization of output photoreceptor signal after the second analog storage module carries out storage and the second amplification module amplifies processing,
Then synthesis module synthesizes the first optimization photoreceptor signal and the second optimization photoreceptor signal, and passes through output mould
Block exports wide dynamic images signal.Thus WDR conjunction is carried out to big pixel photoreceptor signal and small pixel photoreceptor signal using binary channels
At the not no bottleneck of the shooting speed of frame rate reduction processing;Secondly, handling same image, there is no delay phenomenons, solve
Existing image composing technique, which reduces there is delay, frame per second and has a smear when shooting mobile target, leads to image mould
The problem of paste.
Those of ordinary skill in the art will appreciate that: the step of realizing above method embodiment or part steps can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, which exists
When execution, step including the steps of the foregoing method embodiments is executed, and storage medium above-mentioned includes: ROM, RAM, magnetic or disk
Etc. the various media that can store program code.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations;Although referring to aforementioned reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features;And these are modified
Or replacement, the spirit and model of each embodiment technical solution of the embodiment of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (7)
1. a kind of image processing apparatus, which is characterized in that described image processing unit includes:
Input module, the first analog storage module, the second analog storage module, the first amplification module, the second amplification module, synthesis
Module and output module;
The output end of the input module connects the first receiving end of first analog storage module and second respectively simultaneously and receives
End and the first receiving end and the second receiving end of second analog storage module, the first of first analog storage module
Output end and second output terminal connect the first input end and the second input terminal of first amplification module, second simulation respectively
The first output end and second output terminal of memory module connect first input end and the second input of second amplification module respectively
End, the output of first amplification module terminate the first input end of the synthesis module, the output of second amplification module
The second input terminal of the synthesis module is terminated, the output of the synthesis module terminates the output module;
The big pixel photoreceptor signal of the input module output image is successively stored by first analog storage module
Output first optimizes photoreceptor signal after amplifying processing with first amplification module;
The small pixel photoreceptor signal of the input module output image is successively stored by second analog storage module
Output second optimizes photoreceptor signal after amplifying processing with second amplification module;
The synthesis module synthesizes the first optimization photoreceptor signal and the second optimization photoreceptor signal, and passes through institute
State output module output wide dynamic images signal;
The synthesis module includes third operational amplifier COMP3,
Normal phase input end, inverting input terminal and the output end of the third operational amplifier COMP3 is respectively the synthesis mould
The first input end of block, the second input terminal and output end;
Wherein, the first optimization photoreceptor signal and the second optimization photoreceptor signal pass through the third operational amplifier
COMP3 is weighted synthesis, and weighting coefficient optimizes the ratio of photoreceptor signal according to the first optimization photoreceptor signal and described second
Example distribution is set.
2. image processing apparatus as described in claim 1, which is characterized in that the input module includes:
First switch tube M1, second switch M2, third switching tube M3, the 4th switching tube M4, the 5th switching tube M5, big pixel light
Fulgurite PL, small pixel photoelectric tube PS, reset capacitance CFD;
The input of the first switch tube M1 terminates main control signal RX, the output end of the first switch tube M1 and the described 4th
The output end of switching tube M4 connects, the output end and institute of the control terminal of the first switch tube M1 and the second switch M2
The output end connection of third switching tube M3 is stated, the charge output of big pixel photoelectric tube PL described in photoelectric tube terminates the second switch
The input of the control terminal of pipe M2, the second switch M2 terminates first control signal TXL, the electricity of the small pixel photoelectric tube PS
Lotus output terminates the control terminal of the third switching tube M3, and the input of the third switching tube M3 terminates second control signal TXS,
The first end of the reset capacitance CFD and the control terminal of the first switch tube M1 and the input terminal of the 4th switching tube M4
Connection, the second end ground connection of the reset capacitance CFD, the control of the 4th switching tube M4 terminate the 5th switching tube M5's
Control terminal, the input of the 5th switching tube M5 terminate reset signal RS, and the output end of the 5th switching tube M5 is described defeated
Enter the output end of module.
3. image processing apparatus as described in claim 1, which is characterized in that first analog storage module includes:
First switch SHRL, second switch SHSL, the first sampling capacitance CLr and the first storage capacitance CLs;
The first end of the first switch SHRL is the first receiving end of first analog storage module, the first switch
The second end of SHRL is connect and first as first analog storage module with the first end of the first sampling capacitance CLr
Output end, the second end ground connection of the first sampling capacitance CLr, the first end of the second switch SHSL are first simulation
The first end of second receiving end of memory module, the second end of the second switch SHSL and the first storage capacitance CLs connect
It connects and the second output terminal as first analog storage module, the second end of the first storage capacitance CLs is grounded.
4. image processing apparatus as described in claim 1, which is characterized in that second analog storage module includes:
Third switch SHRS, the 4th switch SHSS, the second sampling capacitance CSr and the second storage capacitance CSs;
The first end of the third switch SHRS is the first receiving end of second analog storage module, the third switch
The second end of SHRS is connect and first as second analog storage module with the first end of the second sampling capacitance CSr
Output end, the second end ground connection of the second sampling capacitance CSr, the first end of the 4th switch SHSS are second simulation
The first end of second receiving end of memory module, the second end of the 4th switch SHSS and the second storage capacitance CSs connect
It connects and the second output terminal as second analog storage module, the second end of the second storage capacitance CSs is grounded.
5. image processing apparatus as described in claim 1, which is characterized in that first amplification module includes that the first operation is put
Big device COMP1,
Normal phase input end, inverting input terminal and the output end of the first operational amplifier COMP1 is respectively described first to put
First input end, the second input terminal and the output end of big module.
6. image processing apparatus as described in claim 1, which is characterized in that second amplification module includes that the second operation is put
Big device COMP2,
Normal phase input end, inverting input terminal and the output end of the second operational amplifier COMP2 is respectively described second to put
First input end, the second input terminal and the output end of big module.
7. a kind of image processing method based on image processing apparatus described in claim 1, which is characterized in that at described image
Reason method the following steps are included:
A. the input module is used to export the big pixel photoreceptor signal and small pixel photoreceptor signal of image;
B. first analog storage module is for storing the big pixel photoreceptor signal, while second simulation is deposited
Storage module is for storing the small pixel photoreceptor signal;
C. the first optimization of output is photosensitive after first amplification module is used to amplify the big pixel photoreceptor signal processing
Signal, while second amplification module is used to amplify the small pixel photoreceptor signal output the second optimization sense after processing
Optical signal;
D. the synthesis module is used to synthesize the first optimization photoreceptor signal and the second optimization photoreceptor signal, and
Wide dynamic images signal is exported by the output module.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1514652A (en) * | 2002-12-25 | 2004-07-21 | ��ʿ��Ƭ��ʽ���� | Image synthesizing method and camera device |
CN101729796A (en) * | 2008-10-14 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
CN102158653A (en) * | 2011-05-03 | 2011-08-17 | 东华大学 | Device and method for acquiring digital image with high dynamic range in real time |
CN103259985A (en) * | 2013-05-17 | 2013-08-21 | 昆山锐芯微电子有限公司 | CMOS image sensor, pixel unit and control method of pixel unit |
CN104733480A (en) * | 2013-12-19 | 2015-06-24 | 全视科技有限公司 | Image sensor pixel for use in high dynamic range image sensor |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4081188B2 (en) * | 1998-09-16 | 2008-04-23 | オリンパス株式会社 | Image pickup apparatus using amplification type solid-state image pickup device |
JP3458741B2 (en) * | 1998-12-21 | 2003-10-20 | ソニー株式会社 | Imaging method and imaging apparatus, image processing method and image processing apparatus |
US7825966B2 (en) * | 2007-06-29 | 2010-11-02 | Omnivision Technologies, Inc. | High dynamic range sensor with blooming drain |
CN102164251B (en) * | 2011-05-25 | 2014-04-02 | 格科微电子(上海)有限公司 | Signal processing circuit and signal processing method for image sensor |
CN102547159B (en) * | 2012-02-16 | 2014-01-22 | 中国科学院上海高等研究院 | Wide-dynamic range image sensor and control method thereof |
JP6205763B2 (en) * | 2013-03-12 | 2017-10-04 | 株式会社リコー | Photoelectric conversion device and image generation device |
-
2016
- 2016-09-05 CN CN201610802701.6A patent/CN106331434B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1514652A (en) * | 2002-12-25 | 2004-07-21 | ��ʿ��Ƭ��ʽ���� | Image synthesizing method and camera device |
CN101729796A (en) * | 2008-10-14 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
CN102158653A (en) * | 2011-05-03 | 2011-08-17 | 东华大学 | Device and method for acquiring digital image with high dynamic range in real time |
CN103259985A (en) * | 2013-05-17 | 2013-08-21 | 昆山锐芯微电子有限公司 | CMOS image sensor, pixel unit and control method of pixel unit |
CN104733480A (en) * | 2013-12-19 | 2015-06-24 | 全视科技有限公司 | Image sensor pixel for use in high dynamic range image sensor |
Non-Patent Citations (1)
Title |
---|
CCD图像传感器降噪技术的研究;佟首峰等;《光学精密工程》;20000430;第8卷(第2期);说明书第3.1节,图3 |
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