CN106331434A - Image processing device and image processing method - Google Patents
Image processing device and image processing method Download PDFInfo
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- CN106331434A CN106331434A CN201610802701.6A CN201610802701A CN106331434A CN 106331434 A CN106331434 A CN 106331434A CN 201610802701 A CN201610802701 A CN 201610802701A CN 106331434 A CN106331434 A CN 106331434A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/741—Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
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Abstract
The invention belongs to the technical field of image processing, and provides an image processing device and an image processing method. According to the image processing device, large-pixel photosensitive signals of an output image of an input module sequentially pass through a first analog storage module for being stored and a first amplifying module for being amplified and processed, and then first optimized photosensitive signals are outputted; small-pixel photosensitive signals of an output image of the input module sequentially pass through a second analog storage module for being stored and a second amplifying module for being amplified and processed, and then second optimized photosensitive signals are outputted; and a synthesizing module synthesizes the first optimized photosensitive signals and the second optimized photosensitive signals, and wide-dynamic image signals are outputted through an output module. Double channels are adopted to carry out WDR (Wide Dynamic Range) synthesis on large-pixel and small-pixel photosensitive signals, and a bottleneck of a photographing speed for reduced frame processing does not exist; and when the same image is processed, no time delay exists, and the problems that time delay exists in the existing image synthesis technology, the frame rate is reduced, and the image is blurred as smear exists when a moving target is photographed can be solved.
Description
Technical field
The invention belongs to technical field of image processing, particularly relate to a kind of image processing apparatus and method.
Background technology
In recent years, existing single-chip width dynamically (hereinafter referred to as WDR, Wide Dynamic Range) technology generally uses
The multiple image of different exposure time is synthesized by DSP (Digital Signal Processing, Digital Signal Processing),
This sequential frame image for synthesis is generally of bigger time delay, therefore has smear when the mobile target of shooting and causes figure
As fuzzy problem.Secondly, final output frame rate can be reduced to the half of original frame per second or less by the WDR image of synthesis,
When the target of shooting quickly movement, frame per second can be a bottleneck.
Therefore, existing image composing technique also exists time delay, frame per second reduces and has when the mobile target of shooting and drags
Shadow causes image blurring problem.
Summary of the invention
It is an object of the invention to provide a kind of image processing apparatus and method, it is intended to solve existing image composing technique
There is time delay, frame per second reduces and has smear when the mobile target of shooting and causes image blurring problem.
The invention provides a kind of image processing apparatus, described image processing apparatus includes:
Input module, the first analog storage module, the second analog storage module, the first amplification module, the second amplification module,
Synthesis module and output module；
The outfan of described input module connects first receiving terminal and second of described first analog storage module the most respectively
Receiving terminal and the first receiving terminal of the second analog storage module and the second receiving terminal, the first of described first analog storage module
Outfan and the second outfan connect first input end and second input of described first amplification module, described second simulation respectively
First outfan of memory module and the second outfan connect first input end and second input of described second amplification module respectively
End, the output of described first amplification module terminates the first input end of described synthesis module, the output of described second amplification module
Terminating the second input of described synthesis module, the output of described synthesis module terminates described output module；
The big pixel photoreceptor signal of described input module output image sequentially passes through described first analog storage module to be carried out
Storage and described first amplification module export the first optimization photoreceptor signal after being amplified processing；
The small pixel photoreceptor signal of described input module output image sequentially passes through described second analog storage module to be carried out
Storage and described second amplification module export the second optimization photoreceptor signal after being amplified processing；
Described synthesis module optimizes photoreceptor signal by described first and described second optimization photoreceptor signal synthesizes, and leads to
Cross described output module output wide dynamic images signal.
Present invention also offers a kind of image processing method based on image processing apparatus described above, at described image
Reason method comprises the following steps:
The most described input module is for exporting big pixel photoreceptor signal and the small pixel photoreceptor signal of image；
The most described first analog storage module is used for storing described big pixel photoreceptor signal, the most described second mould
Analog storage module is for storing described small pixel photoreceptor signal；
The most described first amplification module exports the first optimization to described big pixel photoreceptor signal after being amplified processing
Photoreceptor signal, it is excellent that the most described second amplification module exports second after being amplified described small pixel photoreceptor signal processing
Allelopathic optical signal；
The most described synthesis module closes for optimizing photoreceptor signal and described second optimization photoreceptor signal by described first
Become, and export wide dynamic images signal by described output module.
In sum, the invention provides a kind of image processing apparatus and method, this image processing apparatus is by input mould
Block output image big pixel photoreceptor signal sequentially pass through the first analog storage module carry out storage and the first amplification module carry out
Exporting the first optimization photoreceptor signal after processing and amplifying, the small pixel photoreceptor signal being simultaneously entered module output image sequentially passes through the
Two analog storage modules carry out storage and the second amplification module is amplified output the second optimization photoreceptor signal after process, then close
Become module to optimize photoreceptor signal by described first and described second optimization photoreceptor signal synthesizes, and exported by output module
Wide dynamic images signal.Thus use the dual pathways that big pixel photoreceptor signal and small pixel photoreceptor signal are carried out WDR synthesis, do not have
The bottleneck of the shooting speed of frame rate reduction processing；Secondly, same image is processed, there is not time delay phenomenon, solve existing
Image composing technique there is time delay, frame per second reduces and has smear when the mobile target of shooting and causes image blurring asking
Topic.
Accompanying drawing explanation
The structural representation of the image processing apparatus that Fig. 1 provides for the embodiment of the present invention.
The exemplary circuit figure of the image processing apparatus that Fig. 2 provides for the embodiment of the present invention.
The flow chart of steps of the image processing method that Fig. 3 provides for another embodiment of the present invention.
Detailed description of the invention
In order to make the technical problem to be solved in the present invention, technical scheme and beneficial effect clearer, below in conjunction with
Drawings and Examples, are further elaborated to the present invention.Should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
The image processing apparatus that the embodiment of the present invention provides and method are to use the sense of dual pathways parallel processing size pixel
Optical signal, the output bus of common column pixel, on serial samples photoreceptor signal to corresponding sampling capacitance, more parallel to sampling electricity
Signal in appearance carries out computing and amplification, processes circuit by the weighting of rear class, it is achieved the analog synthesis of wide dynamic images signal,
And there is no the bottleneck of frame rate reduction processing.
In order to technical solutions according to the invention are described, illustrate below by specific embodiment.
Fig. 1 shows the structure of the image processing apparatus that the embodiment of the present invention provides, for convenience of description, illustrate only with
The part that the embodiment of the present invention is relevant, details are as follows:
This image processing apparatus includes input module the 101, first analog storage module the 102, second analog storage module
103, first amplification module the 104, second amplification module 105, synthesis module 106 and output module 107.
The outfan of input module 101 connects first receiving terminal and second of the first analog storage module 102 the most respectively and connects
Receiving end and the first receiving terminal of the second analog storage module 103 and the second receiving terminal, the first of the first analog storage module 102
Outfan and the second outfan connect first input end and second input of the first amplification module 104, the second analog storage respectively
First outfan of module 103 and the second outfan connect first input end and second input of the second amplification module 105 respectively,
The outfan of the first amplification module 104 is bonded into the first input end of module 106, and the outfan of the second amplification module 105 engages
Become the second input of module 106, the output termination output module 107 of synthesis module 106.
Input module 101 exports the big pixel photoreceptor signal of image and sequentially passes through the first analog storage module 102 and deposit
Storage and the first amplification module 104 export the first optimization photoreceptor signal after being amplified processing；
Input module 101 exports the small pixel photoreceptor signal of image and sequentially passes through the second analog storage module 103 and deposit
Storage and the second amplification module 105 export the second optimization photoreceptor signal after being amplified processing；
Synthesis module 106 optimizes photoreceptor signal by first and the second optimization photoreceptor signal synthesizes, and by output mould
Block 107 exports wide dynamic images signal.
As one embodiment of the invention, big pixel photoreceptor signal and small pixel photoreceptor signal are divided by described input module 101
After taking indescribably, use twin-channel form to export, serial samples photoreceptor signal is deposited to corresponding sampling capacitance
Storage, more parallel the signal on sampling capacitance is carried out computing and amplification, then pass through operational amplifier to this photosensitive letter of big pixel
Number and small pixel photoreceptor signal be weighted process and synthesize, export wide dynamic images signal.Described big pixel photoreceptor signal
Pixel value be more than 10,000,000 pixels, the pixel value of described small pixel photoreceptor signal is less than 10,000,000 pixels.
Fig. 2 has gone out the exemplary circuit of the image processing apparatus that the embodiment of the present invention provides, and for convenience of description, illustrate only
The part relevant to the embodiment of the present invention, details are as follows:
As one embodiment of the invention, this input module 101 includes:
First switching tube M1, second switch pipe M2, the 3rd switching tube M3, the 4th switching tube M4, the 5th switching tube M5, big picture
Element photocell PL, small pixel photocell PS, reset capacitance CFD；
The input termination main control signal RX of the first switching tube M1, the outfan of the first switching tube M1 and the 4th switching tube M4
Outfan connect, the outfan controlling end and second switch pipe M2 of the first switching tube M1 and the output of the 3rd switching tube M3
End connects, the control end of the electric charge output termination second switch pipe M2 of big pixel light fulgurite PL, the input of second switch pipe M2
Connect the first control signal TXL, the control end of electric charge output termination the 3rd switching tube M3 of small pixel photocell PS, the 3rd switching tube
The input of M3 terminates the second control signal TXS, the first end of reset capacitance CFD and the control end and the 4th of the first switching tube M1
The input of switching tube M4 connects, the second end ground connection of reset capacitance CFD, control termination the 5th switching tube of the 4th switching tube M4
The control end of M5, input termination reset signal RS of the 5th switching tube M5, the outfan of the 5th switching tube M5 is input module 101
Outfan.This reset capacitance CFD can be integrated capacitor, it is also possible to be by parasitic capacitance produced by ghost effect.Make
For one embodiment of the invention, this first switching tube M1, second switch pipe M2, the 3rd switching tube M3, the 4th switching tube M4, the 5th open
Closing pipe M5 can also use audion or field effect transistor to replace, as long as the effect with the embodiment of the present invention can be played.
As one embodiment of the invention, this first analog storage module 102 includes:
First switch SHRL, second switch SHSL, the first sampling capacitance CLr and the first storage electric capacity CLs；
First receiving terminal that first end is the first analog storage module 102 of the first switch SHRL, the first switch SHRL's
Second end and first end connection first outfan as the first analog storage module 102 of the first sampling capacitance CLr, first
The second end ground connection of sampling capacitance CLr, first end of second switch SHSL is the second reception of the first analog storage module 102
End, first end of second end of second switch SHSL and the first storage electric capacity CLs connects and as the first analog storage module 102
The second outfan, first storage electric capacity CLs the second end ground connection.
As one embodiment of the invention, this second analog storage module 103 includes:
3rd switch SHRS, the 4th switch SHSS, the second sampling capacitance CSr and the second storage electric capacity CSs；
First receiving terminal that first end is the second analog storage module 103 of the 3rd switch SHRS, the 3rd switch SHRS's
Second end and first end connection first outfan as the second analog storage module 103 of the second sampling capacitance CSr, second
The second end ground connection of sampling capacitance CSr, the first end is the second analog storage module 103 second reception of the 4th switch SHSS
End, second end of the 4th switch SHSS and first end of the second storage electric capacity CSs connect and as the second analog storage module 103
The second outfan, second storage electric capacity CSs the second end ground connection.
As one embodiment of the invention, this first amplification module 104 includes the first operational amplifier COMP1, the first computing
The normal phase input end of amplifier COMP1, inverting input and outfan are respectively the first input of the first amplification module 104
End, the second input and outfan.
As one embodiment of the invention, this second amplification module 105 includes the second operational amplifier COMP2, the second computing
The normal phase input end of amplifier COMP2, inverting input and outfan are respectively the first input of the second amplification module 105
End, the second input and outfan.
As one embodiment of the invention, this synthesis module 106 includes the 3rd operational amplifier COMP2, the 3rd operation amplifier
The normal phase input end of device COMP2, inverting input and outfan are respectively the first input end of synthesis module 106, second defeated
Enter end and outfan.
Fig. 3 shows the steps flow chart of the image processing method that the embodiment of the present invention provides, and for convenience of description, only illustrates
The part relevant to the embodiment of the present invention, details are as follows:
A kind of image processing method based on the image processing apparatus described in claim 1, it is characterised in that described image
Processing method comprises the following steps:
The most described input module is for exporting big pixel photoreceptor signal and the small pixel photoreceptor signal of image；
The most described first analog storage module for described big pixel photoreceptor signal is stored, the most described the
Two analog storage modules are for storing described small pixel photoreceptor signal；
It is excellent that the most described first amplification module exports first after being amplified described big pixel photoreceptor signal processing
Allelopathic optical signal, the most described second amplification module exports second after being amplified described small pixel photoreceptor signal processing
Optimize photoreceptor signal；
The most described synthesis module is carried out for optimizing photoreceptor signal and described second optimization photoreceptor signal by described first
Synthesis, and export wide dynamic images signal by described output module.
Below in conjunction with Fig. 1 and Fig. 2, the operation principle of above-mentioned image processing apparatus with method is illustrated:
First, the first switching tube M1, when pixel reading circuit works, is opened by main control signal RX, to reset capacitance
CFD resets, and this resetting voltage VRL is sampled extremely by the 4th switching tube M4, the 5th switching tube M5 and the first switch SHRL
The second switch pipe M2 that first sampling capacitance CLr, big pixel light fulgurite PL connect is opened by the first control signal TXL, this signal
Reaching reset capacitance CFD, the voltage VSL of this signal passes through the 4th switching tube M4, the 5th switching tube M5 and second switch SHSL
Store to the first storage electric capacity CLs；
Same, when small pixel PS is carried out signal-obtaining, control the first switching tube M1 to multiple by main control signal RX
Position electric capacity CFD resets, and this resetting voltage VRS is adopted by the 4th switching tube M4, the 5th switching tube M5 and the 3rd switch SHRS
The switching tube M3 that sample connects to the second sampling capacitance CSr, small pixel photocell PS is opened by the second control signal TXS, this signal
Reaching reset capacitance CFD, the voltage VSS of this signal is by the 4th switching tube M4, the 5th switching tube M5 and the 4th switch SHSS
Store to the second storage electric capacity CSs.
Especially, VRL-VSL is referred to as big pixel photoreceptor signal, VRS-VSS is referred to as small pixel photoreceptor signal, then leads to
Cross WDR synthesizer and big pixel photoreceptor signal and small pixel photoreceptor signal are weighted synthesis, export WDR picture element signal Vout.
Wherein weight coefficient can be set to by big pixel photoreceptor signal and the pro rate of small pixel photoreceptor signal, such as its weight coefficient
0.5, i.e. WDR picture element signal Vout=0.5* (VRL-VSL)+0.5* (VRS-VSS).
In sum, embodiments providing a kind of image processing apparatus and method, this image processing apparatus passes through
The big pixel photoreceptor signal of input module output image sequentially passes through the first analog storage module and carries out storage and the first amplification mould
Block exports the first optimization photoreceptor signal after being amplified processing, be simultaneously entered the small pixel photoreceptor signal of module output image successively
The second optimization photoreceptor signal is exported after the second analog storage module carries out storage and the second amplification module is amplified processing,
Then synthesis module optimizes photoreceptor signal by described first and described second optimization photoreceptor signal synthesizes, and by output mould
Block output wide dynamic images signal.Thus use the dual pathways that big pixel photoreceptor signal and small pixel photoreceptor signal are carried out WDR conjunction
Become, there is no the bottleneck of the shooting speed of frame rate reduction processing；Secondly, same image is processed, there is not time delay phenomenon, solve
Existing image composing technique also exists time delay, frame per second reduces and has a smear when the mobile target of shooting causes image mould
The problem stuck with paste.
One of ordinary skill in the art will appreciate that: the step or the part steps that realize said method embodiment can be passed through
The hardware that programmed instruction is relevant completes, and aforesaid program can be stored in computer read/write memory medium, and this program exists
During execution, perform to include the step of said method embodiment, and aforesaid storage medium includes: ROM, RAM, magnetic disc or CD
Etc. the various media that can store program code.
Embodiment described above only in order to technical scheme to be described, is not intended to limit；Although with reference to aforementioned reality
Execute example the present invention has been described in detail, it will be understood by those within the art that: its still can to aforementioned respectively
Technical scheme described in embodiment is modified, or wherein portion of techniques feature is carried out equivalent；And these amendments
Or replace, do not make the essence of appropriate technical solution depart from spirit and the model of the embodiment of the present invention each embodiment technical scheme
Enclose.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.
Claims (8)
1. an image processing apparatus, it is characterised in that described image processing apparatus includes:
Input module, the first analog storage module, the second analog storage module, the first amplification module, the second amplification module, synthesis
Module and output module；
The outfan of described input module connects first receiving terminal and second of described first analog storage module the most respectively and receives
End and the first receiving terminal of described second analog storage module and the second receiving terminal, the first of described first analog storage module
Outfan and the second outfan connect first input end and second input of described first amplification module, described second simulation respectively
First outfan of memory module and the second outfan connect first input end and second input of described second amplification module respectively
End, the output of described first amplification module terminates the first input end of described synthesis module, the output of described second amplification module
Terminating the second input of described synthesis module, the output of described synthesis module terminates described output module；
The big pixel photoreceptor signal of described input module output image sequentially passes through described first analog storage module and stores
The first optimization photoreceptor signal is exported with described first amplification module after being amplified processing；
The small pixel photoreceptor signal of described input module output image sequentially passes through described second analog storage module and stores
The second optimization photoreceptor signal is exported with described second amplification module after being amplified processing；
Described synthesis module optimizes photoreceptor signal by described first and described second optimization photoreceptor signal synthesizes, and passes through institute
State output module output wide dynamic images signal.
2. image processing apparatus as claimed in claim 1, it is characterised in that described input module includes:
First switching tube M1, second switch pipe M2, the 3rd switching tube M3, the 4th switching tube M4, the 5th switching tube M5, big pixel light
Fulgurite PL, small pixel photocell PS, reset capacitance CFD；
The input termination main control signal RX of described first switching tube M1, the outfan and the described 4th of described first switching tube M1
The outfan of switching tube M4 connects, and described first switching tube M1 controls end and the outfan of described second switch pipe M2 and institute
The outfan stating the 3rd switching tube M3 connects, and the electric charge output of big pixel light fulgurite PL described in photocell terminates described second switch
The control end of pipe M2, the input of described second switch pipe M2 terminates the first control signal TXL, the electricity of described small pixel photocell PS
Lotus output terminates the control end of described 3rd switching tube M3, and the input of described 3rd switching tube M3 terminates the second control signal TXS,
First end of described reset capacitance CFD controls end and the input of described 4th switching tube M4 with described first switching tube M1's
Connecting, the second end ground connection of described reset capacitance CFD, described 4th switching tube M4 controls the described 5th switching tube M5's of termination
Controlling end, input termination reset signal RS of described 5th switching tube M5, the outfan of described 5th switching tube M5 is described defeated
Enter the outfan of module.
3. image processing apparatus as claimed in claim 1, it is characterised in that described first analog storage module includes:
First switch SHRL, second switch SHSL, the first sampling capacitance CLr and the first storage electric capacity CLs；
First receiving terminal that first end is described first analog storage module of described first switch SHRL, described first switch
Second end of SHRL is connected and as the first of described first analog storage module with first end of described first sampling capacitance CLr
Outfan, the second end ground connection of described first sampling capacitance CLr, first end of described second switch SHSL is described first simulation
Second receiving terminal of memory module, second end of described second switch SHSL connects with first end of described first storage electric capacity CLs
Connect and as the second outfan of described first analog storage module, the second end ground connection of described first storage electric capacity CLs.
4. image processing apparatus as claimed in claim 1, it is characterised in that described second analog storage module includes:
3rd switch SHRS, the 4th switch SHSS, the second sampling capacitance CSr and the second storage electric capacity CSs；
First receiving terminal that first end is described second analog storage module of described 3rd switch SHRS, described 3rd switch
Second end of SHRS is connected and as the first of described second analog storage module with first end of described second sampling capacitance CSr
Outfan, the second end ground connection of described second sampling capacitance CSr, first end of described 4th switch SHSS is described second simulation
Second receiving terminal of memory module, second end of described 4th switch SHSS connects with first end of described second storage electric capacity CSs
Connect and as the second outfan of described second analog storage module, the second end ground connection of described second storage electric capacity CSs.
5. image processing apparatus as claimed in claim 1, it is characterised in that described first amplification module includes that the first computing is put
Big device COMP1,
Normal phase input end, inverting input and the outfan of described first operational amplifier COMP1 is respectively described first and puts
The big first input end of module, the second input and outfan.
6. image processing apparatus as claimed in claim 1, it is characterised in that described second amplification module includes that the second computing is put
Big device COMP2,
Normal phase input end, inverting input and the outfan of described second operational amplifier COMP2 is respectively described second and puts
The big first input end of module, the second input and outfan.
7. image processing apparatus as claimed in claim 1, it is characterised in that described synthesis module includes the 3rd operational amplifier
COMP2,
Normal phase input end, inverting input and the outfan of described 3rd operational amplifier COMP2 are respectively described synthesis mould
The first input end of block, the second input and outfan.
8. an image processing method based on the image processing apparatus described in claim 1, it is characterised in that at described image
Reason method comprises the following steps:
The most described input module is for exporting big pixel photoreceptor signal and the small pixel photoreceptor signal of image；
The most described first analog storage module is for storing described big pixel photoreceptor signal, and the most described second simulation is deposited
Storage module is for storing described small pixel photoreceptor signal；
It is photosensitive that the most described first amplification module exports the first optimization to described big pixel photoreceptor signal after being amplified processing
Signal, the most described second amplification module exports the second optimization sense to described small pixel photoreceptor signal after being amplified processing
Optical signal；
The most described synthesis module synthesizes for optimizing photoreceptor signal and described second optimization photoreceptor signal by described first, and
Wide dynamic images signal is exported by described output module.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000092396A (en) * | 1998-09-16 | 2000-03-31 | Olympus Optical Co Ltd | Image pickup device using amplification type solid-state image pickup element |
| CN1514652A (en) * | 2002-12-25 | 2004-07-21 | ��ʿ��Ƭ��ʽ���� | Image synthesizing method and camera device |
| US20070200935A1 (en) * | 1998-12-21 | 2007-08-30 | Sony Corporation | Image pickup method and apparatus, and image processing method and apparatus |
| CN101365069A (en) * | 2007-06-29 | 2009-02-11 | 豪威科技有限公司 | High dynamic range sensor with blooming drain |
| CN101729796A (en) * | 2008-10-14 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
| CN102158653A (en) * | 2011-05-03 | 2011-08-17 | 东华大学 | Device and method for acquiring digital image with high dynamic range in real time |
| CN102164251A (en) * | 2011-05-25 | 2011-08-24 | 格科微电子（上海）有限公司 | Signal processing circuit and signal processing method for image sensor |
| CN102547159A (en) * | 2012-02-16 | 2012-07-04 | 上海中科高等研究院 | Wide-dynamic range image sensor and control method thereof |
| CN103259985A (en) * | 2013-05-17 | 2013-08-21 | 昆山锐芯微电子有限公司 | CMOS image sensor, pixel unit and control method of pixel unit |
| JP2014175985A (en) * | 2013-03-12 | 2014-09-22 | Ricoh Co Ltd | Photoelectric conversion device and image generation device |
| CN104733480A (en) * | 2013-12-19 | 2015-06-24 | 全视科技有限公司 | Image sensor pixel for use in high dynamic range image sensor |
-
2016
- 2016-09-05 CN CN201610802701.6A patent/CN106331434B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000092396A (en) * | 1998-09-16 | 2000-03-31 | Olympus Optical Co Ltd | Image pickup device using amplification type solid-state image pickup element |
| US20070200935A1 (en) * | 1998-12-21 | 2007-08-30 | Sony Corporation | Image pickup method and apparatus, and image processing method and apparatus |
| CN1514652A (en) * | 2002-12-25 | 2004-07-21 | ��ʿ��Ƭ��ʽ���� | Image synthesizing method and camera device |
| CN101365069A (en) * | 2007-06-29 | 2009-02-11 | 豪威科技有限公司 | High dynamic range sensor with blooming drain |
| CN101729796A (en) * | 2008-10-14 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
| CN102158653A (en) * | 2011-05-03 | 2011-08-17 | 东华大学 | Device and method for acquiring digital image with high dynamic range in real time |
| CN102164251A (en) * | 2011-05-25 | 2011-08-24 | 格科微电子（上海）有限公司 | Signal processing circuit and signal processing method for image sensor |
| CN102547159A (en) * | 2012-02-16 | 2012-07-04 | 上海中科高等研究院 | Wide-dynamic range image sensor and control method thereof |
| JP2014175985A (en) * | 2013-03-12 | 2014-09-22 | Ricoh Co Ltd | Photoelectric conversion device and image generation device |
| CN103259985A (en) * | 2013-05-17 | 2013-08-21 | 昆山锐芯微电子有限公司 | CMOS image sensor, pixel unit and control method of pixel unit |
| CN104733480A (en) * | 2013-12-19 | 2015-06-24 | 全视科技有限公司 | Image sensor pixel for use in high dynamic range image sensor |
Non-Patent Citations (1)
| Title |
|---|
| 佟首峰等: "CCD图像传感器降噪技术的研究", 《光学精密工程》 * |
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