WO2024140724A1

WO2024140724A1 - Image sensor, camera module and electronic device

Info

Publication number: WO2024140724A1
Application number: PCT/CN2023/142085
Authority: WO
Inventors: 罗轶; 易铃棋
Original assignee: 维沃移动通信有限公司
Priority date: 2022-12-30
Filing date: 2023-12-26
Publication date: 2024-07-04

Abstract

The present application belongs to the technical field of image processing. Disclosed are an image sensor, a camera module and an electronic device. The image sensor comprises a pixel array, a conversion gain selection logic module and a cache line decoding driving module, wherein the pixel array comprises N rows of pixel units and M columns of pixel units; N pixel units in the same column are connected to the conversion gain selection logic module by means of a first connection line, and M pixel units in the same row are connected to the cache line decoding driving module by means of a second connection line; the conversion gain selection logic module is used for determining, according to a first pixel output signal of each pixel unit, a dual-gain mode selection signal corresponding to each pixel unit; and the pixel unit is used for writing, when receiving a cache control signal sent by the cache line decoding driving module, the dual-gain mode selection signal corresponding to the pixel unit, both M and N being positive integers.

Description

Image sensors, camera modules and electronic devices

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on December 30, 2022, with application number 202211736330.8 and title “Image sensor, camera module and electronic device”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application belongs to the field of image processing technology, and specifically relates to an image sensor, a camera module and an electronic device.

Background technique

In image sensors (Complementry Metal-Oxide Semiconductor, CMOS), the dynamic range adjustment of an image is generally achieved by changing the pixel exposure time of all pixels and making an overall adjustment to the pixel signal gain.

In mainstream High Dynamic Range (HDR) or Wide Dynamic Range (WDR) technologies, whether it is multi-frame, line interleaving, or dual gain scheme, all pixels use the same exposure time. The modulation effect of HDR is changed by adjusting the exposure time and the output signal gain. For example, in Dual Conversion Gain (DCG) technology, all pixels are exposed long/short together, but the output signal is amplified with different gains, that is, only the readout signal is amplified with high/low gain.

However, in the related technology, based on the DCG-HDR function, in the implementation process, since pixel-by-pixel modulation cannot be performed, all pixel units in the pixel array often need to be exposed in the high gain (High Conversion Gain, HCG) mode first, and then exposed in the low gain (Low Conversion Gain, LCG) mode after reading. This method not only has high requirements on computing power, but also the synthesized HDR image often has brightness/color stratification and signal-to-noise ratio (SNR) drop due to processing defects. For example, in scenes with complex changes in brightness and darkness, the existing DCG-HDR technology has some pixels locally overexposed or some pixels underexposed in the output images of certain scenes.

Summary of the invention

The purpose of the embodiments of the present application is to provide an image sensor, a camera module and an electronic device, which can solve the problem of poor output image imaging effect caused by the inability to perform pixel-by-pixel modulation during the implementation of the DCG-HDR function.

In a first aspect, an embodiment of the present application provides an image sensor, comprising: a pixel array, a conversion gain selection logic module, and a cache line decoding drive module;

The pixel array includes N rows of pixel units and M columns of pixel units. The N pixel units in the same column are connected to the conversion gain selection logic module through a first connection line; the M pixel units in the same row are connected to the conversion gain selection logic module through a second connection line. The cache line decoding driver module is connected;

Wherein, the conversion gain selection logic module is used to determine the dual gain mode selection signal corresponding to each pixel unit according to the first pixel output signal of each pixel unit;

The pixel unit is used to write a dual gain mode selection signal corresponding to the pixel unit when receiving a cache control signal sent by the cache row decoding driving module, and both M and N are positive integers.

In a second aspect, an embodiment of the present application provides a camera module, comprising an image sensor as described in the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, comprising the camera module as described in the second aspect.

In an embodiment of the present application, the conversion gain selection logic module can automatically determine the corresponding dual gain mode selection signal for each pixel unit based on the sampling of the pixel output signal of each pixel unit, and send the dual gain mode selection signal to the corresponding pixel unit, so that each pixel unit can determine whether it should operate in high gain mode or low gain mode according to the dual gain mode selection signal within each frame time, thereby realizing pixel-level gain adjustment, avoiding the high computing power requirements and poor adjustment effect caused by the overall adjustment of the pixel array, and the adjustment mode of each pixel unit is determined according to the pixel output signal in the current time, ensuring the accuracy and effectiveness of the pixel adjustment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a pixel array in the related art;

FIG2 is a schematic diagram of a structure of an image sensor according to an embodiment of the present application;

FIG3 is a schematic diagram of a conversion gain selection logic module structure according to an embodiment of the present application;

FIG4 is a second schematic diagram of the structure of an image sensor provided in an embodiment of the present application;

FIG5 is a second schematic diagram of the conversion gain selection logic module structure provided in an embodiment of the present application;

FIG. 6 is a third schematic diagram of the image sensor structure provided in an embodiment of the present application.

Specific embodiments

The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and/or" in the specification and claims represents at least one of the connected objects, and the character "/" generally indicates that the objects associated with each other are in an "or" relationship.

The image sensor, camera module and electronic device provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in combination with the accompanying drawings.

In the related art, the realization of DCG-HDR technology relies on the improvement of the traditional 4-in-1 pixel array (4-Transistor Active Pixel Sensor, 4T-APS) pixels. Figure 1 is a structural schematic diagram of the pixel array in the related art. As shown in Figure 1, the traditional RGGB pixel array or synthetic pixel array (such as a 4-in-1 pixel array) includes components for realizing the DCG function in the pixel circuit module: the typical design is a DCG transistor and a corresponding capacitor C.

The specific working principle is as follows: the photodiode (PD) in the optical module of the pixel is responsible for photosensitivity and photoelectric conversion in each frame time. The generated charge e- is cached in the floating diffusion (FD) capacitor after passing through the TX transistor switch. In the readout stage, the charge e- in the FD will be amplified by the source follower (SF) transistor and converted into a corresponding voltage, and the pixel signal PIX_OUT is output to the outside of the pixel after passing through the SEL transistor switch. The RST transistor is responsible for resetting the FD to the voltage VDD. The DCG function is implemented to change the size of the FD. In the HCG mode, the FD needs to be as small as possible. In the LCG mode, the FD needs to be as large as possible. Therefore, a DCG transistor switch and a capacitor C are added. The DCG transistor switch is responsible for the mode conversion between HCG and LCG, and the capacitor C is responsible for expanding the FD capacitor. When the pixel needs to be in HCG, the DCG transistor switch is disconnected, and the FD is responsible for receiving the charge e- transferred from the PD. When the pixel needs to be in LCG mode, the DCG transistor is closed to connect FD and C to expand the capacitance (the RST transistor switch must remain open to prevent resetting). Therefore, the charge e- transferred from PD is FD+C. In summary, the essential method of realizing the DCG function is to change the size of the FD capacitor according to the needs.

In the field of computational photography, pixel-by-pixel control technology can achieve pixel-level dynamic range control to avoid image overexposure or underexposure. Specifically, it can encode overexposed or underexposed pixels pixel by pixel and perform gain control, which can effectively eliminate the problem of overexposure or underexposure. By modulating a single pixel, the problem of the edge of the area being too abrupt can be effectively avoided.

FIG. 2 is one of the schematic diagrams of the structure of the image sensor provided by the embodiment of the present application. As shown in FIG. 2 , the image sensor comprises: a pixel array 11, a conversion gain selection logic module 12, and a cache line decoding driving module 13;

The pixel array 11 includes N rows of pixel units and M columns of pixel units 110. The M pixel units 110 in the same row are connected to the cache row decoding driving module 13 via a second connection line 111; the N pixel units 110 in the same column are connected to the conversion gain selection logic module 12 via a first connection line 112.

The conversion gain selection logic module 12 is used to determine the dual gain mode selection signal corresponding to each pixel unit 110 according to the first pixel output signal of each pixel unit 110;

The pixel unit 110 is used to write a dual gain mode selection signal corresponding to the pixel unit 110 when receiving a cache control signal sent by the cache row decoding driving module 13 , where M and N are both positive integers.

Specifically, the pixel array described in the embodiment of the present application includes a plurality of pixel units, which may specifically include N pixel rows in the same row and M pixel columns in the same column, corresponding to NxM pixel units in each pixel array.

In the embodiment of the present application, the conversion gain selection logic module and the cache row decoding driving module both use a row/column parallel wiring layout to transmit or control signals to the pixel array.

Specifically, in order to further save wiring space, M pixel units in the same row are connected to the cache row decoding driver module through the same connection line. Accordingly, each pixel row in the pixel array is connected to the cache row decoding driver module through its corresponding connection line.

Accordingly, the cache row decoding driving module may transmit a cache control signal to each pixel row respectively. More specifically, the cache row decoding driving module may transmit a corresponding cache control signal to each pixel unit in the pixel row.

Specifically, also for the consideration of saving wiring space, the N pixel units in the same column may also be connected to the conversion gain selection logic module through the same connection line.

The first pixel output signal of the pixel unit described in the embodiment of the present application may specifically be a pixel output signal output by the pixel unit in the current frame after being reset and exposed. The first pixel output signal of each pixel unit may be a different pixel output signal.

The conversion gain selection logic module described in the embodiment of the present application is specifically used to further determine whether each pixel unit is suitable for a high gain mode or a low gain mode based on the first pixel output signal of each pixel unit, and then obtain a dual gain mode selection signal corresponding to each pixel unit.

In an embodiment of the present application, the dual gain mode selection signal corresponding to each pixel unit can be a digital signal or an analog signal. The dual gain mode selection signal will control the pixel unit to output the pixel signal according to the gain mode indicated by the dual gain mode selection signal within this frame time.

The cache row decoding driver module described in the embodiment of the present application may specifically include a decoder and a driver controlled by a control logic unit. The cache row decoding driver module can output a cache control signal for one or more pixel rows. After the pixel unit receives the cache control signal, it can activate the cache in the pixel unit and write the dual gain mode selection signal into the cache of the pixel unit, so that when the pixel output signal is subsequently read, the pixel output signal can be gain amplified according to the gain mode indicated by the dual gain mode selection signal.

Optionally, the pixel unit specifically includes: an in-pixel cache device, the in-pixel cache device is connected to the cache row decoding driving module via the first connecting line;

Wherein, the in-pixel cache device is used to cache the dual-gain mode selection signal.

More specifically, in the embodiment of the present application, an in-pixel cache device is newly provided in each pixel unit, and the in-pixel cache module is specifically used to cache the dual-gain mode selection signal of the pixel unit within the current frame time.

The pixel cache devices in the same row of pixel units are connected to the cache row decoding driving module through the first connecting line. The cache row decoding driving module determines the corresponding pixel units according to the first pixel output signal of each pixel unit. After receiving the dual gain mode selection signal, the dual gain mode selection signal corresponding to each pixel unit is transmitted to the buffer device in the pixel through the first connecting line.

After the pixel unit receives the cache control signal sent by the cache row decoding driving module, the pixel unit activates the in-pixel cache device, receives the dual-gain mode selection signal output by the cache row decoding driving module through the first connecting line, writes the received dual-gain mode selection signal into the in-pixel cache device, and deletes the dual-gain mode selection signal of the previous frame time originally stored in the in-pixel cache device.

In the embodiment of the present application, the dual gain mode selection signal corresponding to each pixel unit can be stored separately through the in-pixel cache device, which can effectively realize pixel adjustment on a pixel by pixel basis, and the in-pixel cache device can effectively update the dual gain mode selection signal in the in-pixel cache device within each frame time, effectively realizing pixel adjustment processing on a time frame by time frame, thereby ensuring the accuracy of image adjustment.

Optionally, the conversion gain selection logic module includes: M first conversion gain selection logic submodules, the first conversion gain selection logic submodule includes: a first mode selection unit and a first analog-to-digital conversion unit, the first mode selection unit and the first analog-to-digital conversion unit are connected;

The pixel units in the same column are connected to the corresponding first analog-to-digital conversion unit through a third connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding first mode selection unit through the first connection line;

The first analog-to-digital conversion unit is used to perform analog-to-digital conversion on the first pixel output signal of the pixel unit to obtain a first pixel output digital signal;

The first mode selection unit is used to analyze the first pixel output digital signal to obtain a dual-gain mode selection signal, and transmit the dual-gain mode selection signal to the in-pixel cache device of the corresponding pixel unit.

FIG3 is one of the schematic diagrams of the conversion gain selection logic module structure provided in an embodiment of the present application. As shown in FIG3 , each first conversion gain selection logic submodule 121 includes: a first mode selection unit 1211 and a first analog-to-digital conversion unit 1212. The first analog-to-digital conversion unit can specifically be a successive approximation register. The first mode selection unit 1211 and the first analog-to-digital conversion unit 1212 are connected. FIG4 is a second schematic diagram of the image sensor structure provided in an embodiment of the present application. As shown in FIG4 , the first conversion gain selection logic submodule 121 includes: a first mode selection unit 1211 and a first analog-to-digital conversion unit 1212. The pixel unit 110 in each pixel column can be connected to the corresponding first conversion gain selection logic submodule 121 via a third connecting line, that is, M pixel columns are connected with M first conversion gain selection logic submodules.

More specifically, in an embodiment of the present application, each pixel unit in the same column is connected to its corresponding first analog-to-digital conversion unit through a third connecting line, and at the same time, the pixel in-pixel cache device in the pixel unit in the same column is connected to the corresponding first mode selection unit through the first connecting line.

The first analog-to-digital conversion unit is a successive approximation register;

The successive approximation register is used to convert the first pixel output signal into a 2-bit digital signal through a successive approximation register logic to obtain a first pixel output digital signal.

More specifically, the first pixel output signal of each pixel unit in the pixel column first enters the first An analog-to-digital conversion unit implements analog-to-digital conversion processing to convert the first pixel output signal into a digital signal to obtain a first pixel output digital signal.

More specifically, the first analog-to-digital conversion unit in the embodiment of the present application can specifically adopt a successive approximation register (SAR) analog-to-digital conversion architecture with a 2-bit resolution. The first pixel output signal (φPIX) is converted into a 2-bit digital signal (SAR_OUT[S1, S0]) through the successive approximation register logic SAR Logic, that is, the first pixel output digital signal.

V _SAR and V _REF in the first analog-to-digital conversion unit are modulation bias voltages. The user can change the input voltage range and resolution of the first analog-to-digital conversion unit by changing the magnitudes of these two voltages.

More specifically, the first mode selection unit performs mode selection analysis according to the first pixel output digital information, and thereby obtains a dual-gain mode selection signal for each pixel unit.

After calculating and obtaining the dual-gain mode selection signal, the first mode selection unit may transmit the dual-gain selection signal corresponding to each pixel unit to the in-pixel buffer device of the pixel unit through the first connection line.

Optionally, the first mode selection unit comprises: a first adder and a mode selection logic subunit;

Wherein, the first adder is used to add the first pixel output digital signal and a preset increase threshold signal to obtain an adder output signal;

The mode selection logic subunit is used to obtain a dual-gain mode selection signal according to the adder output signal, and transmit the dual-gain mode selection signal to the in-pixel cache device of the corresponding pixel unit.

More specifically, in the embodiment of the present application, the user may also wish to artificially increase the output value of the first pixel output digital signal SAR_OUT[S1, S0], and therefore a first adder may be further added to the first mode selection unit. The first adder may specifically be a 2-bit adder that cooperates with the 2-bit first pixel output digital signal.

The preset increase threshold signal described in the embodiment of the present application may specifically be a preset increase threshold signal CG_THR[T1, T0].

The first adder may specifically add the first pixel output digital signal SAR_OUT[S1, S0] and the preset increase threshold signal CG_THR[T ₁ , T ₀ ] to obtain an adder output signal, and send the adder output signal to the logic selection unit for processing.

The mode selection logic subunit in the embodiment of the present application may be specifically configured with a preset truth table, which may specifically match the dual-gain mode selection signal corresponding to the adder output signal through truth table 1.

For example, the truth table 1 is shown in Table 1 below:

Table 1

Among them, [C, A1, A0] is the adder output signal, (φDCG_SEL) is the dual gain mode selection signal, when (φDCG_SEL) is 0, the dual gain mode selection signal corresponds to the low gain mode, when (φDCG_SEL) is 1, the dual gain mode selection signal corresponds to the high gain mode.

Optionally, in an embodiment of the present application, a user-controlled master control signal CG_SET[I1, I0] is preset in the selection logic subunit. Through this preset master control signal, the form of the output dual gain mode selection signal can be specified, so that when the conversion gain selection logic module is shielded or fails, it can continue to operate normally in high gain or low gain mode to collect and output images.

The mode selection logic subunit analyzes and obtains the dual-gain mode selection signal corresponding to each pixel, and transmits the dual-gain mode selection signal to the pixel in-pixel cache device of the corresponding pixel unit.

In an embodiment of the present application, the first pixel output signal is sampled by a first conversion gain selection logic submodule including a first analog-to-digital conversion unit, and the first analog-to-digital conversion unit can adopt a high-speed and low-power analog-to-digital conversion unit, which can effectively improve the mode selection rate and reduce the operating power consumption. At the same time, the generation of the dual-gain mode selection signal does not rely on the intervention of external devices.

Optionally, the conversion gain selection logic module includes: M second conversion gain selection logic submodules, the second conversion gain selection logic submodule includes: a second mode selection unit and a comparator unit, the second mode selection unit is connected to the comparator unit;

The pixel units in the same column are connected to the corresponding comparator units through a fourth connection line, and the in-pixel cache devices in the pixel units in the same column are connected to the corresponding second mode selection units through the first connection line;

The comparator unit is used to obtain a comparator unit output signal according to a preset modulation bias voltage signal and the first pixel output signal;

The second mode selection unit is used to determine a dual-gain mode selection signal according to the output signal of the comparator unit, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.

FIG5 is a second schematic diagram of the conversion gain selection logic module structure provided in an embodiment of the present application. As shown in FIG5 , it includes: M second conversion gain selection logic submodules 141, the second conversion gain selection logic submodule 141 includes: a second mode selection unit 1411 and a comparator unit 1412, the second mode selection unit 1411 and the comparator unit 1412 are connected;

FIG6 is a third schematic diagram of the image sensor structure provided in an embodiment of the present application. As shown in FIG6 , the second conversion gain selection logic submodule 141 includes: a second mode selection unit 1411 and a comparator unit 1412. The pixel unit 110 in each pixel column can be connected to its corresponding second conversion gain selection logic submodule 141 via a fourth connecting line, that is, M pixel columns are connected to M second conversion gain selection logic submodules.

More specifically, the pixel column is directly connected to the comparator unit in the second conversion gain selection logic submodule through a fourth connecting line. After the second mode selection unit is connected in series to the comparator unit, the first pixel output signal of each pixel unit is first input into the comparator unit for comparison and analysis with a preset modulation bias voltage signal V _THR , and then the comparator unit output signal is obtained according to the comparison and analysis result.

The second mode selection unit will further perform gain mode analysis based on the output signal of the comparator unit to obtain a dual gain mode selection signal corresponding to each pixel unit, and then the second mode selection unit will transmit the dual gain mode selection signal to the pixel cache device in the corresponding pixel unit through the first connecting line.

Optionally, the comparator unit is specifically used to:

When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit output signal is a low level output signal;

When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit output signal is a high level output signal;

Wherein, the second mode selection unit is used to determine that the dual-gain mode selection signal is a low-gain mode selection signal according to the low-level output signal;

Alternatively, the second mode selection unit is used to determine that the dual-gain mode selection signal is a high-gain mode selection signal according to the high-level output signal.

The preset modulation bias voltage signal described in the embodiment of the present application may be an externally input voltage signal, and its voltage magnitude and period may be pre-modulated by the user.

After entering the comparator unit, the first pixel output signal inputted by each pixel unit is firstly compared with the preset modulation bias voltage signal.

When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit always outputs a low level (COMP_OUT=0), that is, the output signal of the comparator unit at this time is a low level output signal.

When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit always outputs a high level (COMP_OUT=1), that is, the comparator unit output signal at this time is a high level output signal.

After the comparator unit output signal is obtained, it is input into the second mode selection unit for calculation. The second mode selection unit may be configured with a preset truth table 2, and the dual gain mode selection corresponding to the comparator unit output is matched through truth table 2.

For example, truth table 2 is shown in Table 2 below:

Among them, COMP_OUT is the comparator unit output signal. When the comparator unit output signal is a low-level output signal 0, the dual gain mode selection signal (φDCG_SEL) is determined to be a low gain mode selection signal 0. When the comparator unit output signal is a high-level output signal 1, the dual gain mode selection signal is determined to be a high gain mode selection signal 1.

Optionally, the second mode selection unit in the embodiment of the present application is also pre-configured with a master control signal CG_SET[I1, I0] controlled by the user. Through this preset master control signal, the form of the output dual gain mode selection signal can be specified, so that when the conversion gain selection logic module is shielded or fails, it can continue to operate normally in high gain or low gain mode to collect and output images.

In the embodiment of the present application, a simple comparator unit is used to effectively improve the generation efficiency of the gain mode selection signal, while effectively reducing the occupied area of the conversion gain selection logic module in the image sensor. The conversion gain selection logic module calculates the corresponding dual gain mode selection signal for the first pixel output signal of each pixel unit, which can effectively implement the gain mode adjustment for each pixel unit and effectively ensure the final imaging effect.

Optionally, the pixel array further comprises: a signal reading module;

The N pixel units in the same column are connected to the signal reading module via a fifth connecting line;

The signal reading module is used to read the second pixel output signal of each pixel unit, and the second pixel output signal is obtained after the pixel unit performs signal gain processing according to the signal gain mode corresponding to the written dual gain mode selection signal.

Specifically, the fifth connection line described in the embodiment of the present application may be the same connection line as the third connection line or the fourth connection line in the above embodiment.

In the embodiment of the present application, in each frame time, after each pixel unit completes resetting and exposure, it will enter the reading phase, at which time the signal reading module will read the pixel output signal of each pixel unit.

In the process of reading the pixel output signal, the corresponding gain mode of the pixel unit is determined according to the dual gain mode selection signal cached by the in-pixel cache device in each pixel unit, that is, whether each pixel unit is suitable for high gain mode or low gain mode.

In the process of reading the pixel output signal, the signal is output according to the gain mode corresponding to the pixel unit, and finally a second pixel output signal after gain processing is obtained.

Optionally, in the embodiment of the present application, after the second pixel output signal is obtained, the second pixel output signal can be used as the first pixel output signal in the next frame time to help each pixel unit in the next frame select its corresponding dual Gain mode selection signal.

In an optional embodiment, the conversion gain selection logic module described in the embodiment of the present application can be specifically a simple decoder, and the dual gain mode selection signal required by each pixel unit can be specifically provided by an external module. The dual gain mode selection signal required by each pixel unit can be issued through the conversion gain selection logic module.

Optionally, an embodiment of the present application also provides a camera module including the above-mentioned image sensor, through which pixel-by-pixel modulation can be performed in the process of realizing the DCG-HDR function, thereby effectively ensuring the imaging effect of the output image.

Optionally, the embodiment of the present application further provides an electronic device, which includes the camera module in the above embodiment, and the electronic device can be a terminal or other devices other than the terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR)/virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not make specific limitations.

The electronic device in the embodiment of the present application may be a device having an operating system. The operating system may be Android

(Android) operating system, may be an iOS operating system, or may be other possible operating systems, which are not specifically limited in the embodiments of the present application.

It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above specific embodiments. The above-mentioned specific implementation modes are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

An image sensor comprises: a pixel array, a conversion gain selection logic module, and a cache line decoding drive module;

The pixel array includes N rows of pixel units and M columns of pixel units, the N pixel units in the same column are connected to the conversion gain selection logic module through a first connection line; the M pixel units in the same row are connected to the cache row decoding drive module through a second connection line;

Wherein, the conversion gain selection logic module is used to determine the dual gain mode selection signal corresponding to each pixel unit according to the first pixel output signal of each pixel unit;

The pixel unit is used to write a dual gain mode selection signal corresponding to the pixel unit when receiving a cache control signal sent by the cache row decoding driving module, and both M and N are positive integers.
The image sensor according to claim 1, wherein the pixel unit specifically comprises: an in-pixel cache device, the in-pixel cache device is connected to the cache row decoding driver module through the first connection line;

Wherein, the in-pixel cache device is used to cache the dual-gain mode selection signal.
The image sensor according to claim 2, wherein the conversion gain selection logic module comprises: M first conversion gain selection logic submodules, the first conversion gain selection logic submodule comprising: a first mode selection unit and a first analog-to-digital conversion unit, the first mode selection unit and the first analog-to-digital conversion unit are connected;

The pixel units in the same column are connected to the corresponding first analog-to-digital conversion unit through a third connection line, and the in-pixel buffer devices in the pixel units in the same column are connected to the corresponding first mode selection unit through the first connection line;

The first analog-to-digital conversion unit is used to perform analog-to-digital conversion on the first pixel output signal of the pixel unit to obtain a first pixel output digital signal;

The first mode selection unit is used to analyze the first pixel output digital signal to obtain a dual-gain mode selection signal, and transmit the dual-gain mode selection signal to the in-pixel cache device of the corresponding pixel unit.
The image sensor according to claim 3, wherein the first analog-to-digital conversion unit is a successive approximation register;

The successive approximation register is used to convert the first pixel output signal into a 2-bit digital signal through a successive approximation register logic to obtain a first pixel output digital signal.
The image sensor according to claim 3, wherein the first mode selection unit comprises: a first adder and a mode selection logic subunit;

Wherein, the first adder is used to add the first pixel output digital signal and a preset increase threshold signal to obtain an adder output signal;

The mode selection logic subunit is used to obtain a dual-gain mode selection signal according to the adder output signal, and transmit the dual-gain mode selection signal to the in-pixel cache device of the corresponding pixel unit.
The image sensor according to claim 2, wherein the conversion gain selection logic module comprises: M second conversion gain selection logic submodules, and the second conversion gain selection logic submodule comprises: a second mode selection A selection unit and a comparator unit, wherein the second mode selection unit is connected to the comparator unit;

The pixel units in the same column are connected to the corresponding comparator units through a fourth connection line, and the in-pixel cache devices in the pixel units in the same column are connected to the corresponding second mode selection units through the first connection line;

The comparator unit is used to obtain a comparator unit output signal according to a preset modulation bias voltage signal and the first pixel output signal;

The second mode selection unit is used to determine a dual-gain mode selection signal according to the output signal of the comparator unit, and transmit the dual-gain mode selection signal to the in-pixel buffer device of the corresponding pixel unit.
The image sensor according to claim 6, wherein the comparator unit is specifically used for:

When the preset modulation bias voltage signal is greater than the first pixel output signal, the comparator unit output signal is a low level output signal;

When the preset modulation bias voltage signal is less than or equal to the first pixel output signal, the comparator unit output signal is a high level output signal;

Wherein, the second mode selection unit is used to determine that the dual-gain mode selection signal is a low-gain mode selection signal according to the low-level output signal;

Alternatively, the second mode selection unit is used to determine that the dual-gain mode selection signal is a high-gain mode selection signal according to the high-level output signal.
The image sensor according to claim 1, wherein the pixel array further comprises: a signal reading module;

The N pixel units in the same column are connected to the signal reading module via a fifth connecting line;

The signal reading module is used to read the second pixel output signal of each pixel unit, and the second pixel output signal is obtained after the pixel unit performs signal gain processing according to the signal gain mode corresponding to the written dual gain mode selection signal.
A camera module, comprising the image sensor as described in any one of claims 1-8.
An electronic device comprises the camera module as claimed in claim 9.