CN205005137U - FPGA's real -time image acquisition with remove device of making an uproar and handling - Google Patents

Abstract

The utility model provides a FPGA's real -time image acquisition with remove device of making an uproar and handling, includes image sensor, FPGA control processing unit, memory, crystal oscillator circuit and display element, image sensor sends image information, image information is saved to the memory, by FPGA control processing unit gathers and reads image information to carry out filtering operation back, with the information result send to display element shows. The utility model discloses utilize the FPGA system, not only can conveniently design required hardware logic function, overprogram that moreover can the implementation system to great reduction the development degree of difficulty, shortened the R&D cycle, promoted the functioning speed of system, go to make an uproar the operation by the inside filtering of FPGA again and has improved the definition of image greatly, in addition, user's accessible display element look over in real time the plot of data like, reach real -time image acquisition's purpose.

Description

The real time image collection of FPGA and the device of denoising

Technical field

The utility model relates to image variants technical field, particularly the real time image collection of a kind of FPGA and the device of denoising.

Background technology

Image information is one of most important information of obtaining of the mankind, and IMAQ is very extensive in the application of the field such as Digital Image Processing, image recognition.The acquisition and processing of realtime graphic occupies an important position in present multimedia technology.The products such as the digital camera arrived seen in daily life, video telephone, multimedia IP phone and videoconference, core technology wherein during real time image collection.The speed of IMAQ, quality directly have influence on the whole structure of product.But picture signal, in generation, transmission and recording process, often can be subject to the interference of various noise, make the degradation of image, or lose important information, seriously have impact on the visual effect of image.

At present, along with the development of VLSI technology, increasing algorithm can realize with hardware, meanwhile, due to the specialization of production line, at the image that same environment first generates or transmits, its contaminated noise type has similitude and stability, and this also makes application-specific integrated circuit (ASIC) have very large practicality.Traditional IMAQ is based on PC software architecture, and relatively more flexible in image-processing operations, cost is low, but PC is von Neumann structure, cannot realize parallel processing, and speed is comparatively slow, cannot meet the real-time of image procossing; The image variants system of hardware structure generally adopts special integrated circuit ASIC device to realize, application-specific integrated circuit (ASIC) generally all adopts the Harvard structure with parallel processing capability, faster than the system speed of software architecture, requirement of real-time can be realized preferably.The digital signal processing chip DSP of conventional integrated circuit ASIC, it has the typical features such as volume is little, speed is fast, power consumption is little, reliability is strong, has certain parallel processing capability, and can realize some image processing algorithms.But along with people are to the raising of image effect and quality requirement, a lot of high performance DSP device all cannot realize.People urgently seek a kind of new system architecture.The feature of DSP and powerful data-handling capacity and high-speed cruising, is applicable to being applied to image processing field very much.But because its complex circuit designs, development cost are high and cannot carry out the defect of secondary development, bring inconvenience to designer.

Utility model content

Based on this, it is low that the purpose of this utility model is to provide a kind of development difficulty, the real time image collection of the FPGA that the speed of service is fast and the device of denoising.

The real time image collection of a kind of FPGA and the device of denoising, comprise imageing sensor, FPGA controlled processing unit, memory, crystal oscillating circuit and display unit, described imageing sensor sends image information, image information stores by described memory, gathered by described FPGA controlled processing unit and read the image information stored, and carry out filtering operation, after information result is sent to the display of described display unit.

Wherein, described FPGA controlled processing unit comprises initialization unit, controlling of sampling unit, memory control unit filter unit and phase-locked loop pll.Described initialization unit and described controlling of sampling unit are connected with described imageing sensor, and described controlling of sampling unit is for the image information that gathers described imageing sensor and send and single frames rest image.Described memory control unit is connected with described memory, and described memory control unit controls the state of described memory, and the data reading described memory are sent to described filter unit carry out filtering operation.

Described memory adopts DDRSDRAM as the Storage and Processing device of view data, utilizes Bank structure, improves described memory access speed.

The utility model utilizes FPGA system, user not only can design required hardware logic function easily, and the overprogram of system can be realized, thus greatly reduce development difficulty, shorten the R&D cycle, improve the speed of service of system, then carry out the process of the filtering and noise reduction of view data by the filter unit of FPGA inside, substantially increase the definition of image.In addition, user, by the information result data image after display unit real time inspection filtering operation, reaches the object of real time image collection.

Accompanying drawing explanation

Fig. 1 is the FPGA system design flow diagram of the utility model wherein embodiment.

Fig. 2 is the schematic diagram of the utility model wherein real-time image acquisition of the FPGA of an embodiment and the device of denoising.

Fig. 3 is the process schematic of the filtering in Fig. 2

Fig. 4 is that main frame in Fig. 2 is to the data flowchart filling in a byte from machine.

Fig. 5 is main frame in Fig. 2 to from the machine-readable data flowchart getting a byte.

Embodiment

For the ease of understanding the utility model, below with reference to relevant drawings, the utility model is described more fully.First-selected embodiment of the present utility model is given in accompanying drawing.But the utility model can realize in many different forms, is not limited to embodiment described herein.On the contrary, the object of these embodiments is provided to be make to disclosure of the present utility model more thoroughly comprehensively.

It should be noted that, when element is called as " being fixedly arranged on " another element, directly can there is element placed in the middle in it on another element or also.When an element is considered to " connection " another element, it can be directly connected to another element or may there is centering elements simultaneously.Term as used herein " vertical ", " level ", "left", "right" and similar statement are just for illustrative purposes.

Unless otherwise defined, all technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present utility model understand usually.The object of the term used in specification of the present utility model herein just in order to describe specific embodiment, is not intended to be restriction the utility model.Term as used herein " and/or " comprise arbitrary and all combinations of one or more relevant Listed Items.

Refer to Fig. 1, be the FPGA system design flow diagram of the utility model wherein embodiment, this system adopts top down design method, carries out division and the structural design of systemic-function.By conceptual design, systems organization is as the first step of system, design input adopts Verilog hardware description language input mode and Graphics Input method, system is described, functional simulation and on compiler, comprehensively demonstrate design input correctness after, by logic synthesis and optimization tool, generate gate level circuit net table, carry out modular functional verification, time stimulatiom is in conjunction with the fpga chip of concrete model, carry out concrete emulation to check whether logic synthesis result meets designing requirement, adaptive and file download passes through adapter, programming data is downloaded in fpga chip, thus by system converting be concrete physics realization.The utility model adopts the software test platform of Quartusii as emulation of ALAERA company exploitation.

Refer to Fig. 2, the real time image collection of a kind of FPGA and the device of denoising, comprise imageing sensor 10, memory 11, FPGA controlled processing unit 12, crystal oscillating circuit 13 and display unit 14, described imageing sensor 10 sends image information, image information stores by described memory 11, gathered and reading images information by described FPGA controlled processing unit 12, and after carrying out filtering operation, information result is sent to described display unit 14 and shows.

Wherein, described FPGA controlled processing unit 12 comprises initialization unit 121, controlling of sampling unit 122, memory control unit 123 filter unit 124 and phase-locked loop pll 125.

Described initialization unit 121 and described controlling of sampling unit 122 are connected with described imageing sensor 10, and described controlling of sampling unit 122 is for the image information that gathers described imageing sensor 10 and send and single frames rest image.Described memory control unit 123 is connected with described memory 11, and described memory control unit 123 controls the state of described memory 11, and the data reading described memory 11 is sent to described filter unit 124 and carries out filtering operation.

Further, also comprise an image conversion unit 15, for the DID obtained is transformed into rgb format view data, is convenient to described display unit 14 and carries out view data display.

Described memory 11 adopts DDRSDRAM as the Storage and Processing device of view data, utilize Bank structure, when one of them Bank is while carrying out precharge, another Bank can realize reading at once, after carrying out a read-write operation, without the need to waiting for, then directly read-write operation can be carried out to next block Bank again, carry out successively, the view data that described imageing sensor 10 is exported is stored in described memory 11 continuously, meanwhile, described FPGA controlled processing unit 12 reads data serially from described memory 11.

The filtering of described filter unit 124 is shown in Fig. 3, image f (x, y) 1 is transformed into domain space from image space, obtains F (u, v) after 2, in domain space, carry out different enhancings by different filter function H (u, v) 3 pairs of images, obtain G (u, v) 4, again the image after enhancing is transformed into image space from domain space, obtains image g (x, y) 5.

Described initialization unit 121 is realized arranging of its internal register by I2C bus, described I2C bus is made up of data wire SDA and clock SCL, when clock SCL is high level, described data wire SDA by high level to low transition, now, data start transmission; As described clock SCL by low level to high level saltus step, ED transmit.

Refer to Fig. 4, when I2C bus starts to configure described imageing sensor 10, directly can read prewired content from ROM.When carrying out write operation, first after producing a commencing signal by FPGA, send the device address number from machine, finally the answer signal of wait-receiving mode from machine, then FPGA sends the address of the destination register that will access, then receives the answer signal of replying from machine, then sends data to be written by FPGA, and the answer signal receiving since machine, the transmission of stop signal end data is finally sent by FPGA.

Refer to Fig. 5, when carrying out read operation, first producing a commencing signal by FPGA, sending the device address number from machine, wait-receiving mode is from the answer signal of machine, then FPGA sends the address of the destination register that will access, then receive from machine reply answer signal, changed into by FPGA after the answer signal of machine send restart signal, wait-receiving mode is from the answer signal of machine, finally get 8 data from machine-readable, once, then stop signal points out the end of transmission to a byte answer.

In the present embodiment, described imageing sensor 10 is MT9V032 transducer.

The device of real time image collection of the present utility model and denoising, datagraphic information is sent by described imageing sensor, image information stores by described memory, again by the collection of described FPGA controlled processing unit and the image information reading described memory, and after carrying out filtering operation, information result is sent to the display described display unit carrying out data image.

Utilize FPGA system, user not only can design required hardware logic function easily, and the overprogram of system can be realized, thus greatly reduce development difficulty, shorten the R&D cycle, improve the speed of service of system, then carry out the process of the filtering and noise reduction of view data by the filter unit of FPGA inside, substantially increase the definition of image.In addition, user, by the information result data image after display unit real time inspection filtering operation, reaches the object of real time image collection.

The above embodiment only have expressed a kind of execution mode of the present utility model, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the utility model the scope of the claims.It should be pointed out that for the person of ordinary skill of the art, without departing from the concept of the premise utility, can also make some distortion and improvement, these all belong to protection range of the present utility model.Therefore, the protection range of the utility model patent should be as the criterion with claims.

Claims (9)

1. the real time image collection of a FPGA and the device of denoising, comprise imageing sensor, FPGA controlled processing unit, memory, crystal oscillating circuit and display unit, it is characterized in that, described imageing sensor sends image information, image information stores by described memory, gathered and reading images information by described FPGA controlled processing unit, and after carrying out filtering operation, information result is sent to described display unit and shows.

2. the real time image collection of FPGA according to claim 1 and the device of denoising, is characterized in that, described FPGA controlled processing unit comprises initialization unit, controlling of sampling unit, filter unit and memory control unit.

3. the real time image collection of FPGA according to claim 2 and the device of denoising, it is characterized in that, described initialization unit and described controlling of sampling unit are connected with described imageing sensor respectively, and described controlling of sampling unit is for the image information that gathers described imageing sensor and send and single frames rest image.

4. the real time image collection of FPGA according to claim 2 and the device of denoising, it is characterized in that, described memory control unit is connected with described memory, described memory control unit controls the state of described memory, and the information data reading described memory is sent to described filter unit carries out filtering operation.

5. the real time image collection of FPGA according to claim 2 and the device of denoising, it is characterized in that, described memory adopts Bank structure, when one of them Bank is while carrying out precharge, another Bank can realize reading at once, after carrying out a read-write operation, without the need to waiting for, then directly read-write operation is carried out to next block Bank again.

6. the real time image collection of FPGA according to claim 2 and the device of denoising, it is characterized in that, described initialization unit is connected with described imageing sensor by I2C bus, and described FPGA controlled processing unit controls generation and the stopping of described I2C bus control data.

7. the real time image collection of FPGA according to claim 1 and the device of denoising, is characterized in that, also comprises an image conversion unit, for the DID obtained being transformed into the format picture data being suitable for the display of described display unit.

8. the real time image collection of the FPGA according to claim 1 to 7 any one and the device of denoising, is characterized in that, all on FPGA, utilizes Verilog language realize, build nextport hardware component NextPort.

9. the real time image collection of the FPGA according to claim 1 to 7 any one and the device of denoising, is characterized in that, adopts the software test platform of Quartusii as emulation of ALAERA company exploitation.