CN104881666B - A kind of real-time bianry image connected component labeling implementation method based on FPGA - Google Patents
A kind of real-time bianry image connected component labeling implementation method based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of real-time bianry image connected component labeling implementation method based on FPGA, belong to VLSI Design and target identification and technical field of visual measurement, it is intended to realize the real-time connected component labeling of extensive moving target by way of hardware based on FPGA.The present invention uses four symmetrical treatment nodes, using newest serial architecture for exchanging（VPX frameworks）；Each processing node includes the FPGA of XC5VX95TI 2 of XILINX companies and memory capacity is up to the DDR memory cell of 16G bits, is interconnected between node using 16 couples of 2.5GHz RocketIO；Wherein handle node first time scanning element, main controller module, correlation memory group, plain scan unit, DDR access arbitrations module, DDR controller and framing and data outputting module is formed.The present invention realizes the extensive moving target of real-time mark using super scalar pipeline and dynamic deferred pipelining, and the adaptive various resolution ratio of energy, its performance is not interfered with when moving-target shape and quantity change, strong robustness, its operation result and MATLAB bwlabel functions are completely the same.
Description
Technical field
It is especially a kind of to be based on field-programmable gate array the present invention relates to a kind of bianry image connected component labeling implementation method
Row device is realized using superscalar pipelining line technology by hardware mode and carries out connected component labeling in real time to extensive moving target
Method.Belong to VLSI Design and target identification and technical field of visual measurement.
Background technology
Bianry image connected component labeling is the Doppler frequency position of moving-target in radar system, distance is to position, phase
The resolving of the parameters such as position, amplitude, angle and speed provides important evidence, in addition the technology be also widely used for target identification,
Target acquisition, guidance, navigation and field of medical applications.
Bianry image connected component labeling is from only by " 0 "（Represent background dot）" 1 "（Represent target point）The dot matrix of composition
In image, adjacent Objective extraction is come out.The purpose is to find destination object all in image, and same mesh will be belonged to
The all pixels of mark object are marked with unique mark value.In the algorithm simulating stage, often used in MATLAB
Bwlable functions realize the function.In implementation phase, generally there is software and hardware to realize two ways.
The mode that software is realized is use high performance PC or work station, is realized with based on software approach.But
Due to the serialization feature of CPU execute instructions, when image resolution ratio, frame per second improve or moving-target quantity becomes more, a frame is handled
Time spent by image can linear increase.When being more than the frame period time between when treated, frame losing can be caused.In order to reduce processing
Delay, in general mode is that algorithm is improved, it is proposed that region growth method, depth or BFS method, line mark
The various optimized algorithms such as notation.Document " a kind of new method of bianry image connected component labeling "（Computer engineering and application,
2006；42（25）：50-51）Middle using area growth method, it is only necessary to single pass is carried out to image, improves arithmetic speed.
" a kind of new method of bianry image connected component labeling "（Computer application, 2007；27（11）：2776-2777）It is middle to use line
The method that labelling method and region growth method are combined, elementary cell of its connected component as detection, greatly reducing needs to examine
The number of survey.But the algorithm needs to search for the field of each connected component repeatedly, and work as and contain many point-like in image and erect
The algorithm performs efficiency can significantly degenerate during traditional thread binding connected region.The test result obtained by analysis software implementation, it is complete
Into the image connectivity field mark general processing time that resolution ratio is 1024x768 in hundred milliseconds of magnitudes, radar system is not reached much
In the requirement that handles in real time.
Hardware implementation mode is based on ASIC or FPGA device, and processing delay is reduced using its parallelization feature.Document
“FPGA based connected component labeling”（International Conference on
Control, Automation and Systems. Seoul, Korea, 2007：2313-2317）In describe one kind and be based on
Hardware mode realizes framework, can be with 200 two field pictures of processing per second, but maximum only supports 255 moving targets, is needing easily
To handle simultaneously in the polarization sensitive synthetic aperture radar system of thousands of moving targets does not have actual use.
The content of the invention
Present invention seek to address that image resolution ratio is up to 18432x4096, and need to handle thousands of up to ten thousand simultaneously
The technical barrier for the real-time bianry image connected component labeling that prior art can not be realized in the synthetic aperture radar of moving target.This
Invention, by hardware mode, it is big to realize real-time mark based on FPGA using superscalar pipelining line technology
Scale moving target, and the adaptive various resolution ratio of this programme energy, it is not interfered with when moving-target shape and quantity change
Performance, strong robustness, its operation result and MATLAB bwlabel functions are completely the same.
The purpose of the present invention is achieved through the following technical solutions.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, it realizes that algorithm uses four
Neighbourhood signatures' algorithm, it is exactly specifically only related to the state on its left side and the point of top to handling for certain point.It is treated
Journey uses the mode of four scanning, and for the first time using sequential system, image is handled from left to right, from top to bottom；Second
It is secondary then on the contrary using backward mode, handled from right to left, from top to bottom；Third time is handled using sequential system again；Finally
First use backward mode scan process image.Such a Processing Algorithm is relatively conventional algorithm, and its amount of calculation is relatively large, but
It is that can ensure to obtain the result consistent with bwlabel functions in the case of any shape with any quantity moving-target.This hair
The bright starting point be using it is Promethean realize framework and realize thought improve process performance, reach to high-resolution and high frame per second
The beneficial effect of view synthesis.
A kind of its hardware platform of real-time bianry image connected component labeling implementation method based on FPGA of the present invention uses four
Individual symmetrical treatment node composition, using VPX frameworks（High speed serialization architecture for exchanging）, interconnect and use HSSI High-Speed Serial Interface.Wherein four
Individual processing node 100 ~ 103 uses the high-end FPGA of XC5VX95TI-2 of XILINX companies；Memory cell 200 ~ 203 uses
Micron companies model MT47H256M8-3E 2G bit DDR2 particles, each memory cell use 16 DDR2 particles, made
The memory capacity for obtaining each processing unit is 16G bits.Interconnection between processing unit uses 16 couples of 2.5GHz Rocket
IO（The high-speed serial communication standard that XILINX is defined）, its total bandwidth is more than 1000MB/s, disclosure satisfy that in synthetic aperture radar
The requirement for the high data throughput that high-resolution is brought, there are 4 pairs of difference control lines between processing unit in addition, available for handling
The communication of control and status signal between unit.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, wherein described processing section
Point is by first time scanning element 1, main controller module 2, correlation table memory group 3, plain scan unit 4, DDR access arbitrations
Module 5, DDR controller 6 and framing and data outputting module 7 are formed.Main controller module 2 respectively with first time scanning element 1,
Correlation table memory group 3, plain scan unit 4 are connected with framing with data outputting module 7, interactive controlling and status information；
First time scanning element 1 and plain scan unit 4 are connected by the RAM access interfaces of standard with correlation table memory group 3, are write
Port is used for the content for updating correlation table, and read port is used for the value for reading correlation table；First time scanning element 1, commonly sweep
Retouch unit 4 and framing and data outputting module 7 is required for carrying out data interaction with DDR, so these three modules are all by making by oneself
The high speed access interface of justice is connected with DDR access arbitrations module 5；DDR access arbitrations module 5 is according to poll and self-defined priority
The arbitration mode being combined multiple parallel access requests to DDR map and be multiplexed with serial DDR access request with
DDR controller 6 is connected；The accessing time sequence that DDR controller 6 produces DDR according to access request directly accesses outside DDR chips；
Framing and data outputting module 7 are embedded in mark value result in frame according to frame structure to be exported.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, wherein described first time
Scanning element 1 is by serioparallel exchange module 11, initial data ping-pong buffers 12, first time scanning element processing and control module 13, mark
Note value ping-pong buffers 14 and DDR Write posts 15 are formed；Main controller module 2 is by main control state machine 21 and some auxiliary logic structures
Into；Correlation table memory group 3 is made up of access handover module 31, buffer A 32 and buffer B 33；Plain scan unit 4
It is made up of read buffer group 41, plain scan cell processing control module 42, DDR Write posts 43 and mark value ping-pong buffers 44；
DDR access arbitrations module 5 selects state machine 51, port and status register group 52 by port, reads data buffering 53 and read and write to control
State machine 54 processed is formed；DDR controller 6 is by initialization module 61, state of a control machine 62, data channel 63 and phase alignment module
64 are formed；Framing and data outputting module 7 are by read states machine 71, reading data buffering 72, framing control logic 73 and output timing
Control module 74 is formed.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, it, which is realized, includes following step
Suddenly：
1. complete the initial of bianry image according to sequential system from left to right, from top to bottom in first time scanning element
Mark, and the correlation information between mark value is written in correlation table memory group：
A. serioparallel exchange is done to the binary image data of input, is changed into the data of 8 bit widths, deposit initial data table tennis
In buffering.The data for so reading 8 picture points every time are handled, it is possible to reduce reading times；
B. determine whether target point, then do corresponding processing.There are three kinds of situations, if not being target point, then
The mark value of current location point is entered as 0；If new target point, that is, the point of its left side and top is not target
Point, then the maximum mark value that the mark value of current location point is entered as having used is added 1, and to change correlation table；
If be not new target point, it is necessary to read the mark value of adjacent pixel, be then address from correlation table using these mark values
The mark value of correlation is read in memory group, the minimum value for the mark value that the mark value of the point is entered as reading, is finally changed
Correlation table；
C. the mark value calculated needs to be stored in mark value ping-pong buffers, because needing to use one when calculating next line
Capable mark value, the mark value of lastrow is stored in internal storage primarily to improving processing speed.Also to deposit simultaneously
Enter in DDR Write posts FIFO, data volume of the Read-write Catrol logic in first time scanning element in FIFO starts DDR and write behaviour
Mark value is made to be stored in DDR；
2. the processing of first time scanning element completes initial markers and correlation table memory group to image after completing
The inside incorporates the correlation data of mark value.Now main controller module notice plain scan unit starts scanning next time
Operation, and notify the access handover module in correlation table memory group to do access switching, read-write operation afterwards is common
What scanning element was initiated；
Complete mark according to backward mode from right to left, from top to bottom when 3. plain scan unit scans for the first time
Fusion, and update the information of correlation table：
A. from DDR in mark-sense value deposit read buffer group；
B. judge mark value, if not representing that the point is target point for 0.Its processing mode and the processing of first time scanning element
It is entirely different, it is the mark value that currently processed point and the left side and the right point are read from read buffer group first, then uses this
A little mark values read the mark value of correlation as address from correlation table memory group, then compare the mark of 3 points of reading
The minimum value of note value, by the use of this minimum value as the mark value of current point and update the value in correlation table memory group；
C. in the mark value write-in DDR Write posts FIFO calculated, then it is deposited into DDR；
4. plain scan unit completes notice main controller module after scanning, main controller module renewal plain scan list
The parameter value of member opens scan operation next time；
5. repeat the operation of 3,4 steps to complete to scan four times of image twice；
Main controller module notifies the correspondence of framing and data output module from DDR after 6. all scan operations are completed
Last mark value is taken out in position, and the final data of output, last output timing control are then generated according to the form of output frame
Module produces suitable sequential and result is sent.
Compared with prior art, beneficial effects of the present invention include：
1. processing speed is fast, XILINX companies model XC5VX95TI FPGA, processing clock 100MHz condition are used
It is per second that the speed that lower maximum can be handled reaches 400M pixels, is fully able to handle bianry image in synthetic aperture radar in real time and connects
The mark in logical domain；
2. such a shape for realizing structure and moving-target and quantity are unrelated, different shapes and quantity will not reduce processing speed
Degree；
3. parametrization realizes structure, only need to change corresponding buffer when image resolution ratio and bigger frame per second
Space size, and realize logic without modification；
4. constant processing delay, convenient use is in a variety of systems.
Brief description of the drawings
Fig. 1 is hardware structure schematic diagram of the present invention
Fig. 2 is that processing node realizes configuration diagram in present system
Fig. 3 is pending Position Design figure
Fig. 4 a are that first time scanning element streamline realizes timing diagram
Fig. 4 b are the method for expressing schematic diagram of pending point, corresponding mark value and the value in correlation table
Fig. 5 is the schematic diagram of different types of pending point in first time scanning element
Fig. 6 is that plain scan unit streamline realizes timing diagram
Label declaration in figure：
100 ~ 103 processing nodes, 200 ~ 203 processing node external memory units, 1 first time scanning element, 2 master controls
Device module processed, 3 correlation table memory groups, 4 plain scan units, 5 DDR access arbitrations modules, 6 DDR controllers, 7 groups
Frame and data outputting module, 11 serioparallel exchange modules, 12 initial data ping-pong buffers, the processing control of 13 first time scanning elements
Molding block, 14 mark value ping-pong buffers, 15 DDR Write posts, 21 main control state machines, 31 access handover module, 32 buffers
A, 33 buffer B, 41 read buffer groups, 42 plain scan cell processing control modules, 43 DDR Write posts, 44 mark values
Data buffering, 54 Read-write Catrol shapes are read in ping-pong buffers, 51 ports selection state machine, 52 ports and status register group, 53
State machine, 61 initialization modules, 62 state of a control machines, 63 data channel, 64 phase alignment modules, 71 read states machines, 72
Read data buffering, 73 framing control logics, 74 output timing control modules.
Embodiment
Detailed construction, application principle, effect and effect of the present invention, referring to the drawings 1-6, said by the way that mode is implemented as follows
It is bright.
Hardware platform architecture of the present invention using four symmetrical treatment nodes as shown in figure 1, formed, using VPX frameworks, interconnection
Using HSSI High-Speed Serial Interface.Node is handled in the present invention and realizes framework as shown in Fig. 2 mainly including seven main function moulds
Block.This two parts is described in detail in the content of the invention.
System is described separately below and handles the function and specific design method of each module in node, further to the present invention
Explain, its emphasis indicates that how superscalar pipelining line technology embodies in the design, and how to improve and be
Process performance of uniting.Details, which is also set forth, to be realized to some keys in addition：
First, whole system handles node using four identicals FPGA, each FPGA in hardware composition as one, complete
Connected component labeling into a two field picture operates.Processing node 100 ~ 103 is worked by the way of order flowing water.The figure that front end enters
Picture data are a process cycle according to 4 frames, and i-th ~ i+3 two field pictures are assigned in FPGA_A ~ FPGA_D respectively, this four
Handle node to complete after scanning, then be aggregated into FPGA_D.The water operation of the first order is realized from overall realize；
2nd, two processing modules are shared by the way of two-stage pipeline processes in the realization of processing node, including the
Single pass unit 1 and plain scan unit 4, a two field picture are done in first time scanning element first after entering processing node
Processing, processing give plain scan unit after completing and do subsequent treatment, now first time scanning element start to process next frame
Image.This is the water operation of the second level；
3rd, first time scanning element 1, the initial of bianry image is completed according to sequential system from left to right, from top to bottom
Mark, and the correlation information between mark value is written in correlation table memory group.
Need to complete several behaviour when handling the point on (m, n) position as shown in Figure 3 when doing preliminary sweep mark
Make：
1）(m, n), (m, n-1), the two-value data of (m-1, n) three points are read, determines whether background dot, new mesh
Punctuate either has adjacent target point；
2）The mark value of (m, n-1) and (m-1, n) is read, is expressed as g (m, n-1) and g (m-1, n)；
3）Address mark value corresponding to reading inside correlation table is used as with mark value g (m, n-1) and g (m-1, n),
It is expressed as T (g (m, n-1)) and T (g (m-1, n))；
4）Compare T (g (m, n-1)) and T (g (m-1, n)) size, obtain its minimum value, be expressed as T0；
5）The mark value of (m, n) is assigned to T0；
6）Updating T (g (m, n))=T0, T (g (m, n-1))=T0, T (g (m, n-1)) ,=T0 is into correlation table, correlation
Table is deposited in correlation table memory group.
According to FPGA structure, six operations described above each at least need a clock cycle to handle, if
Operation all so will greatly reduce processing speed using the mode of order.In the design using streamline as shown in fig. 4 a
Mode is handled, and using 8 points as processing particle, reads 8 points simultaneously every time to handle.A ~ f in Fig. 4 a represents described above
Six operations, take target and represent respective operations that are last or handling next time；Fig. 4 b illustrate to need point to be processed,
The method for expressing of value in corresponding mark value and correlation table, T represent target point, and B represents background dot.It performs flow such as
Under：
1）In d ', e ', f, ' three clock cycle reads from initial data ping-pong buffers 12 needs 8 originals to be processed
Beginning data d (m, n) ~ d (m, n+7) and from mark value ping-pong buffers 14 read corresponding to 8 points of lastrow mark value g
(m-1,n)~g(m-1,n+7).Often handling 8 pixels only needs to read 1 time.Because there is three clock cycle, the block inside FPGA
The read latency of memory could be arranged to 2 clock cycle, and critical path optimization processing sequential in design can be reduced by so doing.
These data are just read out when the clock cycle 6 '；
2）Read in correlation table memory group 3 for address with g (m-1, n) when a and marked corresponding to g (m-1, n)
Note value T (g (m-1, n)), the delay of same reading correlation table memory group 3 could be arranged to 2 clock cycle；
3）The T (g (m-1, n)) of the point of process points top value is read out when c, and the T (g of left side point
(m, n-1)) it is that the last result handled can directly obtain, it can thus compare the two values, small value is labeled as
T0；
4）In the point that d, tri- clock cycle of e, f obtain c（M, n）Mark value be written to mark value ping-pong buffers 14
In DDR Write posts 15, and it is T0 to update address g (m, n-1) and g (m-1, n) value in correlation table memory group 3；
5）In d, tri- clock cycle renewal correlation table memory groups 3 of e, f, a of subsequent point processing is reading correlation again
Property table, add comparison mechanism avoid address conflict.
This is the water operation of the third level in design.
The emphasis of its design of first time scanning element illustrates according to the algorithm above in processing and control module, what it was handled
Pixel can be divided into 3 kinds of situations, and 1）Background dot；2）Fresh target point；3）Non- new target point.As shown in figure 5, wherein 1 is background
Point；2 be new target point, and 3,4,5 be non-new target point.Then according to whether reading the correlation table of consecutive points above
Value, is divided into several situations shown in following table again：
According to previously described three kinds of situations and whether to read the reading process point top from correlation table memory group 3 and face
The value of near point, the situation of processing are always divided into 4 kinds of situations.Including 1,2,3 and 5a, 4 and 5b.So locate in processing and control module 13
Reason state machine handles all situations using 4 kinds of different processing states.The pipeline design mode according to Fig. 4 a, often
Individual processing state continues 3 clock cycle, can so ensure there is constant processing delay.
4th, plain scan unit 4 can be scanned three times according to backward, order, the order of backward to image, complete mark
The fusion of value, while the correlation information between mark value is written in correlation table memory group.
Exemplified by the point on (m, n) position shown in Fig. 3, it, which is realized, needs to complete following operation：
1）(m, n), (m, n-1), the mark value g (m, n) of (m-1, n) three points, g (m, n-1), g (m-1, n) are read, is sentenced
Whether disconnected is background dot or target point；
2）Corresponding to being read with mark value g (m, n), g (m, n-1) and g (m-1, n) inside the correlation table as address
Mark value, it is expressed as T (g (m, n)), T (g (m, n-1)) and T (g (m-1, n))；
3）Compare T (g (m, n)), T (g (m, n-1)) and T (g (m-1, n)) size, obtain its minimum value, be expressed as
T0；
4）The mark value of (m, n) is assigned to T0；
5）T (g (m, n))=T0, T (g (m, n-1))=T0, T (g (m, n-1))=T0 is updated into correlation table.
The operation of plain scan unit only has 5 steps, but the upper difficulty of its design is bigger.Because in the 2nd above-mentioned step
Need to read value corresponding to 3 mark values from correlation table memory group, need in the 4th step to write 3 values and deposited to correlation table
In reservoir.According to the function of FPGA internal storages, a clock cycle can only carry out a read-write operation simultaneously, if do not entered
Even if row 2 and 4 parallel work-flows of processing also at least need 3 clock cycle, data compare 1 clock cycle of needs, read data
1 clock cycle is also required to write-in result parallel work-flow, this just at least needs 5 clock cycle.And plain scan needs
Perform 3 times, if the pipeline design according to the fixed delay in first time scanning element, then processing speed can be very slow.
In the present invention processing speed is improved using dynamic deferred pipelining.
The pipeline design in plain scan unit is as shown in Figure 6.From wherein A represents to read and treat from read buffer group 41
The mark value of reason, the value of correlation table to be compared is read from correlation table memory group 3；B represents to compare correlation
The mark value for being worth to currently processed point of table；C represents the mark value of currently processed point to be written to DDR Write posts and mark value
In ping-pong buffers, the content of correlation table is updated.
Retardation is big in delay of the delay equal to A+B or C delay of streamline as can be known from Fig. 6 one.It is divided into
Four kinds of situations in following table：
As can be seen from the above table, only need to deposit from correlation table when handling two adjacent target points and processing
It is 3 clock cycle that its pipelining delay during the value of correlation table is read in reservoir group, and other situations are both less than 3 clock cycle.
Because when just having individual moving-target thousands of or up to ten thousand in a two field picture at last, the quantity of target point is relative to whole image
For point and seldom, treatment effeciency has been considerably improved by above-mentioned dynamic deferred pipelining.
Processing node 100 ~ 103 in present embodiment can use FPGA（Field Programmable Gate
Array, field programmable gate array）, it is possible to use ASIC（Application-Specific Integrated Circuit,
Application specific integrated circuit）Realize.
In present embodiment trial operation, using XILINX companies model XC5VX95TI FPGA, processing clock setting is
It is per second to reach 400M pixels for the maximum speed that can be handled under conditions of 100MHz.Bianry image by the processing of the system it
Afterwards, the mark value that the mark value and MATLAB bwlabel functions obtained obtains is completely the same, illustrates to have reached Expected Results.
Above-described specific descriptions, the purpose, technical scheme and beneficial effect of invention are carried out further specifically
It is bright, it should be understood that the specific embodiment that the foregoing is only the present invention, the protection model being not intended to limit the present invention
Enclose, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., should be included in the present invention
Protection domain within.
Claims (3)
- A kind of 1. real-time bianry image connected component labeling implementation method based on FPGA, it is characterised in that：Hardware platform uses four Individual symmetrical treatment node composition, using VPX frameworks（High speed serialization architecture for exchanging）；Wherein four processing nodes 100 ~ 103 use The XC5VX95TI-2 FPGA of XILINX companies, memory cell 200 ~ 203 use 16 capacity as 2G bit DDR2 particles so that The memory capacity 32G bits of each processing unit, interconnection between processing unit using 16 couples of 2.5GHz Rocket IO, separately There are 4 pairs of difference control lines between outer processing unit, available for the control and the communication of status signal between processing unit；Node is wherein handled by first time scanning element（1）, main controller module（2）, correlation table memory group（3）, it is common Scanning element（4）, DDR access arbitration modules（5）, DDR controller（6）With framing and data outputting module（7）Form；It is connected Mode is：Main controller module（2）Respectively with first time scanning element（1）, correlation table memory group（3）, plain scan list Member（4）With framing and data outputting module（7）It is connected, interactive controlling and status information；First time scanning element（1）With commonly sweep Retouch unit（4）Pass through the RAM access interfaces and correlation table memory group of standard（3）It is connected, write port is used to update correlation The content of table, read port are used for the value for reading correlation table；First time scanning element（1）, plain scan unit（4）With framing and Data outputting module（7）It is required for carrying out data interaction with DDR, so these three modules are all connect by customized high speed access Mouth and DDR access arbitration modules（5）It is connected；DDR access arbitration modules（5）It is combined according to poll and self-defined priority secondary Sanction mode is mapped as multiple parallel access requests to DDR serial DDR access request and DDR controller（6）It is connected； DDR controller（6）The accessing time sequence that DDR is produced according to access request directly accesses outside DDR chips；Framing and data output Module（7）Mark value result is embedded in frame according to frame structure and exported；Described first time scanning element（1）By serioparallel exchange module（11）, initial data ping-pong buffers（12）, for the first time scan Cell processing control module（13）, mark value ping-pong buffers（14）With DDR Write posts（15）Form；Main controller module（2）By Main control state machine（21）Formed with some auxiliary logics；Correlation table memory group（3）By access handover module（31）, buffering Device A（32）With buffer B（33）Form；Plain scan unit（4）By read buffer group（41）, plain scan cell processing control Module（42）, DDR Write posts（43）With mark value ping-pong buffers（44）Form；DDR access arbitration modules（5）Shape is selected by port State machine（51）, port and status register group（52）, read data buffering（53）With Read-write Catrol state machine（54）Form；DDR is controlled Device processed（6）By initialization module（61）, state of a control machine（62）, data channel（63）With phase alignment module（64）Form；Group Frame and data outputting module（7）By read states machine（71）, read data buffering（72）, framing control logic（73）With output timing control Molding block（74）Form；Comprise the following steps it is characterized in that realizing：A. in first time scanning element（1）According to from left to right, from top to bottom sequential system complete bianry image it is initial Mark, and the correlation information between mark value is written to correlation table memory group（3）In：A) serioparallel exchange is done to the binary image data of input, is changed into the data of 8 bit widths, be stored in initial data ping-pong buffers （12）In so that the data for reading 8 picture points every time are handled, it is possible to reduce reading times；B) determine whether target point, then do corresponding processing, there are three kinds of situations, if not being target point, then current The mark value of location point is entered as 0；If new target point, that is, the point of its left side and top is not target point, that The maximum mark value that the mark value of current location point is entered as having used is added 1, and to change correlation table；If no It is then address from correlation table memory using these mark values for new target point, it is necessary to read the mark value of adjacent pixel Group（3）Middle to read related mark value, the minimum value for the mark value that the mark value of the point is entered as reading, finally modification is related Property table；C) the mark value deposit mark value ping-pong buffers calculated（14）With DDR Write posts FIFO（15）In, first time scanning element （1）In data volume of the Read-write Catrol logic in FIFO start DDR write operations mark value be stored in DDR；B. first time scanning element（1）Processing completes initial markers and correlation table memory group to image after completing （3）The inside incorporates the correlation data of mark value, now main controller module（2）Notify plain scan unit（4）Under starting Scan operation once, and notify correlation table memory group（3）In access handover module（31）Access switching is done, afterwards Respond plain scan unit（4）The read-write operation of initiation；C. plain scan unit（4）When scanning for the first time melting for mark is completed according to backward mode from right to left, from top to bottom Close, and update the information of correlation table：A) mark-sense value is stored in read buffer group from DDR（41）In；B) judge mark value, if not representing that the point is target point for 0, its processing mode and first time scanning element（1）Place Manage entirely different, be the mark value that currently processed point and the left side and the right point are read from read buffer group first, Ran Houyong These mark values are as address from correlation table memory group（3）It is middle to read related mark value, then compare 3 read The minimum value of the mark value of individual point, by the use of this minimum value as the mark value of current point and update correlation table memory group （3）In value；C) the mark value write-in DDR Write posts FIFO calculated（43）In, then it is deposited into DDR；D. plain scan unit（4）Complete to notify main controller module after scanning（2）, main controller module（2）Renewal is common Scanning element（4）Parameter value open scan operation next time；E. C is repeated, four scannings to image are completed in D step operations twice；F. main controller module after all scan operations are completed（2）Notify framing and data output module（7）From DDR pair Answer position to take out last mark value, the final data of output, last output timing control are then generated according to the form of output frame Molding block（74）Suitable sequential is produced to send result.
- 2. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, its feature exist In：Superscalar pipelining line technology has been used in realization, has been embodied in：A. processing node 100 ~ 103 is worked by the way of order flowing water, and the view data that front end enters is at one according to 4 frames The cycle is managed, i-th ~ i+3 two field pictures are assigned in FPGA_A ~ FPGA_D respectively, after this four processing nodes complete scanning, then FPGA_D is aggregated into, the water operation of the first order is realized from overall realize；B. in the realization of processing node by the way of two-stage pipeline processes, two processing modules are shared, including for the first time Scanning element 1 and plain scan unit 4, a two field picture, which enters to handle node and do in first time scanning element first afterwards, to be located Reason, processing give plain scan unit and do subsequent treatment after completing, now first time scanning element start to process next frame Image, this is the water operation of the second level；C. in processing procedure, completion is needed to read data, read correlation table data, compare, updating correlation to each pixel Table and five steps of data are write, this five steps are handled by pipeline mode so that the processing of each pixel at most only needs Three clock cycle, this is the water operation of the third level.
- 3. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, its feature exist In：Dynamic deferred pipelining is used in the realization of plain scan unit, it is embodied in：Handled according to the last time Processing is divided into four kinds of situations by the type and currently processed vertex type of point, only when two adjacent target points of processing and processing When need from correlation table memory group（3）It is middle read correlation table value when its pipelining delay be 3 clock cycle, other feelings Condition is both less than 3 clock cycle.
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| CN105374032B (en) * | 2015-10-14 | 2018-01-12 | 合肥安晶龙电子股份有限公司 | Method for marking connected region |
| CN105528305B (en) * | 2015-12-04 | 2018-04-13 | 北京理工大学 | A kind of short cycle storage method based on DDR2 SDRAM |
| US10572310B2 (en) | 2016-09-21 | 2020-02-25 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
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| US9996334B2 (en) | 2016-09-21 | 2018-06-12 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US10355945B2 (en) | 2016-09-21 | 2019-07-16 | International Business Machines Corporation | Service level management of a workload defined environment |
| US10417012B2 (en) | 2016-09-21 | 2019-09-17 | International Business Machines Corporation | Reprogramming a field programmable device on-demand |
| CN106780288B (en) * | 2016-12-08 | 2020-10-20 | 苏州长风航空电子有限公司 | Hardware acceleration circuit that polygon was filled |
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| CN107231535B (en) * | 2017-05-11 | 2020-02-18 | 大连理工大学 | Real-time camera of catching of space marker dynamic coordinate |
| CN107993246A (en) * | 2018-01-19 | 2018-05-04 | 歌尔科技有限公司 | Image processing equipment and connected component labeling method, system, device, storage medium |
| CN108961298A (en) * | 2018-07-25 | 2018-12-07 | 安徽师范大学 | A kind of quick connected domain detection FPGA implementation method based on linear array CCD image stream |
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| CN109597654B (en) * | 2018-12-07 | 2022-01-11 | 湖南国科微电子股份有限公司 | Register initialization method, basic configuration table generation method and embedded system |
| CN110533678B (en) * | 2019-07-26 | 2022-02-11 | 杭州电子科技大学 | Image processing method for screening feature targets based on FPGA frame parallel connected domain |
| CN112114103B (en) * | 2020-08-18 | 2021-07-20 | 华南理工大学 | Sewage plant sludge bulking detection method based on robust adaptive canonical correlation analysis |
| CN112784832B (en) * | 2021-02-09 | 2022-09-09 | 西南科技大学 | Object mark point identification method and device |
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