CN104881666A - Real-time binary image connected domain mark realizing method based on FPGA - Google Patents
Real-time binary image connected domain mark realizing method based on FPGA Download PDFInfo
- Publication number
- CN104881666A CN104881666A CN201410068052.2A CN201410068052A CN104881666A CN 104881666 A CN104881666 A CN 104881666A CN 201410068052 A CN201410068052 A CN 201410068052A CN 104881666 A CN104881666 A CN 104881666A
- Authority
- CN
- China
- Prior art keywords
- ddr
- mark value
- module
- time
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000012545 processing Methods 0.000 claims abstract description 61
- 238000009432 framing Methods 0.000 claims abstract description 17
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims description 51
- 239000000872 buffer Substances 0.000 claims description 26
- 238000002372 labelling Methods 0.000 claims description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 4
- 230000004927 fusion Effects 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000003993 interaction Effects 0.000 claims description 2
- 230000002452 interceptive effect Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 13
- 230000006870 function Effects 0.000 abstract description 8
- 238000005259 measurement Methods 0.000 abstract description 2
- 230000000007 visual effect Effects 0.000 abstract description 2
- 230000003139 buffering effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000026676 system process Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000004304 visual acuity Effects 0.000 description 1
Landscapes
- Image Processing (AREA)
- Image Analysis (AREA)
Abstract
The invention discloses a real-time binary image connected domain mark realizing method based on FPGA, which belongs to the large scale integrated circuit design, object identification and visual measurement technical field. The invention aims to achieve real-time connected domain marking of large scale moving objects on the basis of field programmable gate array devices in a hardware way. Four symmetrical processing nodes are used. A newest serial exchange architecture (VPX architecture) is adopted. Each processing node comprises XC5VX95TI-2FPGA of the XILINX corporation and a DDR memory cell of a 16G-bit storage capacity. The nodes are interconnected through 16 pairs of 2.5GHz RocketIO. Each processing node is composed of a first-time scanning unit, a main controller module, a correlation memory group, a common scanning unit, a DDR access arbitration module, a DDR controller, and a framing and data output module. Real-time marking of large scale moving objects is achieved through superscalar streamline and dynamic delay streamline technologies. Adaption to various resolutions is further realized. The performance is not affected when the moving object shape and number are changed. Strong robustness is achieved. The calculation result is completely consistent with the MATLAB bwlabel function.
Description
Technical field
The present invention relates to a kind of bianry image connected component labeling implementation method, especially one is based on FPGA by hardware mode, uses superscalar pipelining line technology to realize carrying out in real time extensive moving target the method for connected component labeling.Belong to large scale integrated circuit design and target identification and technical field of visual measurement.
Background technology
Bianry image connected component labeling in radar system for the Doppler frequency position of moving-target, distance to position, isoparametric the resolving of phase place, amplitude, angle and speed provide important evidence, this technology is also widely used in target identification, target detection, guidance, navigation and field of medical applications in addition.
Bianry image connected component labeling is from the dot matrix image be only made up of " 0 " (expression background dot) and " 1 " (expression impact point), by adjacent Objective extraction out.Its objective is and find destination objects all in image, and all pixels belonging to same destination object are marked by unique mark value.In the algorithm simulating stage, in MATLAB, often use bwlable function to realize this function.At implementation phase, software and hardware is usually had to realize two kinds of modes.
The mode of software simulating uses high performance PC or workstation, realizes with based on software approach.But because CPU performs the serialization feature of instruction, when image resolution ratio, frame per second raising or moving-target quantity become many, the time processed spent by a two field picture can linear increase.When being greater than the frame period time when treated, frame losing can be caused.In order to reduce process time delay, general mode improves algorithm, proposes region growth method, the degree of depth or the various optimized algorithm such as BFS (Breadth First Search) method, wire tag method.Document " a kind of new method of bianry image connected component labeling " (computer engineering and application, 2006; Use region growth method 42(25): 50-51), only need to carry out single pass to image, improve arithmetic speed." a kind of new method of bianry image connected component labeling " (computer utility, 2007; Use the method that wire tag method and region growth method combine 27(11): 2776-2777), its connected component, as the elementary cell detected, greatly reduces the number needing to detect.But this algorithm needs the field repeatedly searching for each connected component, and when can significantly degenerate containing this algorithm execution efficiency when a lot of point-like and vertical line dress connected region in image.By the test result that analysis software implementation obtains, complete resolution be the image connectivity field mark general processing time of 1024x768 hundred milliseconds of magnitudes, not reach in radar system the requirement of process in real time far away.
Hardware implementation mode, based on ASIC or FPGA device, utilizes its parallelization feature to reduce processing delay.Document " FPGA based connected component labeling " (International Conference on Control, Automation and Systems. Seoul, Korea, describe 2007:2313-2317) and a kind ofly realize framework based on hardware mode, can process 200 two field picture per second, but maximumly only support 255 moving targets, in the polarization sensitive synthetic aperture radar system needing simultaneously to process thousands of moving target easily, there is no actual use.
Summary of the invention
The present invention is intended to solve image resolution ratio and is up to 18432x4096, and needs to process the technical barrier of the real-time bianry image connected component labeling that prior art cannot realize in the synthetic-aperture radar of thousands of up to ten thousand moving targets simultaneously.The present invention is based on FPGA and pass through hardware mode, superscalar pipelining line technology is used to achieve the extensive moving target of real-time mark, and the various resolution of this programme energy self-adaptation, its performance can not be affected when moving-target shape and quantity change, strong robustness, the bwlabel function of its operation result and MATLAB is completely the same.
The object of the invention is to be achieved through the following technical solutions.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, its implementation algorithm uses four neighbourhood signatures algorithms, is specifically exactly only relevant to the state of the point of its left side and top to certain any process.Processing procedure uses four modes scanned, and first time uses sequential system, from left to right, from top to bottom processes image; Otherwise second time then uses backward mode, processes from right to left, from top to bottom; Third time uses sequential system process again; Last use backward mode scan process image.This kind of Processing Algorithm is more common algorithm, and its calculated amount is relatively large, but can ensure to obtain the result consistent with bwlabel function in any shape with when any quantity moving-target.The starting point of the present invention be use Promethean realize framework and realize thought improve handling property, reach the beneficial effect that high resolving power and high frame rate image are processed in real time.
A kind of real-time its hardware platform of bianry image connected component labeling implementation method based on FPGA of the present invention uses four symmetrical treatment node compositions, adopts VPX framework (high speed serialization architecture for exchanging), interconnected employing HSSI High-Speed Serial Interface.The wherein high-end FPGA of XC5VX95TI-2 of four processing node 100 ~ 103 use XILINX companies; Storage unit 200 ~ 203 employing Micron company model is the 2G bit DDR2 particle of MT47H256M8-3E, and each storage unit uses 16 DDR2 particles, makes the memory capacity of each processing unit be 16G bit.The high-speed serial communication standard of the Rocket IO(XILINX definition of the interconnected employing 16 couples of 2.5GHz between processing unit), its total bandwidth is greater than 1000MB/s, the requirement of the high data throughput that synthetic-aperture radar middle high-resolution brings can be met, also have 4 pairs of difference control lines between processing unit in addition, can be used for communicating of control between processing unit and status signal.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, wherein said processing node by first time scanning element 1, main controller module 2, correlativity table memory set 3, plain scan unit 4, DDR access arbitration module 5, DDR controller 6 and framing and data outputting module 7 form.Main controller module 2 respectively with first time scanning element 1, correlativity table memory set 3, plain scan unit 4 be connected with data outputting module 7 with framing, interactive controlling and status information; First time, scanning element 1 was connected with correlativity table memory set 3 with the RAM access interface of plain scan unit 4 by standard, and write port is used for the content of update dependence table, and read port is for reading the value of correlativity table; Scanning element 1, plain scan unit 4 and framing and data outputting module 7 all need to carry out data interaction with DDR, so these three modules are all connected with DDR access arbitration module 5 by self-defining high speed access interface for the first time; The arbitration mode that DDR access arbitration module 5 combines according to poll and self-defined priority is multiple parallel being connected with DDR controller 6 to the request of access that the request of access mapping and multiplexing of DDR is the DDR of serial; The accessing time sequence that DDR controller 6 produces DDR according to request of access directly accesses outside DDR chip; Framing and data outputting module 7 export in mark value result embedding frame according to frame structure.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, wherein said first time scanning element 1 by serioparallel exchange module 11, raw data ping-pong buffers 12, first time scanning element processing and control module 13, mark value ping-pong buffers 14 and DDR Write post 15 form; Main controller module 2 is made up of main control state machine 21 and some auxiliary logics; Correlativity table memory set 3 is made up of access handover module 31, impact damper A 32 and impact damper B 33; Plain scan unit 4 is made up of read buffer group 41, plain scan cell processing control module 42, DDR Write post 43 and mark value ping-pong buffers 44; DDR access arbitration module 5 is made up of port selection mode machine 51, port and status register group 52, read data buffering 53 and Read-write Catrol state machine 54; DDR controller 6 is made up of initialization module 61, state of a control machine 62, data channel 63 and phase alignment module 64; Framing and data outputting module 7 are made up of read states machine 71, read data buffering 72, framing steering logic 73 and output timing control module 74.
A kind of real-time bianry image connected component labeling implementation method based on FPGA of the present invention, its realization comprises the steps:
1. in first time scanning element, complete the initial markers of bianry image according to sequential system from left to right, from top to bottom, and the correlation information between mark value be written in correlativity table memory set:
A. serioparallel exchange is done to the binary image data of input, become the data of 8 bit widths, stored in raw data ping-pong buffers.The data of so each reading 8 picture point process, and can reduce reading times;
B. determine whether impact point, then do corresponding process.Having three kinds of situations, if be not impact point, is so 0 the mark value assignment of current location point; If be new impact point, namely the point of its left side and top is not impact point, is so that the maximum mark value used adds 1 the mark value assignment of current location point, and will revises correlativity table; If be not new impact point, need the mark value reading neighbor, then with these mark value for address reads relevant mark value from correlativity table memory set, be the minimum value of mark value read the mark value assignment of this point, finally revise correlativity table;
C. the mark value that calculates needs stored in mark value ping-pong buffers because need the mark value using lastrow when calculating next line, the mark value of lastrow stored in internal storage mainly in order to improve processing speed.Simultaneously also will stored in DDR Write post FIFO, the Read-write Catrol logic for the first time in scanning element starts DDR write operation mark value stored in DDR according to the data volume in FIFO;
2. first time scanning element process completes initial markers to image after completing and incorporates the correlation data of mark value inside correlativity table memory set.Now main controller module notice plain scan unit starts scan operation next time, and notifies that the access handover module in correlativity table memory set does access switching, and read-write operation is afterwards that plain scan unit is initiated;
3. the fusion of mark when the first time scanning of plain scan unit, is completed according to backward mode from right to left, from top to bottom, and the information of update dependence table:
A. from DDR mark-sense value stored in read buffer group;
B. judge mark value, if not being this point of 0 expression is impact point.Its processing mode is completely different with first time scanning element process, first be the mark value reading current process points and the left side and the right point from read buffer group, then from correlativity table memory set, relevant mark value is read as address by these mark value, then the minimum value of the mark value of 3 points of reading is compared, by this minimum value as the mark value of current point and the value in update dependence table memory set;
C., in the mark value write DDR Write post FIFO calculated, be then deposited in DDR;
4. plain scan unit notifies main controller module after completing scanning, and main controller module upgrades the parameter value unlatching scan operation next time of plain scan unit;
5. repeat 3,4 step operations and complete scanning for four times image for twice;
6. after all scan operations complete, main controller module notice framing and data outputting module take out last mark value from the correspondence position of DDR, then generate according to the form of output frame the final data exported, last output timing control module produces suitable sequential and result is sent.
Compared with prior art, beneficial effect of the present invention comprises:
1. processing speed is fast, use the FPGA that XILINX company model is XC5VX95TI, under the condition of processing clock 100MHz, to reach 400M pixel per second for the maximum speed that can process, and can process the mark of bianry image connected domain in synthetic-aperture radar completely in real time;
2. this kind realizes the shape of structure and moving-target and quantity has nothing to do, and different shapes and quantity can not reduce processing speed;
3. parameterizedly realize structure, when image resolution ratio and frame per second larger time only need to revise corresponding buffer space size, and need not revise and realize logic;
4. constant process time delay, easy to use in various different system.
Accompanying drawing explanation
Fig. 1 is hardware structure schematic diagram of the present invention
Fig. 2 is that in present system, processing node realizes configuration diagram
Fig. 3 is pending some Position Design figure
Fig. 4 a is that scanning element streamline realizes sequential chart for the first time
Fig. 4 b is the method for expressing schematic diagram of the value in pending point, corresponding mark value and correlativity table
Fig. 5 is the schematic diagram of pending point dissimilar in first time scanning element
Fig. 6 is that plain scan unit stream waterline realizes sequential chart
Number in the figure illustrates:
100 ~ 103 processing nodes, 200 ~ 203 processing node external memory units, 1 first time scanning element, 2 main controller modules, 3 correlativity table memory set, 4 plain scan unit, 5 DDR access arbitration modules, 6 DDR controllers, 7 framings and data outputting module, 11 serioparallel exchange modules, 12 raw data ping-pong buffers, 13 first time scanning element processing and control module, 14 mark value ping-pong buffers, 15 DDR Write post, 21 main control state machines, 31 access handover modules, 32 impact damper A, 33 impact damper B, 41 read buffer groups, 42 plain scan cell processing control modules, 43 DDR Write post, 44 mark value ping-pong buffers, 51 port selection mode machines, 52 ports and status register group, 53 read data bufferings, 54 Read-write Catrol state machines, 61 initialization modules, 62 state of a control machines, 63 data channel, 64 phase alignment modules, 71 read states machines, 72 read data bufferings, 73 framing steering logics, 74 output timing control modules.
Embodiment
Detailed construction of the present invention, application principle, effect and effect, with reference to accompanying drawing 1-6, be explained by following embodiment.
Hardware platform architecture of the present invention as shown in Figure 1, uses four symmetrical treatment node compositions, adopts VPX framework, interconnected employing HSSI High-Speed Serial Interface.In the present invention, processing node realizes framework as shown in Figure 2, mainly comprises seven main functional modules.These two parts are described in detail in summary of the invention.
The respectively function of each module and specific design method in descriptive system and processing node below, make an explanation to the present invention further, its emphasis is to illustrate how superscalar pipelining line technology embodies in the design, and how to improve system handling property.In addition the details that realizes of some keys is also set forth:
One, the whole system FPGA that use four is identical on hardware is formed, each FPGA are as a processing node, complete the connected component labeling operation of a two field picture.The mode of processing node 100 ~ 103 employing order flowing water works.The view data that front end enters is a treatment cycle according to 4 frames, and i-th ~ i+3 two field picture is assigned in FPGA_A ~ FPGA_D respectively, after these four processing nodes complete scanning, then is aggregated into FPGA_D.From the water operation totally achieving the first order;
Two, in the realization of processing node, adopt the mode of two-stage pipeline processes, have two processing modules, comprise scanning element 1 and plain scan unit 4 for the first time, first one two field picture processes after entering processing node in first time scanning element, give plain scan unit after having processed and do subsequent treatment, now scanning element starts the image processing next frame for the first time.This is the water operation of the second level;
Three, first time scanning element 1, complete the initial markers of bianry image according to sequential system from left to right, from top to bottom, and the correlation information between mark value be written in correlativity table memory set.
Several operation has been needed when processing the point on (m, n) position as shown in Figure 3 when doing preliminary sweep mark:
1) read the two-value data of (m, n), (m, n-1), (m-1, n) three points, determine whether background dot, new impact point or have adjacent impact point;
2) read the mark value of (m, n-1) and (m-1, n), be expressed as g (m, n-1) and g (m-1, n);
3) inside correlativity table, read corresponding mark value using mark value g (m, n-1) and g (m-1, n) as address, be expressed as T (g (m, n-1)) and T (g (m-1, n));
4) compare the size of T (g (m, n-1)) and T (g (m-1, n)), obtain its minimum value, be expressed as T0;
5) mark value of (m, n) is composed as T0;
6) upgrade T (g (m, n))=T0, T (g (m, n-1))=T0, T (g (m, n-1))=T0 in correlativity table, correlativity table is deposited in correlativity table memory set.
According to the structure of FPGA, above-described six operations are each at least needs a clock period to process, if the mode operating all uses order so will reduce processing speed greatly.Use pipeline system process as shown in fig. 4 a in the design, using 8 points as process particle, read 8 points at every turn simultaneously and process.A ~ f in Fig. 4 a represents six operations recited above, brings target to represent respective operations that is last or that next time process; Fig. 4 b describes the method for expressing of the value needed in point to be processed, corresponding mark value and correlativity table, and T represents impact point, and B represents background dot.It is as follows that it performs flow process:
1) at d ', e ', three clock period of f ' read and need 8 raw data d (m to be processed from raw data ping-pong buffers 12, n) ~ d (m, and from mark value ping-pong buffers 14, read the mark value g (m-1 of corresponding lastrow 8 points n+7), n) ~ g (m-1, n+7).Often process 8 pixels only to need to read 1 time.Because there are three clock period, the read latency of the block storage of FPGA inside can be set to 2 clock period, does like this and can reduce critical path optimization process sequential in design.When the clock period 6 ', these data have just been read out;
2) when a with g (m-1, n) for address reads g (m-1 in correlativity table memory set 3, n) corresponding mark value T (g (m-1, n)), the same delay of reading correlativity table memory set 3 can be set to 2 clock period;
3) T (g (m-1 of the point of process points top when c, n) value) has been read out, and the T of left side point (g (m, n-1) be) that the last result processed can directly obtain, so just can compare this two values, little value is labeled as T0;
4) at the point (m that d, e, f tri-clock period obtain c, n) mark value is written in mark value ping-pong buffers 14 and DDR Write post 15, and the value of address g (m, n-1) and g (m-1, n) is T0 in update dependence table memory set 3;
5) when d, e, f tri-clock period update dependence table memory set 3, a of lower some process is reading correlativity table again, adds comparison mechanism and avoids address conflict.
This is the water operation of the third level in design.
The emphasis of first time its design of scanning element is in processing and control module, and according to above-mentioned algorithmic descriptions, the pixel of its process can be divided into 3 kinds of situations, 1) background dot; 2) fresh target point; 3) non-new impact point.As shown in Figure 5,1 be wherein background dot; 2 is new impact point, and 3,4,5 is non-new impact point.Then according to the need of the value of correlativity table reading consecutive point above, several situation shown in following table is divided into again:
According to previously described three kinds of situations and the value whether will reading reading process point top point of proximity from correlativity table memory set 3, the situation of process is always divided into 4 kinds of situations.Comprise 1,2,3 and 5a, 4 and 5b.So processing state machine uses 4 kinds of different treatment states to process all situations in processing and control module 13.The pipeline design mode according to Fig. 4 a, each treatment state continues 3 clock period, can ensure constant processing delay like this.
Four, plain scan unit 4 according to backward, sequentially, the order of backward carries out three scanning to image, can complete the fusion of mark value, the correlation information between mark value is written in correlativity table memory set simultaneously.
Be example with the point on (m, the n) position shown in Fig. 3, it realizes needs and completes following operation:
1) read (m, n), (m, n-1), the mark value g (m, n) of (m-1, n) three points, g (m, n-1), g (m-1, n), determine whether background dot or impact point;
2) with mark value g (m, n), g (m, and g (m-1 n-1), n) inside correlativity table, corresponding mark value is read as address, be expressed as T (g (m, n)), T (g (m, n-1)) and T (g (m-1, n));
3) compare the size of T (g (m, n)), T (g (m, n-1)) and T (g (m-1, n)), obtain its minimum value, be expressed as T0;
4) mark value of (m, n) is composed as T0;
5) T (g (m, n))=T0, T (g (m, n-1))=T0, T (g (m, n-1))=T0 is upgraded in correlativity table.
The operation of plain scan unit only has 5 steps, but the upper difficulty of its design is larger.Because need in the 2nd above-mentioned step to read value corresponding to 3 mark value from correlativity table memory set, need in the 4th step to write 3 values in correlativity table storer.According to the function of FPGA internal storage, a clock period can only carry out a read-write operation simultaneously, even if if do not carry out processing 2 and 4 parallel work-flows at least need 3 clock period yet, data compare 1 clock period of needs, read data and write result parallel work-flow and also need 1 clock period, this just at least needs 5 clock period.And plain scan needs execution 3 times, if according to the pipeline design of the fixed delay in first time scanning element, so processing speed can be slowly.
Use dynamic deferred pipelining to improve processing speed in the present invention.
The pipeline design in plain scan unit as shown in Figure 6.Wherein A represents read pending mark value from read buffer group 41, reads the value of correlativity table to be compared from correlativity table memory set 3; B represents that the value comparing correlativity table obtains the mark value of current process points; C represents the mark value of current process points is written in DDR Write post and mark value ping-pong buffers, the content of update dependence table.
The delay of streamline equals large one of retardation in the delay of A+B or the delay of C as can be known from Fig. 6.Be divided into four kinds of situations in following table:
As can be seen from the above table, when needing when only having when the adjacent impact point of process two and process to read the value of correlativity table from correlativity table memory set, its pipelining delay is 3 clock period, and other situations are all less than 3 clock period.Because when just having thousands of or up to ten thousand moving-targets at last in a two field picture, the quantity of impact point is also little relative to the point of whole image, just substantially increases treatment effeciency by above-mentioned dynamic deferred pipelining.
Processing node 100 ~ 103 in present embodiment can adopt FPGA(Field Programmable Gate Array, field programmable gate array), also ASIC(Application-Specific Integrated Circuit can be used, special IC) realize.
In present embodiment trial run, use the FPGA that XILINX company model is XC5VX95TI, processing clock under being set to the condition of 100MHz the maximum speed that can process to reach 400M pixel per second.After the process of bianry image by native system, the mark value that the bwlabel function of the mark value obtained and MATLAB obtains is completely the same, illustrates and reaches Expected Results.
Above-described specific descriptions; the object of inventing, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. based on a real-time bianry image connected component labeling implementation method of FPGA, it is characterized in that: hardware platform uses four symmetrical treatment node compositions, adopts VPX framework (high speed serialization architecture for exchanging); The wherein XC5VX95TI-2 FPGA of four processing node 100 ~ 103 use XILINX companies; Storage unit 200 ~ 203 adopts 16 capacity to be 2G bit DDR2 particle, makes the memory capacity 32G bit of each processing unit; The Rocket IO of the interconnected employing 16 couples of 2.5GHz between processing unit, also has 4 pairs of difference control lines between processing unit in addition, can be used for communicating of control between processing unit and status signal; Wherein processing node is made up of first time scanning element (1), main controller module (2), correlativity table memory set (3), plain scan unit (4), DDR access arbitration module (5), DDR controller (6) and framing and data outputting module (7); Main controller module (2) is connected with data outputting module (7) with framing with first time scanning element (1), correlativity table memory set (3), plain scan unit (4) respectively, interactive controlling and status information; First time scanning element (1) is connected with correlativity table memory set (3) with the RAM access interface of plain scan unit (4) by standard, and write port is used for the content of update dependence table, and read port is for reading the value of correlativity table; First time scanning element (1), plain scan unit (4) and framing and data outputting module (7) all need to carry out data interaction with DDR, so these three modules are all connected with DDR access arbitration module (5) by self-defining high speed access interface; The arbitration mode that DDR access arbitration module (5) combines according to poll and self-defined priority parallel to be connected with DDR controller (6) to the request of access that the request of access of DDR is mapped as the DDR of serial multiple; The accessing time sequence that DDR controller (6) produces DDR according to request of access directly accesses outside DDR chip; Framing and data outputting module (7) export in mark value result embedding frame according to frame structure.
2. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, is characterized in that: described first time scanning element (1) is made up of serioparallel exchange module (11), raw data ping-pong buffers (12), first time scanning element processing and control module (13), mark value ping-pong buffers (14) and DDR Write post (15); Main controller module (2) is made up of main control state machine (21) and some auxiliary logics; Correlativity table memory set (3) is by access handover module (31), impact damper A(32) and impact damper B(33) form; Plain scan unit (4) is made up of read buffer group (41), plain scan cell processing control module (42), DDR Write post (43) and mark value ping-pong buffers (44); DDR access arbitration module (5) cushions (53) by port selection mode machine (51), port and status register group (52), read data and Read-write Catrol state machine (54) is formed; DDR controller (6) is made up of initialization module (61), state of a control machine (62), data channel (63) and phase alignment module (64); Framing and data outputting module (7) cushion (72), framing steering logic (73) and output timing control module (74) by read states machine (71), read data and form.
3. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, is characterized in that realization comprises the steps:
A. in first time scanning element (1), complete the initial markers of bianry image according to sequential system from left to right, from top to bottom, and the correlation information between mark value is written in correlativity table memory set (3);
a)serioparallel exchange is done to the binary image data of input, becomes the data of 8 bit widths, inner stored in raw data ping-pong buffers (12), the data at every turn reading 8 picture point are processed, can reading times be reduced;
B) determine whether impact point, then do corresponding process; Having three kinds of situations, if be not impact point, is so 0 the mark value assignment of current location point; If be new impact point, namely the point of its left side and top is not impact point, is so that the maximum mark value used adds 1 the mark value assignment of current location point, and will revises correlativity table; If be not new impact point, need the mark value reading neighbor, then with the mark value that these mark value are relevant for address reads from correlativity table memory set (3), be the minimum value of the mark value read the mark value assignment of this point, finally revise correlativity table;
C) mark value calculated is stored in mark value ping-pong buffers (14) and DDR Write post FIFO(15) in, the Read-write Catrol logic in first time scanning element (1) starts DDR write operation mark value stored in DDR according to the data volume in FIFO;
After first time scanning element (1) process initial markers completed to image and inside correlativity table memory set (3), incorporate the correlation data of mark value; Now main controller module (2) notice plain scan unit (4) starts scan operation next time, and notify that the inner access handover module (31) of correlativity table memory set (3) does access and switches, respond the read-write operation that plain scan unit (4) is initiated afterwards;
C. the fusion of mark is completed during plain scan unit (4) first time scanning according to backward mode from right to left, from top to bottom, and the information of update dependence table;
a)from DDR, mark-sense value is stored in read buffer group (41);
B) judge mark value, if not being this point of 0 expression is impact point; The process of its processing mode and first time scanning element (1) is completely different, first be the mark value reading current process points and the left side and the right point from read buffer group, then from correlativity table memory set (3), relevant mark value is read by these mark value as address, then the minimum value of mark value obtaining 3 points read is compared, by this minimum value as the mark value of current point and the value in update dependence table memory set (3);
C) the mark value write DDR Write post FIFO(43 calculated) in, be then deposited in DDR;
d.plain scan unit (4) notifies main controller module (2) after completing scanning, and main controller module (2) upgrades the parameter value unlatching scan operation next time of plain scan unit (4);
E. repeat C, D walks operation and completes scanning for four times image for twice;
F. after all scan operations complete, main controller module (2) notice framing and data outputting module (7) take out last mark value from the correspondence position of DDR, then generate according to the form of output frame the final data exported, last output timing control module (74) produces suitable sequential and result is sent.
4. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, is characterized in that: realization employs superscalar pipelining line technology, be embodied in:
A. the mode of processing node 100 ~ 103 employing order flowing water works; The view data that front end enters is a treatment cycle according to 4 frames, and i-th ~ i+3 two field picture is assigned in FPGA_A ~ FPGA_D respectively, after these four processing nodes complete scanning, then is aggregated into FPGA_D; From the water operation totally achieving the first order;
B. in the realization of processing node, adopt the mode of two-stage pipeline processes, have two processing modules, comprise scanning element 1 and plain scan unit 4 for the first time, first one two field picture processes after entering processing node in first time scanning element, give plain scan unit after having processed and do subsequent treatment, now scanning element starts the image processing next frame for the first time; This is the water operation of the second level;
C. in processing procedure, read data needed to each pixel, has read correlativity table data, compared, update dependence table and write data five steps, this five steps, by pipeline mode process, makes the process of each pixel at most only need three clock period; This is the water operation of the third level.
5. a kind of real-time bianry image connected component labeling implementation method based on FPGA as claimed in claim 1, is characterized in that: in the realization of plain scan unit, use dynamic deferred pipelining; It is embodied in: according to the type of last process points and current process points type, process is divided into four kinds of situations, when needing when only having when the adjacent impact point of process two and process to read the value of correlativity table from correlativity table memory set (3), its pipelining delay is 3 clock period, and other situations are all less than 3 clock period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410068052.2A CN104881666B (en) | 2014-02-27 | 2014-02-27 | A kind of real-time bianry image connected component labeling implementation method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410068052.2A CN104881666B (en) | 2014-02-27 | 2014-02-27 | A kind of real-time bianry image connected component labeling implementation method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104881666A true CN104881666A (en) | 2015-09-02 |
| CN104881666B CN104881666B (en) | 2018-01-16 |
Family
ID=53949153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410068052.2A Active CN104881666B (en) | 2014-02-27 | 2014-02-27 | A kind of real-time bianry image connected component labeling implementation method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104881666B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261049A (en) * | 2015-09-15 | 2016-01-20 | 重庆飞洲光电技术研究院 | Quick detection method of image connection area |
| CN105374032A (en) * | 2015-10-14 | 2016-03-02 | 合肥安晶龙电子股份有限公司 | Communicated region marking method |
| CN105528305A (en) * | 2015-12-04 | 2016-04-27 | 北京理工大学 | DDR2 SDRAM-based short cycle storage method |
| CN106780288A (en) * | 2016-12-08 | 2017-05-31 | 苏州长风航空电子有限公司 | A kind of hardware-accelerated circuit of polygon filling |
| CN107038736A (en) * | 2017-03-17 | 2017-08-11 | 腾讯科技（深圳）有限公司 | A kind of animated show method and terminal device based on frame per second |
| CN107231535A (en) * | 2017-05-11 | 2017-10-03 | 大连理工大学 | A kind of space indicate thing dynamic coordinate real-time capture camera |
| CN107993246A (en) * | 2018-01-19 | 2018-05-04 | 歌尔科技有限公司 | Image processing equipment and connected component labeling method, system, device, storage medium |
| US9996334B2 (en) | 2016-09-21 | 2018-06-12 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| CN108961298A (en) * | 2018-07-25 | 2018-12-07 | 安徽师范大学 | A kind of quick connected domain detection FPGA implementation method based on linear array CCD image stream |
| CN109146804A (en) * | 2018-07-26 | 2019-01-04 | 南京航空航天大学 | A kind of SAR image correction method for geometric distortion based on FPGA |
| CN109597654A (en) * | 2018-12-07 | 2019-04-09 | 湖南国科微电子股份有限公司 | Initialization of register method, the generation method and embedded system of configurations table |
| US10355945B2 (en) | 2016-09-21 | 2019-07-16 | International Business Machines Corporation | Service level management of a workload defined environment |
| US10417012B2 (en) | 2016-09-21 | 2019-09-17 | International Business Machines Corporation | Reprogramming a field programmable device on-demand |
| CN110533678A (en) * | 2019-07-26 | 2019-12-03 | 杭州电子科技大学 | Image processing method based on the parallel connected domain screening characteristic target of FPGA frame |
| US10572310B2 (en) | 2016-09-21 | 2020-02-25 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US10599479B2 (en) | 2016-09-21 | 2020-03-24 | International Business Machines Corporation | Resource sharing management of a field programmable device |
| CN112114103A (en) * | 2020-08-18 | 2020-12-22 | 华南理工大学 | Sewage plant sludge bulking detection method based on robust adaptive canonical correlation analysis |
| CN112784832A (en) * | 2021-02-09 | 2021-05-11 | 西南科技大学 | Object mark point identification method and device |
| CN113377049A (en) * | 2021-06-11 | 2021-09-10 | 西安应用光学研究所 | DDR control method based on FPGA low-delay video image cache |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103548A (en) * | 2011-02-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
| US20110200254A1 (en) * | 2010-02-16 | 2011-08-18 | Seiko Epson Corporation | Image processing device, image processing method, and computer program |
| CN102193865A (en) * | 2010-03-16 | 2011-09-21 | 联想(北京)有限公司 | Storage system, storage method and terminal using same |
| US20110302356A1 (en) * | 2010-06-07 | 2011-12-08 | Xilinx, Inc. | Scalable memory interface system |
| CN102339261A (en) * | 2011-09-16 | 2012-02-01 | 上海智翔信息科技股份有限公司 | DDR (Double Data Rate) 2 SDRAM (Synchronous Dynamic Random Access Memory) controller |
| CN103019779A (en) * | 2012-11-30 | 2013-04-03 | 北京遥测技术研究所 | Program updating method for FPGA (Field Programmable Gate Array)/DSP (Digital Signal Processor) embedded system |
-
2014
- 2014-02-27 CN CN201410068052.2A patent/CN104881666B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110200254A1 (en) * | 2010-02-16 | 2011-08-18 | Seiko Epson Corporation | Image processing device, image processing method, and computer program |
| CN102193865A (en) * | 2010-03-16 | 2011-09-21 | 联想(北京)有限公司 | Storage system, storage method and terminal using same |
| US20110302356A1 (en) * | 2010-06-07 | 2011-12-08 | Xilinx, Inc. | Scalable memory interface system |
| CN102103548A (en) * | 2011-02-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
| CN102339261A (en) * | 2011-09-16 | 2012-02-01 | 上海智翔信息科技股份有限公司 | DDR (Double Data Rate) 2 SDRAM (Synchronous Dynamic Random Access Memory) controller |
| CN103019779A (en) * | 2012-11-30 | 2013-04-03 | 北京遥测技术研究所 | Program updating method for FPGA (Field Programmable Gate Array)/DSP (Digital Signal Processor) embedded system |
Non-Patent Citations (1)
| Title |
|---|
| 汪滴珠 等: "基于FPGA的二值图像连通域快速标记", 《现代电子技术》 * |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261049A (en) * | 2015-09-15 | 2016-01-20 | 重庆飞洲光电技术研究院 | Quick detection method of image connection area |
| CN105261049B (en) * | 2015-09-15 | 2017-09-22 | 重庆飞洲光电技术研究院 | A kind of image connectivity region quick determination method |
| CN105374032B (en) * | 2015-10-14 | 2018-01-12 | 合肥安晶龙电子股份有限公司 | Method for marking connected region |
| CN105374032A (en) * | 2015-10-14 | 2016-03-02 | 合肥安晶龙电子股份有限公司 | Communicated region marking method |
| CN105528305A (en) * | 2015-12-04 | 2016-04-27 | 北京理工大学 | DDR2 SDRAM-based short cycle storage method |
| CN105528305B (en) * | 2015-12-04 | 2018-04-13 | 北京理工大学 | A kind of short cycle storage method based on DDR2 SDRAM |
| US10355945B2 (en) | 2016-09-21 | 2019-07-16 | International Business Machines Corporation | Service level management of a workload defined environment |
| US11095530B2 (en) | 2016-09-21 | 2021-08-17 | International Business Machines Corporation | Service level management of a workload defined environment |
| US10599479B2 (en) | 2016-09-21 | 2020-03-24 | International Business Machines Corporation | Resource sharing management of a field programmable device |
| US10572310B2 (en) | 2016-09-21 | 2020-02-25 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US9996334B2 (en) | 2016-09-21 | 2018-06-12 | International Business Machines Corporation | Deploying and utilizing a software library and corresponding field programmable device binary |
| US11061693B2 (en) | 2016-09-21 | 2021-07-13 | International Business Machines Corporation | Reprogramming a field programmable device on-demand |
| US10417012B2 (en) | 2016-09-21 | 2019-09-17 | International Business Machines Corporation | Reprogramming a field programmable device on-demand |
| CN106780288B (en) * | 2016-12-08 | 2020-10-20 | 苏州长风航空电子有限公司 | Hardware acceleration circuit that polygon was filled |
| CN106780288A (en) * | 2016-12-08 | 2017-05-31 | 苏州长风航空电子有限公司 | A kind of hardware-accelerated circuit of polygon filling |
| CN107038736A (en) * | 2017-03-17 | 2017-08-11 | 腾讯科技（深圳）有限公司 | A kind of animated show method and terminal device based on frame per second |
| CN107231535A (en) * | 2017-05-11 | 2017-10-03 | 大连理工大学 | A kind of space indicate thing dynamic coordinate real-time capture camera |
| CN107231535B (en) * | 2017-05-11 | 2020-02-18 | 大连理工大学 | Real-time camera of catching of space marker dynamic coordinate |
| CN107993246A (en) * | 2018-01-19 | 2018-05-04 | 歌尔科技有限公司 | Image processing equipment and connected component labeling method, system, device, storage medium |
| CN108961298A (en) * | 2018-07-25 | 2018-12-07 | 安徽师范大学 | A kind of quick connected domain detection FPGA implementation method based on linear array CCD image stream |
| CN109146804A (en) * | 2018-07-26 | 2019-01-04 | 南京航空航天大学 | A kind of SAR image correction method for geometric distortion based on FPGA |
| CN109597654A (en) * | 2018-12-07 | 2019-04-09 | 湖南国科微电子股份有限公司 | Initialization of register method, the generation method and embedded system of configurations table |
| CN109597654B (en) * | 2018-12-07 | 2022-01-11 | 湖南国科微电子股份有限公司 | Register initialization method, basic configuration table generation method and embedded system |
| CN110533678A (en) * | 2019-07-26 | 2019-12-03 | 杭州电子科技大学 | Image processing method based on the parallel connected domain screening characteristic target of FPGA frame |
| CN110533678B (en) * | 2019-07-26 | 2022-02-11 | 杭州电子科技大学 | Image processing method for screening feature targets based on FPGA frame parallel connected domain |
| CN112114103A (en) * | 2020-08-18 | 2020-12-22 | 华南理工大学 | Sewage plant sludge bulking detection method based on robust adaptive canonical correlation analysis |
| CN112114103B (en) * | 2020-08-18 | 2021-07-20 | 华南理工大学 | Sewage plant sludge bulking detection method based on robust adaptive canonical correlation analysis |
| CN112784832A (en) * | 2021-02-09 | 2021-05-11 | 西南科技大学 | Object mark point identification method and device |
| CN113377049A (en) * | 2021-06-11 | 2021-09-10 | 西安应用光学研究所 | DDR control method based on FPGA low-delay video image cache |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104881666B (en) | 2018-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104881666A (en) | Real-time binary image connected domain mark realizing method based on FPGA | |
| CN106683158B (en) | Modeling system of GPU texture mapping non-blocking storage Cache | |
| CN107577623A (en) | Cross clock domain asynchronous fifo and data processing method | |
| CN108388527B (en) | Direct memory access engine and method thereof | |
| CN110637461B (en) | Compact optical flow handling in computer vision systems | |
| CN106846255B (en) | Image rotation realization method and device | |
| CN205608814U (en) | Augmented reality system based on zynq software and hardware concurrent processing | |
| US20060161720A1 (en) | Image data transmission method and system with DMAC | |
| Kowalczyk et al. | Real-time implementation of contextual image processing operations for 4K video stream in Zynq ultrascale+ MPSoC | |
| CN103605497B (en) | A kind of bianry image connected component labeling method for quickly identifying | |
| US11668750B2 (en) | Performing testing utilizing staggered clocks | |
| CN103760525A (en) | Completion type in-place matrix transposition method | |
| CN104915213A (en) | Partial reconfiguration controller of reconfigurable system | |
| CN111583094A (en) | Image pulse coding method and system based on FPGA | |
| CN114359662B (en) | Implementation method of convolutional neural network based on heterogeneous FPGA and fusion multi-resolution | |
| US20220113944A1 (en) | Arithmetic processing device | |
| CN102340668A (en) | Reconfigurable technology-based implementation method of MPEG2 (Moving Pictures Experts Group 2) luminance interpolation | |
| Liang et al. | The design of objects bounding boxes non-maximum suppression and visualization module based on FPGA | |
| CN103389413A (en) | Real-time statistical method for frequency spectrum histogram | |
| Seo et al. | A new parallel hardware architecture for high-performance stereo matching calculation | |
| US11836188B2 (en) | Devices and methods for accessing and retrieving data in a graph | |
| CN111814675A (en) | Convolutional neural network characteristic diagram assembling system based on FPGA supporting dynamic resolution | |
| US10665280B2 (en) | Information processing apparatus and semiconductor integrated circuit device | |
| Wong et al. | Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory | |
| CN204537238U (en) | A kind of single SRAM based on FPGA realizes the circuit of table tennis algorithm |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190702 Address after: 610000 Chunfeng Road, Jinquan Street, Jinniu District, Chengdu City, Sichuan Province Patentee after: Chengdu Jingyao Communication Technology Co., Ltd. Address before: 610000 Taisheng Building 2205, 61 Da'an East Road, Qingyang District, Chengdu City, Sichuan Province Patentee before: Wang Lei |
|
| TR01 | Transfer of patent right |