CN106780288A - A kind of hardware-accelerated circuit of polygon filling - Google Patents
A kind of hardware-accelerated circuit of polygon filling Download PDFInfo
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- CN106780288A CN106780288A CN201611125211.3A CN201611125211A CN106780288A CN 106780288 A CN106780288 A CN 106780288A CN 201611125211 A CN201611125211 A CN 201611125211A CN 106780288 A CN106780288 A CN 106780288A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
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Abstract
The invention belongs to figure generation technology field, it is related to a kind of hardware-accelerated circuit of polygon filling.The polygon fills hardware-accelerated circuit includes that DSP, FPGA PLDs, the first frame are deposited and the second frame memory device.Wherein, FPGA PLDs include controller of frame storage, flag data register, color data register, state machine, tfi module.Controller of frame storage is deposited with DSP, the first frame, the second frame is deposited, tfi module, state machine, flag data register, color data register are connected；Tfi module, flag data register and color data register are also connected with state machine simultaneously.Polygon of the present invention is filled hardware-accelerated circuit and can significantly improve polygon charging efficiency, software algorithm burden is reduced, so as to improve entire picture formation efficiency.
Description
Technical field
The invention belongs to figure generation technology field, it is related to the hardware-accelerated implementation method and electricity of a kind of polygon filling
Road.
Background technology
Polygon filling is an important research content of computer graphics, and its function is will to be given on indicator screen
All pixels unit in polygonal closed section is all modified as the color data specified.Existing polygon filling algorithm is general
Software algorithm method is taken to realize, such as seed fill algorithm, Scanning-line Filling algorithm, side mark filling algorithm.Its feature is all
It is to be calculated all pixels color data in the polygonal region for needing filling and write frame by software to deposit.
With the development of technology, the resolution ratio more and more higher of liquid crystal display, the polygon filling demand being related to is more next
It is more, it is necessary to display image content also become increasingly complex, this to polygon filling circuit propose requirement higher.And it is current
Existing software algorithm realizes that polygon fill method has following defect：Algorithm is complicated, polygon charging efficiency is low, it is full to be difficult to
Sufficient high-resolution and real-time application demand.
The content of the invention
The purpose of the present invention：Offer one kind is easily achieved, scalability is strong, the filling of efficiency high, hard-wired polygon
Circuit.
In order to adapt to the trend that airborne cockpit liquid crystal display develops to high-resolution, picture complexity high, propose it is a kind of,
High-performance, the polygon filling implementation easily realized, using DSP 1 and FPGA PLDs 2
As Main Processor Unit part, the two the first frame is deposited 8 and second frame deposit 9 and carry out ping-pong operation, by DSP 1
By the label information of Polygonal Boundary to be filled and colouring information write the first frame deposit 8 or second frame deposit 9, be may be programmed by FPGA
Logical device 2 according to scanning sequency pointwise read line by line the first frame deposit 8 or second frame deposit element marking in 9 and color is believed
Breath, state transition process is carried out by state machine 5 to label information, while process color data, and by the face after treatment
Chromatic number according to by controller of frame storage 3 write the first frame deposit 8 or second frame deposit 9, realize that polygonal hardware is filled with this.
Technical scheme：A kind of hardware-accelerated circuit of polygon filling, the circuit includes：DSP numeral letters
Number processor 1, FPGA PLDs 2, the first frame deposit 8 and second frame deposit 9；
FPGA PLDs 2 include controller of frame storage 3, tfi module 4, state machine 5, flag data register 6,
Color data register 7；
Wherein, controller of frame storage 3 deposits the 8, second frame and deposits 9, tfi module with DSP 1, the first frame respectively
4th, state machine 5, flag data register 6, color data register 7 are connected；
Tfi module 4, flag data register 6, color data register 7 are also connected with state machine 5 respectively simultaneously；
Pixel data is write the first frame and deposits 8 or second frame by the DSP 1 by controller of frame storage 3
9 are deposited, the data of write-in are the integrated datas for containing pixel color information and label information；
Described DSP 1 and described FPGA PLDs 2 are via controller of frame storage 3 pairs
First frame deposit 8 and second frame deposit 9 and take ping-pong operation mode, and the field sync signal sent with tfi module 4 is as the cycle enters
Row alternately switches；
Described 2 pairs of the first frames of FPGA PLDs deposit 8 or second frame deposit 9 operations during, according to screen scanning
Sequentially, carry out pointwise to pixel data to process line by line, the treatment to the pixel data in each address includes reading and writes
Two kinds of operations, and completed inside and outside a pixel clock period；
Described FPGA PLDs 2 the first frame is deposited 8 or second frame deposit 9 each address location operation
It is carried out in two steps, the first step is read operation, the pixel color data during frame is deposited reads display；Second step is write operation,
Deposited in same frame and write on address treated color data information；
Described FPGA PLDs 2 read the first frame deposit 8 or second frame deposit the pixel data in 9 when, it is right
The colouring information included in the pixel data of reading carries out deposit treatment by color data register 7, to the label information for reading
Deposit treatment is carried out by flag data register 6；
Described flag data register 6 sends to state machine 5 element marking information, and color data register 7 is by picture
Plain colouring information is sent to state machine 5, by state machine 5 according to a upper flag state and current markers status information and laststate
The state of carrying out transfer processing, while the pixel color information after treatment is delivered into controller of frame storage 3, writing the first frame by it deposits 8
Or second frame deposit 9.
Beneficial effects of the present invention：Polygon of the present invention fills hardware-accelerated circuit with the He of DSP 1
FPGA complex programmables device 2 is deposited as main process chip using the flag data inside FPGA PLDs 1
Device 6 and color data register 7 DSP 2 is inserted in advance the first frame deposit 8 or second frame deposit 9 polygon edge
Boundary's element marking signal and color signal carry out deposit treatment, are shifted by the mark of state machine 5 pairs and colouring information state of marking
With color data treatment, and the color after treatment on corresponding polygonal internal area filling.This programme is realized using hardware
Polygonal region is filled, and scheme is simple and easy to apply, and hardware implementation efficiency is high, reduces the complexity of software algorithm, improves polygon
The efficiency that the efficiency and figure of shape filling are produced and shown.This polygon fills hardware-accelerated circuit can meet various irregular many
The pixel filling demand of side shape, and multiple polygonal fillings can be completed in a width picture.
Brief description of the drawings
Fig. 1 is the theory diagram that polygon of the present invention fills hardware-accelerated circuit；
Wherein, 1-DSP digital signal processors, 2-FPGA PLDs, 3- controller of frame storage, 4- sequential moulds
Block, 5- state machines, 6- flag datas register, 7- color data register, the frames of 8- first are deposited, the frames of 9- second are deposited.
Specific embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
A kind of hardware-accelerated circuit of polygon filling, the circuit includes：DSP 1, FPGA can be compiled
Journey logical device 2, the first frame deposit 8 and second frame deposit 9；
FPGA PLDs 2 include controller of frame storage 3, tfi module 4, state machine 5, flag data register 6,
Color data register 7；
Wherein, controller of frame storage 3 deposits the 8, second frame and deposits 9, tfi module with DSP 1, the first frame respectively
4th, state machine 5, flag data register 6, color data register 7 are connected；
Tfi module 4, flag data register 6, color data register 7 are also connected with state machine 5 respectively simultaneously.
Described DSP 1, for carrying out drawing algorithm computing, obtains the pixel count of Polygonal Boundary
According to and address date, pixel data is the integrated data for containing label information and colouring information, and wherein label information is two
Binary data, there is three kinds of states, respectively filling-tag, end mark, empty mark；Colouring information is the colouring component numbers of RGB tri-
According to.Along picture scanning direction, the Polygonal Boundary pixel at filling will be started and put upper filling-tag, will terminated polygon at filling
Shape boundary pixel puts end mark, and remaining is not required to filling position pixel and puts overhead mark.
Described controller of frame storage 3, for receiving DSP 1 and FPGA PLDs 2 to frame
The access request of memory device, the first frame is deposited 8 and second frame deposit 9 access and carried out in ping-pong operation mode, and with tfi module 4
The field sync signal of generation carries out alternately switching for the cycle, and a certain field duration accesses one of them when DSP 1
When frame is deposited, FPGA PLDs 2 access another frame and deposit, and next field duration DSP 1 accesses previous
The frame that field FPGA was operated is deposited, and FPGA PLDs 2 access the frame that previous field DSP 1 was operated
Deposit.The pixel address signal and pixel data signal that DSP 1 obtains computing are write by controller of frame storage 3
Enter a certain frame to deposit, next field, the mark that middle DSP 1 writes is deposited by 2 pairs of frames of FPGA PLDs
Data and color data are filled acceleration treatment.
Described FPGA PLDs 2, according to scanning sequency pointwise the first frame is deposited line by line 8 or second frame deposit
9 are written and read operation.The clock frequency that the access frame of FPGA PLDs 2 is deposited is carried out by tfi module 4 to pixel clock
Frequency multiplication is produced, and is the twice of pixel clock frequency.2 pairs of the first frames of FPGA PLDs deposit 8 or second frame deposit 9 in each
The pixel data operation of address location is divided into two steps, and first step is read operation, corresponding to the first of the address location
Individual frame deposits the operating clock cycle, DSP 1 is write into the pixel data reading display that frame is deposited, while to pixel
Label information and colouring information in data do deposit treatment respectively, and label information is deposited by flag data register 6, number of colours
Deposited according to by color data register 7；Second step is write operation, and second frame corresponding to the address location deposits operation
Clock cycle, according to state machine 5 to flag data and the result of color data, corresponding color data is written back into currently
The frame of operation deposits address location.
Described state machine 5, comprising three kinds of states, respectively current pixel output state, occupied state, end filling shape
State, the pixel data after correspondingly output is processed under every kind of state.The original state of state machine 5 is current pixel output state,
According to the label information that flag data register 6 sends, state transfer processing is carried out by the cycle of pixel clock.When state machine 5
During in current pixel output state, if the element marking for receiving is empty mark, it is defeated that state machine is maintained at current pixel
Do well, FPGA PLDs 2 read the pixel color information of current address, and address location is deposited in the frame and be written back into
Full zero data is emptied；If the element marking for receiving is filling-tag, state machine 5 is converted to occupied state, FPGA
PLD 2 while the pixel color information of current address is read, by color data deposit, and by the color
Write back data enters present frame and deposits address location.When state machine 5 is in occupied state, if the element marking for receiving is empty mark
Remember, then state machine is maintained at occupied state, the number of colours of the deposit of the output color data of FPGA PLDs 2 register 7
According to, and the color data is written back into present frame deposits address location；If the element marking for receiving is end mark, state machine
5 are transformed into end occupied state, the color data of the deposit of the output color data of FPGA PLDs 2 register 7, and
The frame deposits address location and is written back into full zero data and emptied.When state machine 5 is to terminate occupied state, if the picture for receiving
Element mark is mark, and state machine 5 is transformed into current pixel output state, and FPGA PLDs 2 read current address
Pixel color information, and deposit address location and be written back into full zero data in the frame and emptied.
The hardware-accelerated circuit of polygon filling of the present invention proposes that one kind is easily realized, scalability is strong, efficiency in sum
Polygon filling hardware implementations high, using DSP 1 and FPGA PLDs 2 as master
Want processing apparatus, the two the first frame is deposited 8 and second frame deposit 9 and carry out ping-pong operation, will be waited to fill out by DSP 2
The label information and colouring information of the Polygonal Boundary filled write the first frame deposit 8 or second frame deposit 9, by FPGA programmable logic devices
Part 2 reads element marking and colouring information during frame is deposited according to scanning sequency pointwise line by line, by state machine 5 according to label information
State transition process is carried out, while being processed color data and the color data after treatment being write by controller of frame storage 3
First frame deposit 8 or second frame deposit 9, realize that polygonal hardware is filled with this.
Described DSP 1, during implementation, can select the DSP devices of AD companies or TI companies.It is described
FPGA PLDs 2, during implementation, can select any Series FPGA of altera corp or Xilinx companies.
After selected PLD, controller of frame storage 3, flag data register 6, color data register 7, tfi module 4, shape
State machine 5 can also be realized by VHDL or Verilog hardware description language programming realizations using pattern input mode.Described
One frame deposit 8 and second frame deposit 9, can select conventional random static or dynamic memory.
Claims (1)
1. the hardware-accelerated circuit that a kind of polygon is filled, it is characterised in that the circuit includes：DSP
(1), FPGA PLDs (2), the first frame deposit (8) and the second frame is deposited (9)；
FPGA PLDs (2) include controller of frame storage (3), tfi module (4), state machine (5), flag data deposit
Device (6), color data register (7)；
Wherein, controller of frame storage (3) deposits (8), the second frame and deposits (9), sequential with DSP (1), the first frame respectively
Module (4), state machine (5), flag data register (6), color data register (7) are connected；
Tfi module (4), flag data register (6), color data register (7) with state machine (5) while be also connected respectively；
Pixel data is write the first frame and deposits (8) or second by the DSP (1) by controller of frame storage (3)
Frame is deposited (9), and the data of write-in are the integrated datas for containing pixel color information and label information；
Described DSP (1) and described FPGA PLDs (2) are via controller of frame storage (3)
(8) are deposited to the first frame and the second frame deposits (9) and takes ping-pong operation mode, and the field sync signal sent with tfi module (4)
For the cycle carries out alternately switching；
Described FPGA PLDs (2) deposit (8) to the first frame or the second frame is deposited during (9) operate, and are swept according to screen
Order is retouched, pointwise is carried out to pixel data and is processed line by line, the treatment to the pixel data in each address includes reading and writing
Enter two kinds of operations, and completed inside and outside a pixel clock period；
Described FPGA PLDs (2) are depositing (8) to the first frame or the second frame deposits each address location behaviour of (9)
It is carried out in two steps, the first step is read operation, the pixel color data during frame is deposited reads display；Second step is grasped for write-in
Make, deposited in same frame and write on address treated color data information；
Described FPGA PLDs (2) deposit (8) or during pixel data during the second frame deposits (9) reading the first frame,
Colouring information to being included in the pixel data of reading carries out deposit treatment by color data register (7), to the mark for reading
Information carries out deposit treatment by flag data register (6)；
Described flag data register (6) sends to state machine (5) element marking information, and color data register (7) will
Pixel color information is sent to state machine (5), by state machine (5) according to a upper flag state and current markers status information and upper
One state carries out state transfer processing, while the pixel color information after treatment is delivered into controller of frame storage (3), by its write-in the
One frame deposits (8) or the second frame is deposited (9).
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| CN201611125211.3A CN106780288B (en) | 2016-12-08 | 2016-12-08 | Hardware acceleration circuit that polygon was filled |
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| CN201611125211.3A CN106780288B (en) | 2016-12-08 | 2016-12-08 | Hardware acceleration circuit that polygon was filled |
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| CN106780288B CN106780288B (en) | 2020-10-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112272122A (en) * | 2020-10-14 | 2021-01-26 | 北京中科网威信息技术有限公司 | FPGA accelerator card detection method and device and readable storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101505413A (en) * | 2009-02-16 | 2009-08-12 | 中国科学院长春光学精密机械与物理研究所 | Intelligent image compression apparatus combined with television tracking device |
| CN102184515A (en) * | 2011-04-13 | 2011-09-14 | 合肥芯硕半导体有限公司 | Method for filling ladder diagram in FPGA (Field Programmable Gate Array) |
| CN104363383A (en) * | 2014-10-16 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Image pre-distortion correction method and device |
| CN104506786A (en) * | 2014-12-02 | 2015-04-08 | 苏州长风航空电子有限公司 | Character generator based on synchronous dynamic random access memory (SDRAM) frame buffer |
| CN104881666A (en) * | 2014-02-27 | 2015-09-02 | 王磊 | Real-time binary image connected domain mark realizing method based on FPGA |
| CN105763878A (en) * | 2014-12-14 | 2016-07-13 | 陕西三元金泰实业发展有限公司 | Picture processing device |
-
2016
- 2016-12-08 CN CN201611125211.3A patent/CN106780288B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101505413A (en) * | 2009-02-16 | 2009-08-12 | 中国科学院长春光学精密机械与物理研究所 | Intelligent image compression apparatus combined with television tracking device |
| CN102184515A (en) * | 2011-04-13 | 2011-09-14 | 合肥芯硕半导体有限公司 | Method for filling ladder diagram in FPGA (Field Programmable Gate Array) |
| CN104881666A (en) * | 2014-02-27 | 2015-09-02 | 王磊 | Real-time binary image connected domain mark realizing method based on FPGA |
| CN104363383A (en) * | 2014-10-16 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Image pre-distortion correction method and device |
| CN104506786A (en) * | 2014-12-02 | 2015-04-08 | 苏州长风航空电子有限公司 | Character generator based on synchronous dynamic random access memory (SDRAM) frame buffer |
| CN105763878A (en) * | 2014-12-14 | 2016-07-13 | 陕西三元金泰实业发展有限公司 | Picture processing device |
Non-Patent Citations (6)
| Title |
|---|
| 曹峰，高伟林: "飞机座舱图形生成系统的硬件加速设计", 《电子技术应用》 * |
| 朱耀东, 张焕春, 经亚枝: "FPGA在飞行仪表字符图形产生器设计中的应用", 《数据采集与处理》 * |
| 李孟华，牛文生，裴静静: "DSP + FPGA结构的嵌入式图形处理设计", 《航空计算技术》 * |
| 李开宇，张焕春，经亚枝: "用FPGA 实现机载全姿态指示仪图形硬件填充", 《计算机辅助设计与图形学学报》 * |
| 贾银亮: "基于FPGA+DSP的飞机座舱综合图形显示技术研究", 《中国博士学位论文全文数据库信息科技辑》 * |
| 高伟林，曹峰，郭超: "基于双处理器系统的图形生成电路研究与应用", 《电子技术应用》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112272122A (en) * | 2020-10-14 | 2021-01-26 | 北京中科网威信息技术有限公司 | FPGA accelerator card detection method and device and readable storage medium |
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