CN104506786B

CN104506786B - A kind of character generator deposited based on SDRAM frames

Info

Publication number: CN104506786B
Application number: CN201410714039.XA
Authority: CN
Inventors: 高伟林; 曹峰; 郭超
Original assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Current assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Priority date: 2014-12-02
Filing date: 2014-12-02
Publication date: 2017-07-14
Anticipated expiration: 2034-12-02
Also published as: CN104506786A

Abstract

The invention belongs to figure generation technology field, it is related to a kind of character generator based on synchronous dynamic random access memory SDRAM, including connected digital processing unit and PLD and two frame memory devices.Wherein digital processing unit includes the first controller of frame storage, and PLD includes switch module, the second controller of frame storage, frame control crosslinking module, the first buffering device, the second buffering device, mark processing module.Wherein switch module is connected with the first controller of frame storage, the second controller of frame storage, the first frame memory device, the second frame memory device；Frame control crosslinking module is connected with the second controller of frame storage；First buffer is connected with the second controller of frame storage；Mark processing module and the second buffering device and the second controller of frame storage connect into loop.Application invention character generator：Hardware circuit scale can be significantly decreased, the reliability and frame for improving circuit deposit operation rate, and support that high graphics is produced.

Description

A kind of character generator deposited based on SDRAM frames

Technical field

The invention belongs to figure generation technology field, it is related to a kind of based on synchronous dynamic random access memory SDRAM's Character generator.

Background technology

Character generator is a supporting important component of liquid crystal display, is formed by a variety of digital circuit combination of devices, Major function is according to mapping instruction, makees graph parameter, data, with various digital processing technologies, and generation graphic character is drawn in real time Face data, are shown with liquid crystal display.Existing character generator typically uses Digital processing device DSP, FPGA Device FPGA and random access storage device SRAM are as main processing block, and digital processing unit operation mapping algorithm program is responsible for Graphic character data are generated, PLD assists to complete the generation of complex figure character data as coprocessor, with Machine accesses memory to be used to keep in figure character data as frame memory device.

With the development of technology, the resolution ratio more and more higher of liquid crystal display, it is necessary to the image content of display also increasingly Complexity, the requirement more and more higher to character graphics generation technology.There is following defect in current existing character generator：It is difficult to full , often there is picture and show not smooth enough, circuit frame storing module is excessively huge, realizes in sufficient high-resolution and real-time application demand Efficiency is low, very flexible, many limitations such as reliability is low, applicating maintenance is difficult.When graphics resolution is improved to 1600 × 1200 When, at present due to there is the limitation of speed and capacity in conventional frame memory device SRAM, it is difficult to meet application requirement.

The content of the invention

The purpose of the present invention aims to provide a kind of simple hardware configuration, strong adaptability, reliability height, can support high-resolution The character generator of liquid crystal display.

In order to adapt to the trend that airborne cockpit liquid crystal display develops to giant-screen high-resolution, to existing technical scheme It is improved, using synchronous dynamic random access memory SDRAM device as frame memory device, substantially reduces the rule of frame storing module Mould, is written and read control to SDRAM device, and coordinate generation display data in real time with DSP using PLD.

Technical scheme：A kind of character generator deposited based on SDRAM frames, including connected digital processing unit and PLD, it is characterised in that：The PLD, which is connected, is provided with the first frame memory device and the second frame storage Part, the digital processing unit is provided with the first controller of frame storage, and PLD deposits control provided with switch module, the second frame Device, frame control crosslinking module, the first buffering device, the second buffering device, mark processing module, wherein switch module are deposited with the first frame Controller, the second controller of frame storage, the first frame memory device, the second frame memory device, which are connected, controls switching；Frame control is crosslinked module and the Two controller of frame storage are connected；First buffer is connected with the second controller of frame storage；Mark processing module and the second buffering device Loop, the first buffering device output character image are connected into the second controller of frame storage.

Further, two pictures of the first frame memory device display corresponding with a data cell of the second frame memory device Element.

Further, second controller of frame storage is deposited to frame takes two kinds of burst operation patterns, corresponding burst Peration data length is respectively 512 address locations and 288 address locations.

Further, first buffering device and the second buffering device cache device using first in first out, and second delays The read-write clock and frame memory device for rushing device use same operating clock.

Further, the switch module is alternative logical device.

Using beneficial effects of the present invention：Graphic operation result is write SDRAM by the character generator together with label information Frame is deposited, and programmable device FPGA assists to complete three kinds of write-back behaviour such as pixel clearing, filling, upset as DSP coprocessor Make, hardware circuit scale can be significantly decreased, improve the operation rate that frame is deposited, and support 1600 × 1200 high resolution graphics Shape is produced.Pixel write back is realized using pipelining, is further increased the reliability of circuit, is met liquid crystal display 1600 × 1200 resolution pictures show demand in real time.

Brief description of the drawings

Fig. 1 is the theory diagram of character generator of the present invention.

Embodiment

Just accompanying drawing in conjunction with the embodiments below, the embodiment to the present invention is described in further detail, so that of the invention Technical scheme is more readily understood, grasped.

Referring to Fig. 1, it is the theory diagram of character generator of the present invention.The character generator includes connected numeral Processor 1 and PLD 2, also including two the first frame memory devices 3 being connected with PLD 2 and Two frame memory devices 4.Wherein, the digital processing unit 1 includes the first controller of frame storage 8, and PLD 2 includes switching molding Block 10, the second controller of frame storage 9, frame control crosslinking module 11, the first buffering device 5, the second buffering device 6, mark processing module 7.Wherein, the controller of frame storage 8 of switch module 10 and first, the second controller of frame storage 9, the first frame memory device 3, the second frame memory device 4 are connected；Frame control crosslinking module 11 is connected with the second controller of frame storage 9；First buffer 5 is connected with the second controller of frame storage 9；Mark The note buffer 6 of processing module 7 and second and the second controller of frame storage 9 connect into loop.

The first frame memory device and second frame memory device a line include 512 address locations, an address location storage Liquid crystal display along two contiguous pixels on scanning direction, can effective reduction flag module processing speed, to improve word Accord with the reliability of generator.In present embodiment, liquid crystal display a line 1600 pixel datas of correspondence are needed during SDRAM frames deposit 800 address location storages.Second controller of frame storage is deposited to SDRAM frames using two kinds of burst operation patterns, corresponding Data length is respectively 512 address locations and 288 address locations.By 1600 pixel datas of a line and SDRAM in program In two row address units correspondence, wherein preceding 1024 pixel datas of 512 address locations of the first row correspondence, 288 before the second row 576 pixel datas after individual address location correspondence, rear 224 address locations are given up.So need 2400 rows to deposit a frame altogether to draw Face data.

For data line, burst reading need to be completed and two steps are write in burst, need to be carried out in two times per secondary burst reading and writing, 512 data burst operations, second of completion, 288 data burst operations are completed for the first time.Need to complete altogether in one line period Four secondary bursts are operated, and preceding is respectively 512 burst read operations and 288 burst read operations twice；It is respectively that behaviour is write in 512 bursts twice afterwards Make and 288 burst write operations.Burst operation enabling signal sys_ADSn, read-write control signal sys_ are produced by frame control crosslinking module R_Wn, burst-length marking signal sys_BLS, using the top layer control signal as the second controller of frame storage.Sys_ADSn signals For ' 0 ' when notify the second controller of frame storage start initiate a burst operation；Sys_R_Wn notifies that the second frame deposits control when being ' 0 ' This time burst operation is write operation to device, is that this time burst operation is read operation to ' 1 ' interval scale；Sys_BLS be ' 0 ' interval scale this time Burst operation is 512 address location data bursts, is that this time burst operation is 288 address location data bursts to ' 1 ' interval scale.

Digital signal processor will need the picture data shown to be deposited together with label information write-in SDRAM frames.The mark Processing module is handled by label information the color data that middle reading is deposited from SDRAM frames, and mark processing is grasped according to streamline Carried out as mode, streamline is divided into the three phases such as mark and color deposit, mark processing, write-back generation：Mark and face The color deposit stage deposits to label information and pixel color value.Processing stage is marked to judge label information, according to The rule pre-established differently carries out write-back to different mark combinations, and write-back mode mainly has three classes：One class is Clearing mode, the data of write-back are 0；Another kind of is filling mode, and the data of write-back are the color value of deposit；3rd class is upset Mode, the data of write-back are to do another color value formed after bit arithmetic to the color value of deposit.Write-back generation phase The pixel data of write-back needed for sending out.

First buffering device and the second buffering device cache device using first in first out, are adopted by PLD Generated with internal resource, and the second buffer and frame memory device use same operating clock, to ensure frame memory device burst operation The integrality and correctness of write-in data in period.Data for depositing middle reading from SDRAM frames, are copied at two-way Reason, leads up to the first buffer and carries out clock zone conversion and send out display, be stored in the after mark processing resume module all the way In two buffers, when being filled with 800 data in the second buffer（1600 pixel datas of correspondence）Afterwards, start to initiate prominent immediately Write operation is sent out, the write back data in the second buffer is entered in SDRAM.

During character generator real work of the present invention, the first controller of frame storage and the second controller of frame storage are in switch module Alternately control is carried out with ping-pong to the first frame memory device and the second frame memory device under control, generated with switch module inside SET signals are that switching mark substitutes operating rights, and when SET is ' 0 ', the first controller of frame storage is grasped to the first frame memory device Make, the second controller of frame storage is operated to the second frame memory device；When SET is ' 1 ', the first controller of frame storage is deposited to the second frame Device is operated, and the second controller of frame storage is operated to the first frame memory device.

Character generator of the present invention deposits graphic operation result together with label information write-in SDRAM frames in summary, can compile Journey device FPGA assists to complete three kinds of write back operations such as pixel clearing, filling, upset as DSP coprocessor, can be notable Ground reduces hardware circuit scale, improves the operation rate that frame is deposited, and support that 1600 × 1200 high graphics are produced.And Pixel write back is realized using pipelining, is further increased the reliability of circuit, is met liquid crystal display 1600 × 1200 Resolution picture shows demand in real time.

In addition to the implementation, the present invention can also have other embodiment.All use equivalent or equivalent transformation shape Into technical scheme, all fall within scope of the present invention.

Claims

1. a kind of character generator deposited based on SDRAM frames, including connected digital processing unit and PLD, it is special Levy and be：The PLD, which is connected, is provided with the first frame memory device and the second frame memory device, and the digital processing unit is set There is the first controller of frame storage, PLD is provided with switch module, the second controller of frame storage, frame control crosslinking module, first Buffering device, the second buffering device, mark processing module, wherein switch module and the first controller of frame storage, the second frame deposit control Device, the first frame memory device, the second frame memory device, which are connected, controls switching；Frame control crosslinking module is connected with the second controller of frame storage；The One buffer is connected with the second controller of frame storage；Mark processing module and the second buffering device are connected with the second controller of frame storage Into loop, the first buffering device output character image,

The frame control crosslinking module is used to produce burst operation enabling signal sys_ADSn, read-write control signal sys_R_Wn, dashed forward Length mark signal sys_BLS is sent out, using the top layer control signal as the second controller of frame storage,

The mark processing module is used to handle the color data for depositing middle reading from SDRAM frames by label information.

2. the character generator deposited according to claim 1 based on SDRAM frames, it is characterised in that：First frame memory device and Two pixels of the data cell correspondence display of two frame memory devices.

3. the character generator deposited according to any one of claim 1 to 2 based on SDRAM frames, it is characterised in that：Described second Controller of frame storage deposits two kinds of burst operation patterns of taking to frame, and corresponding burst operation data length is respectively 512 addresses Unit and 288 address locations.

4. the character generator deposited according to claim 1 based on SDRAM frames, it is characterised in that：First buffering device Device is cached using first in first out with the second buffering device, and the read-write clock and frame memory device of the second buffer use same behaviour Make clock.

5. the character generator deposited according to claim 1 based on SDRAM frames, it is characterised in that：The switch module is two Select a logical device.