JPH01114990A - Texture mapping device - Google Patents

Abstract

PURPOSE:To rapidly execute texture mapping processing as a whole by temporarily storing information on a source vector read out of a source information holding means and writing the information in any one of blocks through a duplicated buffer memory. CONSTITUTION:Address information is successively changed in synchronism with successively supplied structural plane coordinate information and information on the source vector 48 read out correspondingly to the structural plane coordinates is temporarily stored in a holding means 43. The source information is read out of the means 43 in the order of storage in synchronism with the display plane coordinate forming operation on a display vector 49 corresponding to the vector 48 and supplied to an object information holding means 41. The holding means 41 is constituted of block memories 410-413, double buffer memories 450-453 are correspondingly connected to the block memories 410-413, timing control means 460-463 input the display plane coordinate information, decode the lower digit of the information and generate picture element information writing control signals through the double buffer memories to supply source information. In said constitution, mapping graphic information of high quality can be sufficiently rapidly displayed without stopping the operation of a linear interpolation calculator 43.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a texture mapping device, and more specifically, the present invention relates to a texture mapping device, and more specifically, the present invention relates to a texture mapping device. It is an object of the present invention to provide a novel texture mapping device that can read pixel data on a source vector and write pixel data on a destination vector.

<Prior Art> Conventionally, by projecting a desired area of figure data, such as figure data input in advance by an image input device or figure data drawn by a figure drawing device, onto the surface of a desired three-dimensional figure, There is a strong demand for designing designs, checking image effects, etc., and in order to satisfy these demands, texture mapping devices that project and display a desired two-dimensional figure onto a desired three-dimensional figure have been provided. There is.

Conventionally available texture mapping devices decompose a two-dimensional texture original into line segments in the scan line direction, and perform inverse projection transformation for each pixel while scanning in the scan line direction on the display surface. ([About texture mapping (1)
)'' Takeshi Shibamoto, Makoto Kobayashi Collected Lectures, Information Processing Society of Japan, September 9, 1985) was provided.

<Problems to be Solved by the Invention> In the configuration described above, since it is necessary to perform matrix calculation on a pixel-by-pixel basis, there are problems in that the processing speed is slow and extra memory is required. In addition, depending on the combination of the unit polygons that make up the texture original image and the unit polygons that make up the figure on the display surface, accurate mapping may not be possible, and the quality of the figure data displayed on the display surface may be affected. There is also the problem that this results in a decrease in

In order to solve these problems, the inventor of the present invention linearly interpolated the two opposing sides of the unit polygonal area on the display side, and linearly interpolated the two opposing sides of the unit polygonal area on the texture side. Interpolation is performed, and line segment interpolation calculations determined based on the above-mentioned linear interpolation data are performed in synchronization with each other. Data is read from the mapping memory based on the address data obtained by the line segment interpolation calculation on the texture side, and the display plane is read out. We have devised a texture mapping device that does not require extra memory and can display high-quality mapping figure data at high speed by supplying data to the texture mapper.

However, even with this texture mapping device, a sufficient increase in speed could not be achieved, and further improvements were needed.

To explain in more detail: - In order to draw vectors pointing in arbitrary directions (hereinafter referred to as random vectors) in a graphic display device at high speed, image memory (hereinafter referred to as frame memory) is required.
It is necessary to make the capacity larger than that required for actual display. For example, in the case where only 1280x1024 pixels are displayed, there are 256 pits in the dynamic random access memory (hereinafter referred to as D
Sufficient memory space can be achieved by using five RAMs (abbreviated as RAM), but each DR
Since the bit width for each AM is 4, a total bit width of only 20 bits can be obtained.
Since the number of M is 5 and cannot be expressed as a power of 2, a sufficient data input/output speed cannot be achieved. However, the frame memory capacity is 204
If it is set to 8x1024 pixels, the memory space will be achieved with 8 DRAMs, and the overall bit width will be 3.
2, and the number of DRAMs becomes a power of 2, so a sufficient data input/output speed can be achieved.

However, in the latter case, an empty area of 768×1024 pixels will inevitably occur. Therefore, using this empty area as a texture mapping memory area is very advantageous in terms of simplifying the configuration since there is no need to provide a special memory. When applying the Matsu Binta device, it is necessary to access different addresses in the frame memory in order to map one pixel, and even if the linear interpolation calculator has a fast operation speed, the frame memory Since the access time is quite long, the overall texture mapping speed cannot be improved much.

To explain in more detail, in consideration of the extremely large capacity of the frame memory and the need to reduce power consumption, the frame memory has a DRAM inside the shell.
is used, but the time required to access DRAM is about 230~4QQn5ec, for example,
Assuming 400 n5ec, 3000 polygons/second (however, one polygon is 20X inclined in any direction)
There is also the problem that a mapping speed of only about 20 pixels can be achieved. This problem can be solved by limiting the linear interpolation calculation of line segments to only the linear interpolation calculation of line segments in the scan line direction.
Since multiple pixel data can be written and successively output in one access, the time required for access when converted to one pixel can be made almost equal to the time required for linear interpolation calculation. However, when performing linear interpolation calculations on line segments determined based on data obtained by performing interpolation calculations on mutually opposing sides, as shown in L,
The number of pixels existing in the scan line direction is significantly reduced, and the above-mentioned access time of 230 to 400 n5ec is required to write or read the significantly small number of pixel data. Therefore, the ping speed cannot be improved much.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a texture mapping device that can project pixel data of a desired area on a texture plane onto a desired area of a three-dimensional figure on a display plane at extremely high speed.

Means for Solving the Problems> In order to achieve the above object, the texture mapping device of the present invention sequentially changes address data in synchronization with sequentially supplied texture plane coordinate data. source data temporary holding means for holding source data on a source vector read in correspondence with coordinate data; and source data temporary holding means in synchronization with an operation of generating display plane coordinate data on a destination vector corresponding to the source vector. and source data supply means for reading out the source data held in the memory in the order in which they are stored and supplying the read data to the destination data holding means, and furthermore, the destination data holding means is composed of a plurality of block memories. At the same time, the source data supply means inputs the double buffer memory and display plane coordinate data corresponding to each block memory and decodes the lower digits,
It has timing control means for generating a control signal for causing pixel data to be transferred through the double buffer memory based on the decode signal.

However, it is preferable that the source data holding means and the disinduction data holding means are allocated to the same image memory.

In addition, the source data holding means is composed of a plurality of block memories, and a double buffer memory for writing, a double buffer memory for reading, and a lower digit by inputting the texture plane coordinate data in correspondence with each block memory. timing control means for decoding and generating a Mill signal for writing pixel data through the double buffer memory for writing based on the dead signal; and timing control means for delaying the texture plane coordinate data by a predetermined time for reading. Preferably, it includes delay means for supplying the double buffer memory.

The delay means may be composed of a FIFO memory and a decoder, or may be composed of a linear interpolation calculator that generates texture plane coordinate data at a timing delayed by a predetermined period R, and a decoder. You can leave it there.

Further, the source data temporary holding means may be a static random access memory (hereinafter abbreviated as SRAM) or a FIFO memory.

Furthermore, the timing control means generates a t/J III signal that decodes the lower digits of the coordinate data in the scan direction to switch the double buffer memory, and also generates the t/J III signal that switches the double buffer memory. Preferably, the control signal decodes the digit and generates a control signal for selecting the double buffer.

Preferably, the timing control means generates a control signal at a timing when a predetermined lower digit of the coordinate data changes.

Further, as for the coordinate data in the scan direction, the timing control means is configured to control the coordinate data in the scan direction at the timing when the lower predetermined digit corresponding to the capacity of the double buffer memory changes.
For the coordinate data in the direction perpendicular to the scan direction, 1 is generated at the timing when the lowest digit changes.
Preferably, it generates a jlIll signal.

Furthermore, as the timing ilJ″m means, O
Preferably, the drawing end signal output from the DA is also input to generate a control signal for switching the double buffer memory.

Further, it is preferable that the image memory is constituted by a block memory of a plurality of frames of a predetermined size, and that each block memory is divided into two to store mutually different image data, and that it is a dual port DRAM. More preferred.

With the texture mapping device having the above configuration, texture plane coordinate data is supplied to the source data holding means that holds 1i image information for projection, thereby reading out the source data and displaying it. When texture mapping is performed by supplying source data in correspondence with the supplied display plane coordinate data to a destination data holding means that holds image information for the display, the texture plane coordinate data is supplied. As a result, the color data of the pixels on the source vector are sequentially read from the source data holding means and sequentially stored in the source data temporary holding means whose address data is sequentially changed in synchronization with the texture plane coordinate data. Then, the source data supply means reads out the color data held in the source data temporary holding means in the order of storage in synchronization with the display plane coordinate data generation operation on the destination vector corresponding to the source vector, and holds the destination data. Supply means. In this case, the destination data holding means is composed of a plurality of block memories, and the source data supply means receives double buffer memory and display plane coordinate data in correspondence with each block memory. Since it has a timing I control means that decodes the lower digits and generates a control signal for writing pixel data through the double buffer memory based on the decoded signal, the source data is sequentially read from the temporary storage means. The color data stored in the buffer memory is immediately stored in one of the buffer memories, and the data stored in the buffer memory is sequentially supplied to the block memory. Data can be supplied, and the generated pixel data can be temporarily held in the buffer 7 memory and sequentially written to the image memory, improving the overall texture mapping speed. be able to.

If the source data holding means described in F and the destination data holding means are allocated to the same image memory, the same effect as described above can be achieved without increasing the number of memories. can be achieved.

Further, the source data holding means is composed of a plurality of block memories, and in correspondence with each block memory, a built-in double buffer memory, a read double buffer memory, and texture plane coordinate data are input to a lower level. timing control means for decoding the digit and generating a control signal for writing pixel data through the writing double buffer memory based on the decoded signal; and a reading double buffer for delaying the texture plane coordinate data by a predetermined time. When the memory is provided with a delay means for supplying the address data for reading to the source data holding means, it is possible to supply the address data for reading to the source data holding means at high speed. Since the double buffer memories can be switched and selected, read data can be supplied to the source data temporary holding means at high speed.

In this case, the delay means is a FIFO memory,
and a decoder, or a linear interpolation calculator that generates texture plane coordinate data at a timing delayed by a predetermined time, and a decoder, the same effect as above can be achieved. Can be done.

Furthermore, even when the source data temporary holding means is a static random access memory, or a FIF
Even in the case of O memory, the same effect as described above can be achieved.

The timing control means decodes the lower digits of the coordinate data in the scan direction and generates an i control signal for switching the double buffer memory, and also generates the lower digits of the coordinate data in the direction perpendicular to the scan direction. Decode and double buff? If the control signal is to be generated for selection, the lower digits of the coordinate data in the scan direction are decoded and the double Since the buffer memory is switched, the overall data writing speed or data reading speed for the source data holding means or destination data holding means can be improved. In a state where mapping is performed based on source vectors and destination vectors that are tilted, the lower digits of the coordinate data in the direction perpendicular to the scan direction are decoded to select a double buffer, so the same double buffer is selected next time. It becomes possible to write data to the destination data holding means or read data from the source data holding means until selection, and it is possible to improve the texture mapping speed as a whole.

Furthermore, if the timing control means generates a control signal at the timing when a lower predetermined digit of the coordinate data changes, the read source data can be accurately held in the predetermined buffer 7 memory. , the same effect as above can be achieved.

Furthermore, the timing control means generates a control signal for the coordinate data in the scan direction at a timing when a lower predetermined digit corresponding to the capacity of the double buffer memory changes, and for the coordinate data in the direction perpendicular to the scan direction,
When the control signal is generated at the timing when the least significant digit changes, the double buffer 1 memory can be switched or the double buffer memory can be selected based on the generated control data. A similar effect can be achieved.

Furthermore, if the timing control means generates a control signal for switching the double buffer memory by also inputting the drawing end signal output from the DDA, the timing control means automatically switches the double buffer memory at the end of drawing. Memory can be switched.

In addition, if the image memory is composed of a plurality of block memories of a predetermined size and each block memory is divided into two to store different image data, the data of the entire image memory The number of input bits for writing can be increased.

When the image memory is a dual-port DRAM, it is possible to significantly reduce the time during which data writing is prohibited when reading data from the image memory, and to achieve the same effect as described above. Can be done.

To explain in more detail, if the time required for calculation by DDA is tl, and the time required to write data to the image memory is t2 (however, t2 - ntl), then the image memory is configured with n 70-block memories, and each block By providing a double buffer memory and a timing control means in correspondence with the memory, data can be supplied from the double buffer memory to the corresponding block memory without stopping the arithmetic operation by ODA.
Data can be written to the image memory at high speed. That is, when address data for data writing that is continuous in the scan line direction is generated sequentially from the ODA, a predetermined number of pixel data is sequentially supplied to the double buffer memory corresponding to the scan line, and a predetermined number of pixel data are sequentially generated. When pixel data is supplied, the double buffer memory can be switched to supply the predetermined number of pixel data again. Then, while pixel data is being supplied to one buffer memory, a predetermined number of pixel data can be supplied at once to the block memory from the other buffer memory. As a result, mapping data can be continuously written into the image memory while the DDA is kept operating at all times.

Similarly, when the DDA generates address data for reading data, it is possible to continuously read data from the image memory while keeping the DDA in constant operation.

In addition, when continuous address data is generated sequentially from the ODA in a direction inclined to the scan line,
For pixel data belonging to the same scan line,
Similarly to the above, it can be supplied to the double buffer memory corresponding to the scan line, and when the scan line changes, it can be supplied to a different double buffer memory. When the scan line changes, additional double buffer memories are selected one after another, so the scan line will change 0 times before the original double buffer memory is selected again. ,
Since writing of data to the image memory can be completed until then, the series of operations described above can be repeated without stopping the arithmetic operation by ODA.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 3 is a block diagram showing an embodiment of the texture mapping device of the present invention.

y value (two-dimensional coordinate data on the display plane or two-dimensional coordinate data on the texture plane) and binary (depth coordinate data on the display plane)
Edge interpolation circuits (11) (12) (13) (21) corresponding to
) (22H23) and the above edge interpolation circuit (11) (12)
(21) A line segment interpolation circuit (31) which inputs the x and y values output from (22), and the edge interpolation circuit (13) (
a line segment interpolation circuit (32) that receives the Z values output from the line segment interpolation circuit (31), and a source data memory (32) that receives the x and y values output from the line segment interpolation circuit (31) as data read addresses. 42) and a static random access memory (hereinafter referred to as SRAM) in which color data read out from the source data memory (42) is sequentially stored.
) (43), and the address data that increases sequentially in synchronization with the supply of the data read address is S R
an up counter (44) that supplies the A M (43); and a 2-buffer (not shown) that performs 2 sort processing and generates 2 flags by being supplied with the Z value;
It consists of a destination data memory (41) in which the color data read from the SRAM (43) is written to the corresponding address by supplying the above x, y values as a data write address. Incidentally, the destination data memory (41) and the source data memory (42) are respectively allocated to different address spaces of the same frame memory (4).

The side interpolation circuit and line segment interpolation circuit each include a division circuit and an addition circuit. Further, (14) is an I10 interface for taking in drawing command data supplied from a host processor (not shown), (15) is a processor that performs edge selection processing, etc., and (16) is a memory.

FIG. 2 is a block diagram showing the configuration for writing color data to the destination data memory (41), in which the destination data memory (41) is divided into four block memories (41G) (411).
(412) and (413), and the x, y values and S output from the line segment interpolation circuit (31)
The color data read from RAM (43) is
Double buffer memory (45G) (451) (
452) and the block memory (41) via (453).
G) (411) (412) (413).

A timing control circuit (46) is provided corresponding to each block memory and double buffer memory.
0) (461) (462) (463). In addition, the above timing control circuits (460) (461) (4
62) (463) decodes the x and y values output from the line segment interpolation circuit (31) to generate a double buffer switching signal, a double puncher selection signal, and a block memory selection signal. To explain in more detail, the X value and ylil are each decoded by inputting the address data output from the line segment interpolation circuit (31), and the predetermined digit data Cl1F of the X value is decoded.
A double buffer memory switching control signal is generated based on a decode signal corresponding to a predetermined number of upper digits determined based on the capacity of the double buffer memory, and a data write control signal for the block memory is generated based on the decode signal. , generates a double buffer selection control signal and a double buffer memory switching control signal based on the decoded signal corresponding to the least significant digit data of the y coordinate, and generates a data write control signal for the block memory, and further, A double buffer 1 memory switching control signal is generated based on a decode signal corresponding to a line segment drawing end signal (a signal indicating that the control counter of the n-segmentation circuit (31) has reached 0). Further, each of the frame memories (4) has a dual plane configuration, so that while one image is being displayed, other image data can be loaded.

The operation of the texture mapping device having the above configuration is as follows.

FIG. 1 is a schematic diagram for explaining the mapping operation, in which a source data memory (42) and a destination data memory (41) are allocated on the frame memory 6).

Therefore, first, by sequentially generating the x and y values on the source data memory (42) from the line segment interpolation circuit (31) and supplying them as data read address data,
The color data on the source vector (48) is sequentially read out and sent to SRAM (43) where the write address is specified by the up counter (44) whose contents are sequentially incremented in synchronization with the generation of the x and y values. The read color data can be sequentially written.

Next, the x and y values on the destination data memory (41) are sequentially generated from the line segment interpolation circuit (31).
By supplying the data as the data write address data, the color data read from the S RAM (43) in the writing order can be written onto the destination vector (49) for mapping.

That is, the color data on the source vector (48) is sequentially read out from the source data memory (42) allocated on the frame memory (4) and stored in SRAM (43).
Mapping processing can be performed by temporarily retaining the color data and then reading the color data from the SRAM (43) in the order in which they were stored and writing them onto the destination vector (49) of the destination data memory (41). It can be done.

Among the above series of processing, the source vector (48
) can be stored in the S RAM (43) in a short time because the access speed of the S RAM (43) is fast.

Furthermore, for writing the color data read from the SRAM (43) into the destination data memory (41), the destination data memory (41) is divided into four block memories, each with 70 block memories. Since a double buffer memory and a timing control circuit are provided for each, as explained below, it can be done in a short time on a per pixel basis, and the overall texture mapping speed can be increased. can be significantly improved.

That is, in a state where continuous address data in the X coordinate direction is sequentially generated from the line segment interpolation circuit (31),
Only one timing control circuit generates a write control signal, switches the double buffer memory every time a predetermined number of pixel data is generated, and sends SRA to the negative buffer memory.
While the read color data from M (43) is being supplied, a plurality of color data can be written at once from the other buffer memory to the block memory. Therefore, a predetermined number of color data can be loaded into the destination data memory (41) at once without interrupting the calculation operation by the line segment interpolation circuit (31).

In a state where continuous address data in a direction inclined at a predetermined angle with respect to the scan line is being generated sequentially from the line segment interpolation circuit (31), while address data belonging to the same scan line is being generated continuously. , an appropriate timing control circuit can generate a verbal control signal to cause color data to be supplied to the double buffer memory and to be loaded from the double buffer memory to the block memory. When address data belonging to the adjacent scan line is generated, the corresponding timing control circuit generates a write control signal to supply color data to the double buffer memory and from the double buffer memory to the block memory. Color data can be refined.

Thereafter, every time the scan line to which the generated address data belongs changes, the timing control circuit that generates the write control signal changes, and the continuous color data in a direction inclined at a predetermined angle with respect to the scan line is transferred to the destination data memory ( 41).

In other words, the number of color data supplied to each double buffer memory is generally smaller than the limit determined based on the capacity of the double buffer memory, but if color data is supplied to the same double buffer memory, If the time required to write data from the double buffer memory to the block memory is set to a time that is not shorter than the time required to write data from the double buffer memory to the block memory, data is stored in the double buffer memory without interrupting the calculation operation by the line segment interpolation circuit (31). It is possible to write all color data in the destination data memory (41) all at once.

When one piece of image data is mapped as described above, the image data can be read out from the corresponding destination data memory plane and displayed. The next image data can be written to the other image memory plane.

Even if the time required to write data to the frame memory (4) is long, the time required to write data per pixel can be made almost equal to the time required for calculation of the line segment interpolation circuit (31), and the mapping speed can be significantly increased. It can be improved.

FIG. 4 is a block diagram showing a configuration for improving the speed of reading color data on a source vector (48) from a source data memory (42). (401) (4
02) (403), and a write double buffer memory (403) corresponding to each block memory.
5G) (451) (452) (453), double buffer memory for reading (454H455) (456) (45
7), and timing control circuits (460) (461)
(462) (463), and the x and y values output from the line segment interpolation circuit (31) are directly transferred to the writing double buffer memory (450) (451) (4
52) (453) as well as delay F.
The decoded data is supplied to the decoder (40) through the IFO memory (50), and the decoded data output from the decoder (40) is sent to the read double buffer memory (454) (45).
5) (456) (457). In addition, the double buffer memory for reading (454) (455)
The color data read out through (456) and (457) is supplied to SRAM (43) whose storage address is sequentially incremented by an up counter (44).
The read data from AM (43) is transferred to the line segment interpolation circuit (3).
1) The above writing double buffer memory (450) (451) (452) together with the address data output from
(453). In addition, the above line segment interpolation circuit (3
1) Writing data to frame memory (4);
Alternatively, when address data for reading data is generated and address data for reading data is generated, supply of data to be written is prohibited.

Therefore, in the case of this embodiment, when writing data to the frame memory (4) divided into four block memories, that is, when writing color data sequentially output from the SRAM (43), ,
As in the embodiment shown in FIG. 2, the time required to write data per pixel can be made equal to the time required for calculation by the line segment interpolation circuit (31).

Also, source vector (48
), the corresponding writing double buffer memory and block memory are selected based on the switching control signal and selection control signal output from the timing control circuit, and the line segment interpolation circuit (31 ) The necessary color data is read out from the block memory based on the address data output from the block memory. Then, the address data is stored in F for a time corresponding to the time required to complete reading.
The IFO memory (50) delays the decoder (
40), so there is no need to generate the x, y coordinates for reading again, and the double buffer memory (45
S A R via 4H455) (456) (457)
It is only necessary to supply the read data to M (43), and as in the case of the embodiment shown in FIG. can be made equal.

More specifically, as shown in FIG. This can be easily done by adopting a pipeline configuration in which the data are sequentially supplied to the registers (51) and (52).

That is, as shown in FIG. 5B, the register (512(
52) as D type 7 lip 70 lip (hereinafter referred to as D-
(abbreviated as FF), and the first stage D -F F
The J-th digit data output from the line segment interpolation circuit (31) is supplied to the D input terminal of (51), and the
The Q output signal of F (51) is converted to the second stage D -F F
(52) is supplied to the D input terminal, and one additional car D -F
If a configuration is adopted in which the DDA clock signal is supplied to the timing input terminals of F (51) and (52), both D - F
F (51) (52) Q output signals aj, bJ, J5.
J = 0 output signal fiJ, 5J is obtained. Then, the obtained tc signal bJ, and! : IJ AND')"-
(53), and the signals aJ and 5J
is supplied to the AND gate (54), and both AND gates (5
3) By supplying the output signal from (54) to the NOR gate (55), a detection flag for detecting a change in a specific digit can be generated.

Figure 6 shows the changes in the least significant digit of the y coordinate, the changes in the upper digits by a predetermined number from the least significant digit of the X coordinate, and the end of line segment drawing.
It shows a circuit configuration that detects only when the lower digit of the coordinate is a predetermined value, and the DDAjJO calculator (56
), the output data from the DDA7J11 calculator (57) for the y coordinate are supplied to circuits having the same configuration as that shown in FIG. (overflow flag that becomes high level when the content of (58) is 0),
And an output signal from the decoder (59) which takes the y-coordinate data output from the DDA as input and becomes high level when the content of the lower digit becomes a value corresponding to a predetermined block memory is supplied to the AND gate (60). are doing. Then, all the output signals from the decoder (59) are ANDed.
It also supplies the output signals from all AND gates to the NOR gate (61).

Therefore, when the above configuration is adopted, when the output signal from the decoder (59) is at a high level,
A negative logic double buffer memory switching timing detection flag can be output from the NOR gate (61) in response to a change in the most significant digit of the y coordinate, a change in a predetermined digit of the X coordinate, and the end of the line segment mFfj.

In addition, the decoder shown in FIG. 6 and AND-OR-IN
VERTER is easy to use pLD (Prografl
It can be converted into a lable Logic Device).

FIG. 7 shows DRAM timing control without stopping the line segment interpolation circuit (hereinafter abbreviated as DDA) based on the double buffer memory switching timing detection flag generated by the circuit configuration illustrated in the above embodiment. , and a circuit configuration for performing double buffer memory switching, in which eight D-FFs (γ1) (
72)...(78).

The above D -F F (71) is a horizontal synchronizing signal 1-1sYNc (
8C) as a timing input, and a handshake signal H81 (see FIG. 8C) indicating whether read transfer or refresh has been accepted as a clear input,
IQ output signal Q1 (8th
(see Figure C), and this Q output signal Q1
The sampling strobe signal MSRCK (
D -F F with timing input (see diagram 8)
It is supplied to the D input terminal of (72) and generates a Q output signal Q2 (see FIG. 8M) indicating whether it is a write cycle, read transfer, or refresh cycle for the RAM.

The above D-F F (73) and (74) hold the double buffer memory switching timing detection flag BOVI" (see Figure 8C), and are identical to each other except that they operate selectively. It is designed to perform the following actions.

That is, NA using the ◇output signal of the above D-FF as a control signal.
Double buffer memory switching timing detection flag B is passed through the ND gate (79).

VF is supplied to the D input terminal, and the DDA pixel strobe signal DDAR whose level fluctuates for each pixel.
CK (see Figure 8C) is supplied to the timing input terminal through the OR gate (80), and a negative logic handshake signal H82 (see Figure 8C) indicating that the memory write cycle has been accepted is supplied. OR gate (
81) and an AND gate (82) to the clear input terminal. The Q output signal 5ELA (see the eighth diagram) and the 0 output signal 5 output from the D-F F (78) correspond to one D-FF.
Each ELB (see Figure 8C) is an OR gate (80)
(81) and is outputted from D-FF (78) in correspondence with the other D-FF.

and ◇Output signal 5ELB is OR gate (81
) (80).

Therefore, of the Q output signal 5ELA1 or the Q output signal 5ELB supplied to the OR gate (80), the D=FF on the low level side is selected for data retention, and the rising edge of the DDA pixel strobe signal DDARCK is selected. The double buffer memory switching timing detection flag BOVF is taken in at the timing. However, the double buffer memory switching timing detection flag s o v r:
is a NAND gate (7
9), so (signal BFI, F3F
2 (see FIG. 8 I, J)), the signal is supplied to the D input terminal at a timing when a buffer memory full state is likely to occur, and at the same time, it is supplied to an OR gate (83), which will be described later, and is held as is.

The above D-F F (75) generates a Q output signal Q3 corresponding to the next double buffer memory switching state, and supplies the Q output signal to the D input terminal, and also performs the above negative logic handshake. A signal H82 is provided to the timing input terminal.

The above D-F F (7B) (77) generates the sampling strobe signal 5RCK synchronized with the clock without generating glitches, and generates the negative logic pulse signal MB indicating two clocks before the end of the memory cycle.
F2 (see FIG. 8C) is supplied to the timing input terminal of D-FF (16), and a negative logic pulse signal CAS (for example, a column address strobe signal of DRAM) is supplied to the timing input terminal of D-FF (16). Figure 8C
) is supplied to the preset input terminal. Then, the Q output signal Q1 of the above D-F F (71) and the NAN corresponding to both D-F F' (73) (74)
OR gate (83) output signal from D gate (79)
The 0 output signal of D-FF (76H77) is supplied to the D input terminal of D-FF (77) through
The output signal from the NAND gate (84) which inputs the sampling clock signal SCK (see Fig. 8N) is outputted as the sampling strobe signal 5RGK, and is also supplied to the timing input terminal of the D-FF (7γ). .

Then, the negative logic pulse signal CAS is applied to the D-FF (71
) is supplied to the clear input terminal. Also, D-F
The Q output signal of F (77) is outputted as a start signal (see N in FIG. 8) indicating that a memory cycle starts at the rising timing.

The above D -F F (78) outputs the double buffer memory switching signals 5ELA and 5ELB as a Q output signal and a 0 output signal, respectively.
The Q output signal of F (75) is supplied to the D input terminal, and the sampling strobe signal 5RG
K is supplied to the timing input terminal, and the output signal ACDM (8th
(see figure) is supplied to the G input terminal through an inverter (85).

Therefore, at the timing when the signal supplied to the G input terminal is low level and the sampling strobe signal 5RGK rises, the Q output signal from the above 0-FF (75) is held, and the output signal corresponds to the level of this Q output signal. In this way, the Q output signal 5ELA and the 0 output signal 5ELB, which have mutually opposite levels, are continuously output.

Furthermore, the negative logic initialization signal RESET (see FIG. 8N) is applied to the above D -F F (71H73) (74)...
・They are supplied to the ・clear input terminals of (78), respectively.

The operation of the circuit shown in FIG. 7 is as follows.

First, when the power is turned on or processing is interrupted, the initialization signal 7 is sent.
performs the necessary initialization.

After that, the level of the Q output signal of the D-FF (75) changes alternately every time the negative logic handshake signal H82 is supplied to the timing input terminal, so a low level signal is supplied to the G input terminal, and At the timing when the sampling strobe signal 5RGK rises, D −FF (
78) holds the Q output signal, and outputs a Q output signal 5ELA1 and a 0 output signal 5E corresponding to the level of the Q output signal.
LB can be output. Therefore, one of the D-FFs (T3) (74) is selected based on the levels of the Q output signal 5ELA and the Φ output signal 5ELB. That is, the D-FF to which the low level signal is supplied to the OR gate (80) is selected.

The selected D-FF is supplied with the double buffer memory switching timing detection flag BOVF as the D input signal through the NANO gate (19) which is V4m-controlled by the Q output signal, and the OR gate ( 80) as a timing input signal.
Since the DA pixel strobe signal DDARCK is supplied, the DDAii pixel strobe signal DDARC
At the rising edge of K, the double buffer switching timing detection flag BOVF is read and held as is. Furthermore, the double buffer memory switching timing detection flag BOVF mentioned above is not taken out from the Q output terminal of the D-FF, but is taken out as it is from the output terminal of the NANO gate (19). It is supplied to the OR gate (83) at the timing when the buffer memory is full without any delay, and D - F
By being supplied to the D input terminal of F (77),
A start signal indicating the start of a memory cycle can be output from the Q output terminal.

Then, each time the negative logic handshake signal H82 is supplied to the timing input terminal, D-FF (73) (74
) can be used to perform the series of operations described above.

FIG. 8 is a timing chart illustrating the operation of each part of the circuit of FIG. 7, in which a read transfer operation for reading image data is performed during a period T1, and a read transfer operation for reading image data is performed during a period T2. An image data writing operation is performed during the period T3.

Therefore, by associating timing control circuits with the configurations shown in FIGS. 6 and 7 with each block memory and performing VII, the frame memory (4 ) Texture mapping can be performed by sequentially reading data from and writing data to the source data memory (42) and destination data memory (41) assigned to the data memory (41). That is, source vector (48), destination vector (49)
By eliminating the influence of the slope of , any vector can be converted per pixel to D D A (31)
The mapping process in the frame memory (4) can be performed in a time equal to the time required for the calculation.

2048X10 for graphic display devices
To obtain a 24-pixel image memory, one image memory is constructed using eight 256-bit DRAMs to store pixel data for one screen, and is also used as a double buffer memory. Two 1x8 bits are used as a set. The image memory has a dual plane configuration consisting of a plane for storing pixel data being displayed and a plane for writing pixel data for the next display. It consists of eight 256-bit DRAMs.

Therefore, even if you try to divide the screen memory into eight block memories for each plane and provide a double buffer memory and a timing control circuit corresponding to each block memory while maintaining the dual-brain configuration as described above, it will be difficult to This cannot be applied because the input bit width of the image memory as a whole is small. That is, since the input bit width of the 256-bit DRAM is set to 4 bits, the input bit width of each image memory as a whole is only 32 bits.

However, when eight 1x8-bit double buffer memories are provided, the bit width of the double buffer memories as a whole is 64 bits, so it is not possible to ensure a one-to-one correspondence between the sides. 16 DRAs per plane
Since M must be used, there is a problem in that more memory is required than necessary.

In order to solve these problems, to ensure a dual-plane configuration as an image memory, and to ensure a sufficient input pit width, each DRAM is Inside of , each plane is partitioned and D D A (31
) to determine which plane should be accessed based on the last three digits of the y value output from
(See Figure 9A).

FIG. 9B is a diagram for further detailed explanation, in which timing control circuits CNTO1CNT1...CNT7 are provided, and double buffer memories DBO, DBI...DB7 are provided corresponding to each timing control circuit. , 16 D corresponding to each double buffer memory
RAMOLDRAMl...DRAM units, respectively...DRAMj-2, DRAMj-1, DRAM, D
It is divided into RAM unit 1, DRAM unit 2, and so on. Furthermore, the even-numbered and odd-numbered DRAMs are paired and correspond to each double buffer memory, respectively.
Moreover, it is made to correspond to each timing control circuit.

In addition, each of the above timing 1111 circuits has 0DA (31
) and the address data on the DRAM to which the pixel data supplied to the double buffer memory should be written based on the upper address data of yll...
j-2, j-1, j, j+1, j+2, . . . are held, and data for selecting a plane based on the data in the last 7th digit is also held.

Therefore, as in the case of the above embodiment, OD A is performed on the condition that the least significant digit of the y-coordinate changes, the F4th digit of the X-coordinate changes, or the line segment drawing is completed.
The data output from (31) is supplied to one buffer 7 memory of either double buffer memory, and the data held in the other buffer memory is supplied to -.
Data can be written to the corresponding DRAM all at once, and as a whole, the time required to write data per pixel to the DRAM can be made equal to the time required for calculation for one pixel by ODA (31).

As a result, the arithmetic operation by OD A (31) must be stopped during the refresh operation period for the DRAM and the period during which pixel data is read out from the DRAM at the time of display, but for periods other than the above,
Pixel data can be generated and the generated pixel data can be written into the DRAM without stopping the arithmetic operation by DDA (31). Moreover, since the DRAM refresh operation period is predetermined, it is possible to predict it, and it can be dealt with simply by thinning out the DDA control clock in advance. This eliminates the need for a handshake to identify the data, and further reduces the time required to write data to the image memory.

Furthermore, in the above embodiment, if a dual-port DRAM is used as the DRAM, the time required for reading for display can be greatly reduced, and about 98% of the time can be allocated for data writing. Therefore, the time required to write data to the image memory can be shortened as a whole.

It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, instead of S RAM (43), FIFO
In addition to being able to use memory, FI for delay
Instead of the FO memory (50), it is possible to use a separate DDA that generates address data at a timing delayed by a predetermined time from the line segment interpolation circuit (31),
Furthermore, it is possible to change the number of double buffer memories and the number of timing control circuits, and it is also possible to perform processing such as enlargement, reduction, rotation, etc., and other changes can be made to the gist of the invention. It is possible to make various design changes within the scope.

<Effects of the Invention> As described above, the present invention causes the data on the source vector read from the source data holding means to be temporarily held in the source data temporary holding means whose addresses are sequentially increased; The mapping process is performed by writing the data into one of the block memories constituting the destination data holding means via a double buffer memory that is controlled based on a control signal output from the timing control means. Since the destination data that has been mapped is obtained, there is a unique effect that the texture mapping process can be performed at an extremely high speed as a whole.

[Brief Description of the Drawings] Fig. 1 is a schematic diagram explaining the mapping operation, Fig. 2 is a block diagram showing the configuration for writing color data to the destination data memory, and Fig. 3 is a schematic diagram illustrating the mapping operation. FIG. 4 is a block diagram showing an embodiment of the Chikusuge Yamatsubing device; FIG. 4 is a block diagram showing a configuration for also improving the speed of reading color data of source vector F from the source data memory; FIG. 5A is an ODA A schematic diagram showing the vibrating state; Figure 5B is a diagram showing an example of a circuit configuration for detecting a change in the content of a specific digit of address data; Figure 6 is a diagram showing the content of a specific digit of address data. FIG. 7 is a diagram showing the other side of the circuit configuration for detecting a change in , and FIG. 7 is a diagram showing a circuit configuration for controlling the timing of the DRAM and performing double buffer memory switching based on the double buffer memory switching timing detection flag. , FIG. 8 is a timing chart explaining the operation of the circuit diagram in FIG. 7, FIG. 9A is a diagram explaining the brain configuration of the image memory, and FIG. 9B is a diagram showing the image memory with the configuration shown in FIG. 9A. , a double buffer memory, and a timing control circuit. (4) Frame memory, (31) Line interpolation circuit, (40) Decoder, (41) Disaination data memory, (42) Source data memory, (43)...SRAM, (44)...up counter, (48)...source vector, (49)...destination vector, (50
)・FIFO memory, (400) (401) (402) (403)...Block memory, (450) (451)...(457)・
・Double buffer memory, (460) (461) (4
62) (463)... Timing control circuit patent applicant Daikin Industries, Ltd. Agent Patent attorney Tomoshi Tsugawa Figure 2 Figure 5 (B) Figure 6 (A)

Claims (1)

[Claims] 1. Read the source data by supplying texture plane coordinate data to the source data holding means (42) holding image information for projection, and read the image information for display. In a texture mapping device that supplies source data to destination data holding means (41) in correspondence with supplied display plane coordinate data, address data is supplied in synchronization with sequentially supplied texture plane coordinate data. source data temporary holding means (43) for holding data on a source vector (48) that is sequentially changed and read out in accordance with the texture plane coordinate data;
Then, in synchronization with the display plane coordinate data generation operation on the display vector (49) corresponding to the source vector (48), the source data held in the source data temporary holding means (43) is read out in the order in which they are stored, and destination data is generated. and a source data supply means for supplying the source data to the holding means (41), and furthermore, the destination data holding means (41) is a plurality of block memories (410), (411), (412), and (413). The source data supply means is configured to include:
Double buffer memory (
450) (451) (452) (453) and display plane coordinate data as input, decodes the lower digits, and generates a control signal to write pixel data through the double buffer memory based on the decoded signal. Means (460) (461) (462)
(463) A texture mapping device comprising: (463). 2. Texture mapping according to claim 1, wherein the source data holding means (42) and the destination data holding means (41) are allocated on the same image memory (4). Device. 3. The source data holding means (42) is composed of a plurality of block memories (400) (401) (402) (403), and each block memory (400)
(401) (402) (403) Double buffer memory for writing (450) (451) (452)
(453), double buffer memory for reading (454)
(455), (456), and (457), and timing control that decodes the lower digits by inputting texture plane coordinate data and generates a control signal to write pixel data through the writing double buffer memory based on the decoded signal. Means (460) (461) (462) (
463), and a delay means (50) for delaying the texture plane coordinate data by a predetermined time and supplying the same to a reading double buffer memory. Texture mapping device. 4. The third aspect of the above claim, wherein the delay means is composed of a FIFO memory (50) and a decoder (40).
The texture mapping device described in Section 1. 5. A linear interpolation calculator in which the delay means generates texture plane coordinate data at a timing delayed by a predetermined time;
The texture mapping device according to claim 3, comprising a decoder and a decoder. 6. The texture mapping apparatus according to claim 1, wherein the source data temporary holding means is a static random access memory. 7. The texture mapping apparatus according to claim 1, wherein the source data temporary holding means is a FIFO memory. 8. The timing control means decodes the lower digits of the coordinate data in the scan direction to generate a control signal for switching the double buffer memory, and also decodes the lower digits of the coordinate data in the direction perpendicular to the scan direction. A texture mapping device according to any one of claims 1 to 3, which generates a control signal for selecting a double buffer. 9. The texture mapping device according to any one of claims 1 to 3, wherein the timing control means generates the control signal at a timing when a lower predetermined digit of the coordinate data changes. 10. The timing control means generates a control signal for coordinate data in the scanning direction at a timing when a predetermined lower digit corresponding to the capacity of the double buffer memory changes;
10. The texture mapping apparatus according to claim 9, wherein the control signal is generated at the timing when the least significant digit changes for coordinate data in a direction perpendicular to the scanning direction. 11. Claims 8 to 10 above, wherein the timing control means generates a control signal for switching the double buffer memory by also inputting a drawing end signal output from the linear interpolation calculator. The texture mapping device according to any one of the above. 12. Claims 1 to 3 above, wherein the image memory is composed of a plurality of block memories of a predetermined size, and each block memory is divided into two to store mutually different image data.
The texture mapping device according to any one of the above items. 13. The texture mapping device according to claim 1, 2, or 12, wherein the image memory is a dual-port dynamic random access memory.