JP2757790B2 - Memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller useful when applied to an image display controller.

[0002]

2. Description of the Related Art Generally, in an image display device, a memory for storing display data called a video memory or a frame memory must be read out at any time during a display period.
In the case of an apparatus used for a video game or the like, it is necessary to frequently rewrite the data in the memory simultaneously with the reading operation. Conventionally, a dynamic RAM (DRAM) has been used for such an image memory.

[0005] However, in a normal DRAM, the access time is longer than the time for displaying one dot. Therefore, in order to perform high-speed memory access during the display period, display data reading from the memory is performed simultaneously for several dots, and the read data is converted into RGB in accordance with the display scan.
A method of converting data into data and using the remaining time for access such as rewriting, a method of simultaneously performing data reading and rewriting using a dual-port DRAM, and the like are used.

With such a method, data of about 64 bits can be finally read out during the display period of 8 dots. However, this number is, for example, only data for one screen when simultaneously displaying 256 colors (8 dots of data are required for one dot), and two figures for 16 colors (4 bits of data are required for 1 dot). Only minute data. In such a situation, there are few display modes (such as a mode in which a single 256-color simultaneous display surface is displayed and a mode in which two-color 16-color simultaneous display surfaces are superimposed and displayed). Therefore, how to use the minimum unit time required for accessing one address of the memory (hereinafter, referred to as a memory access slot) is as follows.
A circuit fixed in hardware according to the setting of the display mode has been used.

On the other hand, in an image display device for a video game or the like, there is a strong demand for overlapping more display surfaces and increasing the number of simultaneous display colors. When the display surfaces are superimposed, after processing the data of the memory for a plurality of surfaces, the priority is determined for each dot to determine the surface to be displayed. Therefore, in an image display device for a video game or the like, it is highly necessary to access a larger number of bits to the image memory.

As a DRAM that can meet such a demand,
Attention has been paid to a synchronous DRAM (hereinafter, referred to as an SDRAM) that enables high-speed access. SDRAM is
In the bank division mode, two memory areas (bank 0 and bank 1) are provided, and bank 0 and bank 1 are alternately accessed by clock control, and the address of bank 1 is read while bank 0 data is being read. It is possible to take in. If an SDRAM is used, for example, a data width of 16 bits can be used to access 512 bits of data within a time period of displaying 8 dots.

[0007]

SUMMARY OF THE INVENTION S that can be accessed at high speed
When a DRAM is used as an image memory, for example, even on a display surface that requires 24-bit data per dot, which can display a natural image, data for two surfaces can be accessed.
4 bits / 1 dot (16
In (color display), data for 16 surfaces can be accessed. As the number of display colors, modes such as 24 bits / dot, 16 bits / dot, 8 bits / dot, and 4 bits / dot are conceivable. Depending on the user, many modes such as character mode and bitmap mode can be selected.

However, when such a large number of display modes are realized, if a circuit in which the control of the memory access slot is fixed in a hardware manner in accordance with the display mode setting as in the prior art is used, the character mode can be used as a pattern name address or a character mode. When changing the method of generating addresses based on the number of display colors on each surface or selecting different attribute data for each surface, a control circuit for that is required for the pattern name address generation unit and the character data address generation unit. And the circuit scale increases. Further, it is easy to control the SRAM to be in the bank split mode during the display period and to set the random access mode during the non-display period. However, in this case, a request such as screen rewriting from the CPU cannot be executed during the display period. Sufficient speed cannot be achieved.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a memory control device capable of interrupting in a random access mode during a data read operation in a bank division mode.

[0010]

A memory control device according to the present invention divides the inside into at least two banks and individually executes precharge, thereby continuously and alternately inputting the address of each bank without gaps. A dynamic RAM capable of switching between a bank division mode and a random access mode, and a mode setting means for periodically setting a data read operation in the bank division mode of the dynamic RAM in units of a predetermined number of access slots And monitoring the output of the mode setting means to detect that a predetermined number of access slots in which the two banks are not accessed are continuous during the data read operation in the bank split mode. Interrupt control means for outputting an interrupt enable signal It is characterized.

Preferably, in the present invention, the mode setting means selects a register for setting an access mode for each access slot in a minimum time unit required to access one address of the dynamic RAM, and selects a set value of the register. And a decoding unit that decodes the setting value selected by the slot selection unit and generates a control signal to the address generation unit.

[0012]

According to the present invention, the access mode in the SDRAM bank division mode can be set by the mode setting means. Therefore, for example, for each access slot, whether to execute a pattern name access, a character data access, a bitmap data access, or a random access from the CPU. By freely setting the display mode, the display surface can be freely configured. Further, the output of the mode setting means is monitored to detect during the data read operation in the bank division mode that a predetermined number of access slots in which the two banks are not accessed at the same time are consecutive. , An interrupt enable signal can be output, and high-speed performance of various systems can be realized by effectively utilizing access slots.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an image display control device according to one embodiment of the present invention. SDRA for storing display data
M1 has two internal banks 0 and 1 in the bank division mode. FIG. 1 shows a block configuration of the access control circuit unit for one of the banks 0.
The other bank 1 can be partially shared by performing time division processing or the like, but a similar control circuit is provided.

FIG. 2 shows an equivalent circuit configuration of the SDRAM 1 in the bank division mode. As shown in the figure, the memory address has an area 11a (bank 0) having an MSB of 0 and an area 11b having an MSB of 1 (bank 1). , 1 can be accessed alternately,
The precharge operation is individually performed. The read data is selected by the column selector 14, taken into the data latch 15, and output to the outside.

FIG. 3 shows an example of a read access timing of the SDRAM 1. The row address R0 and the column address C0 of the bank 0 and the row address R1 and the column address C1 of the bank 1 are alternately taken in according to the clock CK. The data D00 and D01 of the bank 0 are
It is output at the clock timing when the row address R1 and the column address C1 of the bank 1 are input. D01 is D
This is data at an address following 00, which means that two words of data can be output with one address input. If only one word is required, D01 is not required. The precharge of each bank is automatically executed at the output timing of the data D01 in the case of the final data, that is, the output of two words. The same applies to the output and precharge of the data D10 of the bank 1. The data is 16 bits wide,
Here, one address (row address and column address)
, And the time required to read 16-bit data for two words is the access unit time. That is, FIG.
.. For four periods of the clock CK are the time required for displaying one dot (8 bits) (about 14 bits).
0nS) and the SDRAM 1
Access slot.

In order to control the access to the display data of the SDRAM 1, a counter 2a for counting the horizontal position and the vertical position of the display scan, and a coordinate calculating means for generating coordinates in the display space based on the count value. 2
b is provided. For example, as shown in FIG. 4A, when the display surface is composed of 40 × 20 cells (1 cell = 8 × 8 dots), the display coordinates generation means 2 sequentially displays the display positions (0, 0). , (1,
0),... Are output.

The SDRAM 1 in FIG. 1 stores display data in a bitmap mode in addition to display data in a character mode. FIG. 4 shows a display example in a character mode. That is, as shown in FIG. 4B, a table of character data composed of 8 × 8 bits and a table of pattern name data for selecting the character data according to the display surface are stored in the SDRAM 1. You. The pattern name address generating means 3 and the character data address generating means 4 serve as address generating means for generating an address of data stored in the SDRAM 1 based on the coordinates obtained by the display coordinate generating means 2.
Is provided. For example, the display surface is divided into small areas (cells) equal to the minimum unit of character data of 8 × 8 dots or 16 × 16 dots, and which character pattern is displayed in each cell is determined by a pattern name unique to the character data. This will be set for each cell. The pattern name is often given by a number using the actual address of the memory where the character data is stored.

When the pattern name address is generated by the pattern name address generating means 3 based on the output from the display coordinate generating means 2, the SDRAM 1 is accessed via the memory interface means 5 to store the pattern name data. Is read. The read data is temporarily held in the buffer. Then, based on the pattern name data, the character data address is generated by the character data address generating means 4, and the SDRAM 1 is accessed via the interface means 5. Details of the pattern name address generating means 3 and the character data address generating means 4 will be described later.

The character data read from the SDRAM 1 is sent to the dot data control means 6 via the interface means 5. Here, character data is temporarily held for each screen, converted into RGB signals for each dot in accordance with a display scan, and sent to a display device. Here, dot data to be actually displayed is determined according to the priority order of each screen. There are various ways of assigning priorities.For example, a priority number is added to the pattern name and displayed in descending order of the value.If the dot code on the surface with the highest priority is a transparent code, the next priority is assigned. Processing such as display of dot data on a high surface is performed.

In order to control the pattern name address generating means 3 and the character data address generating means 4 to set a display mode, that is, an access mode for each memory access slot of the SDRAM 1, in this embodiment,
Sixteen mode setting registers 7 are provided. That is, in order to set the display mode in units of 8 dots (cycle of eight access slots), 8 dots × 2 banks = 1
Six registers 7 are prepared. A predetermined code is set in the register 7 for each memory access slot in accordance with the access content. FIG. 5 is a code setting example of the register 7.

The slot selecting means 8 is provided for selecting the code set in the mode setting register 7 as described above. The slot selecting means 8 comprises a 3-bit counter 8a for counting the period of 8 dots, and a selector 8b for selecting a setting code of the register 7 according to the count value.

The code output from the slot selecting means 8 is actually decoded by the decoder 9 into a signal for controlling the pattern name address generating means 3 and the character data address generating means 4. The output of the decoder 9 is delayed by the delay means 10 according to necessary processing. That is, the decoded control code is sent to the interface means 5 after being delayed by the time τ1 required for generating the pattern name by the delay circuit 10a, and the output of the pattern name address generating means 3 causes the SDRAM 1 to execute the pattern name address. Is indicated. Delay circuit 1
By 0b, a control code delayed by the time τ2 required for memory access is sent to the character data address generation means 4 to control generation of the character data address. Further, the control code delayed by the delay circuit 10c by the time τ3 required for generating the character data address is sent to the interface means 5 to instruct execution of access to the character data address.

In FIG. 1, the decoder 9 is provided before the delay means 10, but this decoder 9 is omitted, and a decoder is built in the pattern name address generating means 3 and the character data address generating means 4 instead. It is good also as composition which makes it do.

In the pattern name address generating means 3,
Based on the XY coordinate values output from the display coordinate generating means 2,
Generate a pattern name address. At this time, attribute data (for example, an offset value, etc.) of the pattern name address set for each surface is selected according to the slot control code sent from the delay unit 10. For example, as shown in FIG. 5, when code 0 is sent, a pattern name address is generated based on the attribute data of the first surface and the XY coordinate values.

The character data address generation means 4 uses a character name based on the pattern name read from the pattern name data table of the SDRAM 1 and held in the buffer and the XY coordinate values output from the display coordinate generation means 2. Generate a data address. The pattern name held in the buffer is selected according to the display surface when the control code sent from the delay unit 10 indicates access to character data. For example, when the code 4 shown in FIG. 5 is sent, a character data address is generated by adding a pattern name to the XY coordinates of the first surface.

The interface means 5 includes a delay means 10
When the slot control code sent from the controller instructs access to the pattern name address, the pattern name address output from the pattern name address generation means 3 is selected, and the memory address, RAS, A memory command signal such as CAS is transmitted. As a result, SDRAM1
And outputs the pattern name to the character data address generating means 4.

When the slot control code sent from the delay means 10 indicates an access to a character data address, the interface means 5 selects the character data address output from the character data address generation means 4, The memory address, RAS or CA,
A memory command signal such as S is transmitted. As a result SDR
It receives the data output from AM 1 and outputs character data to dot data control means 6.

FIG. 6 shows an example of the read access of the SDRAM 1 according to this embodiment when the code setting as shown in FIG. 5 is used. In the case of this setting example, the slot selecting means 8 of the bank 0 uses eight time slot periods T0
During the period from to T7, the codes set in the register 7 are output in the order of 0, F, F, F, 4, 4, 4, and 4. According to this setting example, one pattern name read (T0) for bank 0 during the display time (T0 to T7) for 8 dots, with the first surface being 16 bits / dot.
And (16 bits / dot) / 8 dots / 32 bits =
Four times of character data reading (T4 to T7) are executed.

Also, the number of display colors is 8 bits / dot for the second surface, and 4 bits / dot for both the third and fourth surfaces. For the bank 1 during the display time (T0 to T7), the second surface is One pattern name reading (T0) and (8
(Bits / dot) .8 dots / 32 bits = two times of character data reading (T1, T2) are executed.
The surface and the fourth surface are read out once (T
4, T6), (4 bits / dot), 8 dots / 32
Bit = 1 character data read (T5, T
7) is executed.

In the above embodiment, the display data in the character mode has been described. However, the display data in the bitmap mode is not generated by the pattern name address generating means 3 shown in FIG. A bitmap data address generating means is provided in place of the means 4.

Next, while the display data is being accessed in the bank split mode described above, the CPU
An embodiment in which random access is interrupted for screen rewriting or the like in the RAM 1 will be described with reference to FIG. SDR
The AM1 can perform not only a bank split mode but also a random access mode similar to a normal DRAM. For example, it is easy to completely separate the display period and the non-display period in time, and to execute random access during the non-display period. However, with such a control method, the number of slots that can respond to requests from the CPU decreases, and the CPU
Processing speed slows down when there are frequent requests from

FIG. 7 shows a circuit configuration of a control circuit portion for finding an empty slot and outputting an access permission signal to the CPU during the display operation period in the bank division mode described in the above embodiment. . Specifically, banks 0, 1
An access permission signal is output when two slots are free at the same time. Mode setting registers 71, 72, selector 8b of slot selecting means 8
1, 8b2 and the decoders 91 and 92 specifically show the configuration shown in FIG. 1, including the portion for bank 1 omitted in FIG.

In order to monitor the output of the mode setting register 7 in the bank split mode, two decoders 91 and 9 are used.
2 are provided with NOR gates G1 and G2, respectively. It is determined by these NOR gates G1 and G2 that a control code indicating that the banks 0 and 1 are not accessed is issued. The outputs of these NOR gates G1 and G2 are multiplied by an AND gate G3. Further, the output of the AND gate G3 is input to one input terminal of the AND gate G4, and is input to another input terminal via a delay element D that delays one slot. These gates G1 to G4 and the delay element D constitute an interrupt control circuit 20, and the output of the AND gate G4 is sent to the CPU as an access permission signal.

For example, the relationship between the control code of the access slot set by the register 7 and the access content is shown in FIG.
Suppose it was something like FIG. 9 shows a state in which the display mode is set by such a control code and an access permission signal is obtained during operation in the bank split mode. Decoder 91, with control code 7 (no access)
In the slot in which the outputs of 92 are all "0", the outputs of the NOR gates G1 and G2 are "1". AND gate G3
To obtain the "1" output in slots T4, T5 and T7 where both banks 0 and 1 are empty. Due to the product of this "1" output and a signal delayed by one slot, the output of AND gate G4 becomes "1" for slot T5.

As described above, when the two slots T4 and T5 that are not used for display access in both the banks 0 and 1 are continuous, a permission signal for permitting the CPU to access the interrupt is generated. You. As a result, the address and data can be input in the access slot T5 as shown by the broken line in FIG. Thus, according to this embodiment, access slots not used during the display period in the bank split mode can be released to the CPU. Therefore, even when the number of CPU slots increases and screen rewriting or the like is frequently required, high-speed operation can be performed as a whole.

[0036]

As described above, according to the present invention, S
The access mode in the DRAM bank division mode can be set by the mode setting means. The access mode can be arbitrarily set, and the display surface can be freely configured by, for example, applying to a display control device. Also, an output of the mode setting means is monitored to detect a vacancy of a predetermined number of access slots during a data read operation in the bank division mode, and an interrupt enable signal in the random access mode is output to the CPU. Thus, high-speed performance of various systems using the SDRAM can be realized by effectively utilizing the access slots.

[Brief description of the drawings]

FIG. 1 shows a configuration of an image display control device according to an embodiment of the present invention.

FIG. 2 shows a configuration of an SDRAM used in the embodiment.

FIG. 3 shows an access timing of the SDRAM.

FIG. 4 shows the display surface of the embodiment and the contents stored in the SDRAM.

FIG. 5 shows an example of code setting by a register of the embodiment.

FIG. 6 shows an example of data access of the SDRAM of the embodiment.

FIG. 7 shows a configuration of an access permission signal generation circuit of another embodiment.

FIG. 8 shows an example of control code setting by the register of the embodiment.

FIG. 9 is a timing chart of generation of an access permission signal according to the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... SDRAM, 2 ... Display coordinate generation means, 2a ... Scan counter, 2b ... Coordinate calculation means, 3 ... Pattern name address generation means, 4 ... Character data address generation means, 5 ... Memory interface means, 6 ... Dot data control Means 7, display mode setting register 8, memory access slot selecting means 9, decoder 10, delay means G1, G NOR gate, G3
G4: AND gate, D: delay element, 20: interrupt control circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 11/407 G11C 11/34 362S 371H

Claims (2)

(57) [Claims] 1. A bank division mode and a random access mode in which the interior is divided into at least two banks and precharge is executed individually, thereby enabling address input of each bank to be alternately continued without a gap. A mode setting means for periodically setting a data read operation mode in a bank division mode of the dynamic RAM in units of a predetermined number of access slots; and data set by the mode setting means. Address generation means for generating an address for accessing the dynamic RAM in accordance with a read operation mode; and a predetermined number of which the two banks are not accessed during a data read operation in a bank division mode by monitoring an output of the mode setting means. Access slots are continuous Interrupt control means for detecting the occurrence of the interrupt and outputting an interrupt enable signal in the random access mode. 2. A mode setting unit comprising: a register for setting an access mode for each access slot in a minimum time unit required to access one address of the dynamic RAM; and a slot selection unit for selecting a set value of the register. 2. The memory control device according to claim 1, further comprising: decoding means for decoding a set value selected by said slot selecting means and generating a control signal to said address generating means.