CN112272122A - FPGA accelerator card detection method and device and readable storage medium - Google Patents
FPGA accelerator card detection method and device and readable storage medium Download PDFInfo
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- CN112272122A CN112272122A CN202011099048.4A CN202011099048A CN112272122A CN 112272122 A CN112272122 A CN 112272122A CN 202011099048 A CN202011099048 A CN 202011099048A CN 112272122 A CN112272122 A CN 112272122A
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- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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Abstract
The embodiment of the invention provides a method and a device for detecting an FPGA accelerator card and a readable storage medium, wherein FPGA accelerator card detection variables are obtained, the FPGA accelerator card detection variables comprise slot position characterization variables and card state characterization variables, whether a slot position corresponding to the slot position characterization variables is the FPGA accelerator card or not is determined based on the slot position characterization variables and the card state characterization variables corresponding to the slot position characterization variables, whether the slot position corresponding to the slot position characterization variables is the FPGA accelerator card or not is determined based on the slot position characterization variables and the card state characterization variables corresponding to the slot position characterization variables, and the FPGA accelerator card and a common network card can be accurately distinguished when the FPGA accelerator card and the common network card are mixed and inserted for use.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for detecting an FPGA (field programmable gate array) accelerator card and a readable storage medium.
Background
The CPU (Central Processing Unit) and the network card of the conventional network hardware device have limited Processing performance, and especially appear to be very sensitive on the complex service Processing capability of a packet, so a special accelerator card hardware device is introduced to improve the forwarding performance of the network device, in which an FPGA (Field Programmable Gate Array) device belongs to a semi-custom circuit in an asic, is a Programmable logic Array, and is used in cooperation with the conventional network card and a special custom program, so that the FPGA accelerator card can be used as a common network card or an accelerator card, and supports mixed insertion with the common network card on a multi-slot device. However, when the FPGA accelerator card is inserted into a multi-slot device and used in a mixed manner with a common network card, the FPGA accelerator card cannot be distinguished and judged by naked eyes from the appearance.
Disclosure of Invention
In view of the above technical problems in the prior art, embodiments of the present invention provide a method and an apparatus for detecting an FPGA accelerator card, and a readable storage medium.
In a first aspect, an embodiment of the present invention provides a method for detecting an FPGA accelerator card, including:
acquiring FPGA accelerator card detection variables, wherein the FPGA accelerator card detection variables comprise slot position characterization variables and card state characterization variables;
and determining whether the slot position corresponding to the slot position characterization variable is an FPGA accelerator card or not based on the slot position characterization variable and a card state characterization variable corresponding to the slot position characterization variable.
Optionally, according to the FPGA accelerator card detection method of an embodiment of the present invention, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot position characterization variable.
Optionally, according to the FPGA accelerator card detection method of an embodiment of the present invention, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot position characterization variable, and specifically includes:
sending a message for inquiring the bit state of the FPGA accelerator card by a preset protocol to the interface of the slot position, and determining whether a response message of the same preset protocol is received;
and setting the card state characterization variables based on the confirmation result.
Optionally, according to the FPGA accelerator card detection method according to an embodiment of the present invention, the sending a preset protocol to the interface of the slot to query a bit state message of the FPGA accelerator card, and determining whether a response message of the same preset protocol is received includes:
sending a message for inquiring the on-site state of the FPGA accelerator card by a preset protocol to an interface of the slot position;
delaying preset time, and judging whether a response message of the same preset protocol is received or not;
if the response message is not received, circularly sending the message of inquiring the in-place state of the FPGA accelerator card by the preset protocol, and judging whether the response message is received or not after time delay until the response message is judged to be received or the preset cycle times are reached.
Optionally, according to the FPGA accelerator card detection method of an embodiment of the present invention, the FPGA accelerator card detection variable further includes an FPGA switch flag, and the FPGA switch flag is used to represent a switch state of an FPGA in the FPGA accelerator card.
Optionally, according to the FPGA accelerator card detection method of an embodiment of the present invention, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag.
Optionally, according to the FPGA accelerator card detection method of an embodiment of the present invention, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag, which specifically includes:
if the FPGA zone bit file exists, the FPGA switch marks 1 of all the interfaces corresponding to the slot position; if the FPGA zone bit file does not exist, the FPGA switch marks of all the interfaces corresponding to the slot position are set to be 0.
In a second aspect, an embodiment of the present invention further provides an FPGA accelerator card detection apparatus, including:
the FPGA accelerator card detection variable comprises a slot position characterization variable and a card state characterization variable;
and the FPGA accelerator card determining module is used for determining whether the slot position corresponding to the slot position characterization variable is the FPGA accelerator card or not based on the slot position characterization variable and the card state characterization variable corresponding to the slot position characterization variable.
In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the steps of the method provided in the first aspect.
In a fourth aspect, embodiments of the present invention also provide a non-transitory computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the method as provided in the first aspect above.
According to the FPGA accelerator card detection method, the FPGA accelerator card detection device and the readable storage medium provided by the embodiment of the invention, the FPGA accelerator card detection variables are obtained, the FPGA accelerator card detection variables comprise the slot position characterization variables and the card state characterization variables, and whether the slot position corresponding to the slot position characterization variables is the FPGA accelerator card or not is determined based on the slot position characterization variables and the card state characterization variables corresponding to the slot position characterization variables, so that the FPGA accelerator card and the common network card can be accurately distinguished when the FPGA accelerator card and the common network card are mixed and inserted for use.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for detecting an FPGA accelerator card according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an internal structure of an FPGA accelerator card according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an FPGA accelerator card detection apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, when the FPGA accelerator card and the common network card are used in a mixed insertion mode, the FPGA accelerator card cannot be distinguished and judged visually, and therefore the embodiment of the invention provides the FPGA accelerator card detection method. Fig. 1 is a schematic flow chart of a method for detecting an FPGA accelerator card according to an embodiment of the present invention, and as shown in fig. 1, the method includes:
and step 110, acquiring FPGA accelerator card detection variables, wherein the FPGA accelerator card detection variables comprise slot position characterization variables and card state characterization variables.
Specifically, the network equipment comprises a plurality of network equipment into which the common network card and/or the FPGA accelerator card are inserted, and when the system is initialized, the inserted FPGA accelerator card or the common network card interface is registered by a network card driver in the network equipment to monitor the state of the FPGA accelerator card and/or the common network card, so that the identification and subsequent data interaction are facilitated. Based on the method, FPGA accelerator card detection variables are added in a network port data structure, the FPGA accelerator card detection variables comprise a slot characterization variable FPGA _ slot and a card state characterization variable FPGA _ exist _ flag, the slot characterization variable FPGA _ slot and the card state characterization variable FPGA _ exist _ flag are used for monitoring the card state of each slot on network equipment, and the network equipment acquires the FPGA accelerator card detection variables and judges whether the inserted network card is the FPGA accelerator card according to the FPGA accelerator card detection variables.
And 120, determining whether the slot position corresponding to the slot position characterization variable is the FPGA accelerator card or not based on the slot position characterization variable and the card state characterization variable corresponding to the slot position characterization variable.
Specifically, the slot characterization variable fpga _ slot is used for setting and storing a relevant slot number according to a slot where the card is inserted, and the card state characterization variable fpga _ exist _ flag corresponding to the slot characterization variable is used for characterizing the card state of the slot corresponding to the slot characterization variable. The slot position card state comprises the following steps: the method comprises three types of operation modes, namely no network card is inserted (namely not in-place state), an ordinary network card is inserted (in-place state), and an FPGA accelerator card is inserted (in-place state). Based on the slot position characterization variable and the card state characterization variable corresponding to the slot position characterization variable, the network device may determine whether the slot position corresponding to the slot position characterization variable is an FPGA accelerator card.
According to the method provided by the embodiment of the invention, the FPGA accelerator card detection variables are obtained, the FPGA accelerator card detection variables comprise the slot position characterization variables and the card state characterization variables, and whether the slot position corresponding to the slot position characterization variables is the FPGA accelerator card or not is determined based on the slot position characterization variables and the card state characterization variables corresponding to the slot position characterization variables, so that the FPGA accelerator card and the common network card can be accurately distinguished when the FPGA accelerator card and the common network card are used in a mixed insertion manner.
Based on the above embodiment, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot state characterization variable.
Specifically, all interfaces of all slot positions are regarded as a common network card at the beginning of detection, the card state corresponding to the initial value of the card state representation variable FPGA _ exist _ flag is in an out-of-place state, and then the in-place state query result is replaced by the out-of-place state, the in-place state of the common network card or the in-place state corresponding to the FPGA accelerator card according to the in-place state query result of the FPGA accelerator card.
According to the method provided by the embodiment of the invention, the value of the card state characterization variable is determined through the in-place state query result of the FPGA accelerator card of the slot position corresponding to the slot position characterization variable, and whether the slot position corresponding to the slot position characterization variable is the FPGA accelerator card is determined based on the value of the card state characterization variable, so that the rapid identification of the FPGA accelerator card and a common network card can be realized.
Based on the above embodiment, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot state characterization variable, and specifically includes:
sending a message for inquiring the bit state of the FPGA accelerator card by a preset protocol to the interface of the slot position, and determining whether a response message of the same preset protocol is received;
and setting the card state characterization variables based on the confirmation result.
Specifically, as shown in fig. 2, an internal structure diagram of an FPGA accelerator card provided in an embodiment of the present invention is shown, where an external optical port of the FPGA is a physical interface of a panel of a network device, an internal interface is a network card drive registration interface such as XL710, an FPGA stores a customized logic program of the FPGA, and a DDR3 stores a program operation result, the FPGA accelerator card communicates with the network device through a preset protocol message, the network device sends a query message of a preset protocol to the FPGA accelerator card (i.e., a preset protocol query message of an on-bit state of the FPGA accelerator card), the FPGA accelerator card stores and returns a corresponding response message to the network device after parsing, and a common network card does not parse the query message of the preset protocol and does not reply the response message to the network device, and the FPGA accelerator card and the common network card can be distinguished and determined based: the network device creates a background thread at the final stage of system initialization completion and message receiving and sending, sends a preset protocol query FPGA acceleration card bit state message (such as 0x8888) to the interface of each slot position in the thread, and confirms whether a response message is received to set the card state representation variable, and based on the value of the card state representation variable, the FPGA acceleration card or the common network card can be judged.
If the current interface of the current slot receives a response message of the FPGA, setting FPGA _ exist _ flag to be 1, and judging that the slot insert card is an FPGA acceleration card; if the current interface of the current slot position does not receive any response message of the FPGA, setting FPGA _ exist _ flag to be 2, and judging that the slot position plug-in card is a common network card; it should be noted that, when the system is initialized, the network device will only register an interface for the inserted network card, and therefore, if it is determined that no interface is registered in the current slot, the default is an unplugged state (i.e., not in-bit state), the FPGA _ exist _ flag default value is set to 3, and it is not necessary to send the message for querying the bit state of the FPGA accelerator card through the preset protocol.
According to the method provided by the embodiment of the invention, the preset protocol is sent to the interface of the slot position to inquire the position state message of the FPGA accelerator card, whether the response message of the same preset protocol is received or not is confirmed, and the card state representation variable is set based on the confirmation result so as to judge whether the slot position is the FPGA accelerator card or the common network card, so that the FPGA accelerator card and the common network card can be accurately distinguished.
Based on the above embodiment, the sending a message of a preset protocol to the interface of the slot to query the status of the FPGA accelerator card, and determining whether a response message of the same preset protocol is received specifically includes:
sending a message for inquiring the on-site state of the FPGA accelerator card by a preset protocol to an interface of the slot position;
delaying preset time, and judging whether a response message of the same preset protocol is received or not;
if the response message is not received, circularly sending the message of inquiring the in-place state of the FPGA accelerator card by the preset protocol, and judging whether the response message is received or not after time delay until the response message is judged to be received or the preset cycle times are reached.
Specifically, in consideration of the robustness design, after the network device sends a preset protocol query FPGA acceleration card to the slot interface to delay the preset time to wait for the network card to return a response message, the detailed process is as follows: the network equipment assembles a preset protocol query FPGA accelerator card bit state message according to a fixed format corresponding to the preset protocol, a sending direction sends the preset protocol query FPGA accelerator card bit state message (such as 0x8888) and delays for a plurality of milliseconds, and a message receiving direction receives a response message of the same preset protocol, and then the FPGA _ exist _ flag is set to be 1.
If the response message is not received in time within the delay time, the operation is repeated, namely, the message of the in-place state of the FPGA acceleration card is sent again, and whether the response message is received or not is judged after the delay until the response message is judged to be received or the preset cycle number is reached. For example: if the response message is not received in time within the delay time, the operation is repeated for six times. Setting fpga _ exists _ flag to be 1 as long as a response message is received once within six times; if the response message is not received for six times, the situation that the response message of any FPGA is not received is indicated, FPGA _ exist _ flag is set to be 2, the slot is judged to be a common network card, other subsequent interfaces of the slot send the message of inquiring the FPGA accelerating card in the preset protocol before the message of inquiring the FPGA accelerating card in the bit state is judged, if the first interface of the slot is judged to be the common network card, the subsequent interfaces do not send the message of inquiring the FPGA accelerating card in the preset protocol, and the detection speed of other slot network cards is prevented from being influenced by unnecessary delay. Of course, the preset time and the preset cycle number may be adjusted according to actual needs, and this is not specifically limited in the embodiment of the present invention. It should be noted that, after receiving the response message, the network device may determine whether the response message is a response message (e.g., 0x8888) of the same preset protocol, and only when it is determined that the received response message is a response message of the same preset protocol, the loop may jump out, and set FPGA _ exist _ flag to 1, otherwise, the network device may send a message of querying the on-bit status of the FPGA accelerator card by using the preset protocol once every preset time interval.
The method provided by the embodiment of the invention comprises the steps of sending a message for inquiring the on-position state of the FPGA accelerator card by a preset protocol to an interface of the slot position, delaying the preset time, judging whether a response message of the same preset protocol is received or not, if the response message is not received, circularly sending the message for inquiring the on-position state of the FPGA accelerator card by the preset protocol, and judging whether the response message is received or not after delaying until the response message is judged to be received or the preset cycle number is reached, so that the accuracy of judging the FPGA accelerator card is ensured.
Based on the above embodiment, the FPGA accelerator card detection variable further includes an FPGA switch flag, and the FPGA switch flag is used for representing a switch state of an FPGA in the FPGA accelerator card.
Specifically, the FPGA accelerator card has two operating modes: and the FPGA is started to be used as an accelerator card and is not started to be used as a common network card. In order to further determine the working mode of the FPGA accelerator card, an FPGA switch mark FPGA _ open _ flag is added in the network port data structure, and the FPGA switch mark is used for representing the switch state of the FPGA in the FPGA accelerator card. The default initial state of the FPGA switch mark is an unknown state, and the FPGA accelerator card can be subsequently changed into an on state or an off state according to the detection result of the FPGA accelerator card, so that in the state of a slot position card, the state of the FPGA accelerator card can be subdivided into two states of turning on the FPGA to be used as the accelerator card and turning off the FPGA to be used as a common network card.
According to the method provided by the embodiment of the invention, the working mode of the FPGA accelerator card is further determined through the FPGA switch mark for representing the switch state of the FPGA in the FPGA accelerator card, and the working state of the FPGA accelerator card can be accurately judged.
Based on the above embodiment, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag.
Specifically, when the network device system is initialized, the relevant command line and the web interface can be registered and provided, the FPGA in the FPGA accelerator card is set to be turned on or off according to the slot, the flag bit file named according to the slot (for example, FPGA _ open _ slot1) is created or deleted in the background storage directory by the switching operation, and the FPGA switch flag of the internal interface is set: and setting all internal interface FPGA switch flags FPGA _ open _ flag at the slot position to be 1 when the slot position is started, writing the FPGA flag bit file to a disk directory, setting all internal interface FPGA switch flags FPGA _ open _ flag at the slot position to be 0 when the slot position is closed, and deleting the FPGA flag bit file.
And simultaneously, providing a echoing function of configuring the on-off state of the FPGA on the web interface: judging according to the card state of the slot position, if the slot position is not in the position state, turning the switch grey, and not allowing the opening and closing operation; and if the FPGA acceleration card is in the bit state, the operation of opening and closing is allowed, and the opening and closing state is displayed normally. The FPGA is opened and closed only once by operating for the first time, and the FPGA can keep the previous opening or closing state during subsequent initialization. Therefore, the setting of the FPGA switch flag of the slot internal interface can be performed only by judging whether the FPGA flag bit file (FPGA _ open _ slotx) of the slot exists in the disk directory.
According to the method provided by the embodiment of the invention, the value of the FPGA switch mark is determined through the FPGA mark bit file of the slot position corresponding to the FPGA switch mark, so that the value of the FPGA switch mark can be rapidly determined, and the FPGA switch state is further determined.
Based on the above embodiment, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag, which specifically includes:
if the FPGA zone bit file exists, the FPGA switch marks 1 of all the interfaces corresponding to the slot position; if the FPGA zone bit file does not exist, the FPGA switch marks of all the interfaces corresponding to the slot position are set to be 0.
Specifically, if the FPGA flag bit file exists, the FPGA flag bits FPGA _ open _ flag of all internal interfaces under the slot position are set to 1, and the FPGA is judged to be in an open state; and if the FPGA zone bit file does not exist, setting the FPGA zone bits FPGA _ open _ flag of all internal interfaces under the slot position to be 0, and judging that the FPGA is in a closed state. It is worth noting that for a slot in an out-of-bit state or a normal network card in-bit state, the FPGA flag FPGA _ open _ flag corresponding to the internal interface is defaulted to 0.
The network equipment can provide a query command line, determine the state of each slot card in the network equipment based on the slot characterization variable, the card state characterization variable and the FPGA switch mark, and display the content as the current equipment slot number and the state of each slot card: the FPGA accelerating card is divided into two states of opening the FPGA to be used as the accelerating card and closing the FPGA to be used as the common network card.
According to the method provided by the embodiment of the invention, if the FPGA zone bit file exists, the FPGA switch marks of all interfaces corresponding to the slot position are set to be 1; if the FPGA zone bit file does not exist, the FPGA switch marks of all the interfaces corresponding to the slot position are set to be 0, the value of the FPGA switch marks can be accurately determined, and the FPGA switch state is further determined.
Based on any of the above embodiments, fig. 3 is a schematic structural diagram of an FPGA accelerator card detection apparatus according to an embodiment of the present invention, and as shown in fig. 3, the apparatus includes:
and a detection variable obtaining module 310, configured to obtain FPGA accelerator card detection variables, where the FPGA accelerator card detection variables include a slot characterization variable and a card state characterization variable.
Specifically, the network equipment comprises a plurality of network equipment into which the common network card and/or the FPGA accelerator card are inserted, and when the system is initialized, the inserted FPGA accelerator card or the common network card interface is registered by a network card driver in the network equipment to monitor the state of the FPGA accelerator card and/or the common network card, so that the identification and subsequent data interaction are facilitated. Based on this, an FPGA accelerator card detection variable is added in the network port data structure, the FPGA accelerator card detection variable comprises a slot characterization variable FPGA _ slot and a card state characterization variable FPGA _ exist _ flag, and is used for monitoring the card state of each slot on the network equipment, and the detection variable acquisition module 310 acquires the FPGA accelerator card detection variable and judges whether the inserted network card is the FPGA accelerator card according to the FPGA accelerator card detection variable.
The FPGA accelerator card determining module 320 is configured to determine whether the slot corresponding to the slot characterizing variable is an FPGA accelerator card based on the slot characterizing variable and the card state characterizing variable corresponding to the slot characterizing variable.
Specifically, based on the slot characterization variable and the card state characterization variable corresponding to the slot characterization variable, the FPGA accelerator card determining module 320 may determine whether the slot corresponding to the slot characterization variable is the FPGA accelerator card.
According to the device provided by the embodiment of the invention, the FPGA accelerator card detection variables are obtained through the detection variable obtaining module, the FPGA accelerator card detection variables comprise the slot position characterization variables and the card state characterization variables, the FPGA accelerator card determining module determines whether the slot position corresponding to the slot position characterization variables is the FPGA accelerator card or not based on the slot position characterization variables and the card state characterization variables corresponding to the slot position characterization variables, and the FPGA accelerator card and the common network card can be accurately distinguished when the FPGA accelerator card and the common network card are mixed and inserted for use.
Based on the above embodiment, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot state characterization variable.
Based on the above embodiment, the value of the card state characterization variable is determined based on the in-place state query result of the FPGA accelerator card of the slot corresponding to the slot state characterization variable, and specifically includes:
sending a message for inquiring the bit state of the FPGA accelerator card by a preset protocol to the interface of the slot position, and determining whether a response message of the same preset protocol is received;
and setting the card state characterization variables based on the confirmation result.
Based on the above embodiment, the sending a message of a preset protocol to the interface of the slot to query the status of the FPGA accelerator card, and determining whether a response message of the same preset protocol is received specifically includes:
sending a message for inquiring the on-site state of the FPGA accelerator card by a preset protocol to an interface of the slot position;
delaying preset time, and judging whether a response message of the same preset protocol is received or not;
if the response message is not received, circularly sending the message of inquiring the in-place state of the FPGA accelerator card by the preset protocol, and judging whether the response message is received or not after time delay until the response message is judged to be received or the preset cycle times are reached.
Based on the above embodiment, the FPGA accelerator card detection variable further includes an FPGA switch flag, and the FPGA switch flag is used for representing a switch state of an FPGA in the FPGA accelerator card.
Based on the above embodiment, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag.
Based on the above embodiment, the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag, which specifically includes:
if the FPGA zone bit file exists, the FPGA switch marks 1 of all the interfaces corresponding to the slot position; if the FPGA zone bit file does not exist, the FPGA switch marks of all the interfaces corresponding to the slot position are set to be 0.
The FPGA accelerator card detection apparatus provided in the embodiment of the present invention can execute the FPGA accelerator card detection method, and the specific working principle and the corresponding technical effect thereof are the same as those of the method embodiment, and are not described herein again.
Fig. 4 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 4: a processor (processor)410, a communication Interface 420, a memory (memory)430 and a communication bus 440, wherein the processor 410, the communication Interface 420 and the memory 430 are communicated with each other via the communication bus 440. Processor 410 may invoke logic instructions in memory 430 to perform the flow of steps provided by the above-described method embodiments.
In addition, the logic instructions in the memory 430 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the flow of steps provided by the foregoing method embodiment.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A FPGA accelerator card detection method is characterized by comprising the following steps:
acquiring FPGA accelerator card detection variables, wherein the FPGA accelerator card detection variables comprise slot position characterization variables and card state characterization variables;
and determining whether the slot position corresponding to the slot position characterization variable is an FPGA accelerator card or not based on the slot position characterization variable and a card state characterization variable corresponding to the slot position characterization variable.
2. The FPGA accelerator card detection method of claim 1, wherein the value of the card state characterization variable is determined based on the slot FPGA accelerator card in-place state query result of the slot corresponding to the slot characterization variable.
3. The FPGA accelerator card detection method according to claim 2, wherein the value of the card state characterization variable is determined based on a slot FPGA accelerator card in-place state query result of a slot corresponding to the slot characterization variable, and specifically includes:
sending a message for inquiring the bit state of the FPGA accelerator card by a preset protocol to the interface of the slot position, and determining whether a response message of the same preset protocol is received;
and setting the card state characterization variables based on the confirmation result.
4. The FPGA accelerator card detection method according to claim 3, wherein the sending a preset protocol to the interface of the slot to query a status message of the FPGA accelerator card, and determining whether a response message of the same preset protocol is received specifically includes:
sending a message for inquiring the on-site state of the FPGA accelerator card by a preset protocol to an interface of the slot position;
delaying preset time, and judging whether a response message of the same preset protocol is received or not;
if the response message is not received, circularly sending the message of inquiring the in-place state of the FPGA accelerator card by the preset protocol, and judging whether the response message is received or not after time delay until the response message is judged to be received or the preset cycle times are reached.
5. The FPGA accelerator card detection method of claim 1, wherein the FPGA accelerator card detection variables further comprise FPGA switch flags, and the FPGA switch flags are used for characterizing the switch state of the FPGA in the FPGA accelerator card.
6. The FPGA accelerator card detection method of claim 5, wherein the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag.
7. The FPGA accelerator card detection method according to claim 6, wherein the value of the FPGA switch flag is determined based on the FPGA flag bit file of the slot corresponding to the FPGA switch flag, and specifically comprises:
if the FPGA zone bit file exists, the FPGA switch marks 1 of all the interfaces corresponding to the slot position; if the FPGA zone bit file does not exist, the FPGA switch marks of all the interfaces corresponding to the slot position are set to be 0.
8. The utility model provides a FPGA accelerator card detection device which characterized in that includes:
the FPGA accelerator card detection variable comprises a slot position characterization variable and a card state characterization variable;
and the FPGA accelerator card determining module is used for determining whether the slot position corresponding to the slot position characterization variable is the FPGA accelerator card or not based on the slot position characterization variable and the card state characterization variable corresponding to the slot position characterization variable.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the steps of the FPGA accelerator card detection method according to any one of claims 1 to 7 are implemented when the program is executed by the processor.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of the FPGA accelerator card detection method according to any one of claims 1 to 7.
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