CN103888688A - Time sequence generating device for driving charge coupled device - Google Patents
Time sequence generating device for driving charge coupled device Download PDFInfo
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Abstract
The invention relates to a time sequence generating device for driving a charge coupled device, which comprises a singlechip, an active crystal oscillator and a field programmable gate array, wherein the active crystal oscillator is connected with the input end of the field programmable gate array and provides a clock signal for the field programmable gate array; the single chip microcomputer sequentially accesses a parameter register array in the field programmable gate array through a data bus and an address bus to complete device initialization and provide all parameters needing to be set on site for the field programmable gate array; the input end of the field programmable logic gate array is connected with the output end of the single chip microcomputer, data exchange between the internal parameter register array of the field programmable logic gate array and the single chip microcomputer is achieved, and the field programmable logic gate array generates and outputs horizontal and vertical driving signals, related double sampling and analog-to-digital conversion driving signals and image output timing sequence signals according to parameters of the internal parameter register array.
Description
Technical field
The invention belongs to low-light level imaging technical field, relate to a kind of general electron multiplication charge coupled cell and drive sequential generating means, the sequential generating process while being mainly used in charge-coupled device camera design.
Background technology
Electron multiplication charge coupled device (Electron Multiplying Charge Couple Device, EMCCD) be the new technology occurring in charge coupled device (CCD) field nearly ten years, it is separately integrated hundreds of grades of electron multiplication registers on silicon chip, utilizing high voltage electric field that adjacent two grids form to be read out amplifier at signal electron amplifies signal electron more than 1000 times before being converted to signal voltage, thereby noise after the gain that suppresses to introduce due to sense amplifier and circuit noise, obtain very high sensitivity, be particularly suitable for low-light level imaging.CCD than tradition with image intensifier, its structure and volume are simplified greatly, have greater advantage in the application scenario of some weight and volume sensitivity.
The timing sequencer of CCD is the brain of whole CCD camera, it controlling charge packet generation, collection, shift, read, quantizing process, be the requisite core of camera.At present, driving sequential generating means for CCD mainly contains two kinds: the special integrated timing sequencer of CCD and employing programmable gate array device designed, designed generator, the former has, and integrated level is high, speed is fast, low in energy consumption, phase control precision advantages of higher, but the drive source way that it can provide is less, often can not meet some application requirements that drive way CCD more, and apply dumb, do not there is versatility, when the different CCD of each design, need to reselect driving timing sequencer, design efficiency is low; Adopt the method for programmable gate array device generation CCD clock signal very flexible, can produce according to actual needs more drive source way, there is good versatility and can reusing, but due to needs designed, designed, higher to designer's oneself requirement, there is certain challenge.
Electron multiplication charge coupled device is a kind of special frame transfer type charge coupled cell, relatively normal frames transfevent CCD the is many electron multiplication register of hundreds of level, and therefore sequencing control is also more complicated.Charge coupled device taking model as CCD201 is example, its horizontal transfer drives needs 6 tunnels, vertical transitions drives needs 8 tunnels, need at least 14 roads to drive signal, and more than the total way of some multichannel output type charge coupled device even reaches Liao20 road, existing Special integrated CCD driver cannot meet application requirements at all.For reaching versatility object, the best way is to adopt programmable gate array design charge coupled device to drive the mode of sequential to solve the timing sequencer problem of charge coupled device.
Summary of the invention
(1) technical problem solving
Cannot meet the requirement of charge coupled device to drive source quantity for existing charge coupled device Special integrated timing sequencer, and use dumb, lack the shortcoming of versatility, invented a kind of realize based on field programmable gate array (FPGA) for driving the sequential generating means of charge coupled cell.
(2) technical scheme
The invention provides a kind of for driving the sequential generating means of charge coupled device, mainly comprise single-chip microcomputer, active crystal oscillator and field programmable gate array, wherein: active crystal oscillator is connected with field programmable gate array input, for field programmable gate array provides clock signal; Single-chip microcomputer is accessed the parameter register array of field programmable gate array inside successively by data/address bus and address bus, finishing device initialization, based on the actual application requirements for field programmable gate array provides all on-the-spot parameters of setting that need; The input of field programmable gate array is connected with single-chip microcomputer output, receive the needed parameter of the inner modules of field programmable gate array of single-chip microcomputer output, and generate and export horizontal drive signals, vertical driving signal, correlated-double-sampling and analog-to-digital conversion driving signal and image output timing signal according to the parameter of inner parameter register array.
(3) beneficial effect
The present invention is intended to solve existing CCD Special integrated sequential generation module cannot meet the requirement of frame transfer type charge coupled cell to drive source quantity, and use dumb, the defect that lacks versatility, the present invention is with respect to CCD Special integrated sequential generation module, and tool has the following advantages:
The parameter that this device arranges the inner sequential generation of FPGA module by single-chip microcomputer is deposited module, can realize according to concrete charge coupled device object the flexible customization of Dui Mei road drive source frequency, phase place, duty ratio, has good versatility;
This device can provide the 30 above drive sources in road, has good versatility and can reusing, and the sequential generation module that is suitable as very much frame transfer type charge coupled cell or other large area array CCDs that drive ways produces and drives clock signal more.Frequency, phase place, the duty ratio of Ke Duimei road drive source are controlled flexibly, and phase adjusted resolution is to 1.85ns, maximum drive frequency can reach 54MHz, can meet the application requirements of current all kinds of special CCD to sequential generation module, produce driving clock signal such as being suitable as very much the sequential generation module of electron multiplication charge coupled device and other large area array CCDs that drive way more.
Adopt field programmable gate array (FPGA) to realize, there is extraordinary portability and can reusing.
Brief description of the drawings
Fig. 1 is that the present invention is for driving the sequential generating means structure composition frame chart of charge coupled device;
Fig. 2 is the state machine of main controller module of the present invention inside;
Fig. 3 is that electron multiplication charge coupled device 2 × 2 pixels merge (BIN) pattern output principle and sequential chart.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention be directed to the embodiment of charge coupled device (CCD), described charge coupled device is surface array charge-coupled device, those skilled in the art are by the following examples of the present invention, can realize and relate to the sequential generating means that drives arbitrary surface array charge-coupled device, only introduce embodiment as an example of the sequential generating means of electron multiplication charge coupled device in driven CCD camera example below:
The sequential generating means for driving electron multiplication charge coupled device (EMCCD) as Fig. 1 illustrates the present invention, this device mainly comprises single-chip microcomputer (MCU), active crystal oscillator and field programmable gate array (FPGA), wherein: active crystal oscillator is connected with field programmable gate array input, for field programmable gate array provides clock signal; Single-chip microcomputer is accessed the parameter register array of field programmable gate array inside successively by data/address bus and address bus, finishing device initialization, based on the actual application requirements for field programmable gate array provides all on-the-spot parameters of setting that need; The input of field programmable gate array is connected with single-chip microcomputer output, receive the needed parameter of the inner modules of field programmable gate array of single-chip microcomputer output, and generate and export to drive horizontal drive signals, vertical driving signal, correlated-double-sampling and the analog-to-digital conversion of the magazine electron multiplication charge coupled device of EMCCD to drive signal and image output timing signal according to the parameter of inner parameter register array.
Described field programmable gate array inside comprises data communication interface module, parameter register array module, digital dock manager module, main controller module, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion drive generator module, image output timing generator module, wherein: the input of communication interface modules respectively with single-chip microcomputer output, the data terminal of parameter register array, the output of digital dock administration module connects, assist single-chip microcomputer to complete the access to the arbitrary register in field programmable gate array inside, realize the independent configuration of each the road source driving signal to field programmable gate array output, the input of digital dock manager module is connected with the output of active crystal oscillator, clock signal to active crystal oscillator input is carried out frequency multiplication, phase-locked, generate high frequency clock signal drives generator module and image output timing generator module master clock signal as main controller module, communication interface modules, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, control the timing synchronization between modules, the output of digital dock manager module drives the input of generator module, image output timing generator module to be connected with communication interface modules, main controller module, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, communication interface modules receives the high frequency master clock signal of digital dock manager module output, the data that single-chip microcomputer is sended over are carried out simultaneous decoding, and corresponding registers in write parameters register array, main controller module, horizontal drive signals generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion drive generator module, image output timing generation module to receive the high frequency master clock signal of digital dock manager module output, drive module described in each to produce corresponding action, the input of main controller module is connected with the output of communication interface modules output, parameter register array module, the supplemental characteristic of the control signal of received communication interface module output and the output of parameter register array, control the running of main controller module internal state machine, main controller module output drives generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion to drive the control signal of generator module and image output timing generator module for level of control, the input of horizontal drive generator module is connected with the output of main controller module, for receiving horizontal control signal, and generates and export horizontal drive signals according to control signal content, the input of vertical drive generator module is connected with the output of main controller module, for receiving vertical control signal, and generates and export vertical driving signal according to control signal content, correlated-double-sampling and analog-to-digital conversion drive the input of generator module and the output of main controller module to be connected, be used for receiving correlated-double-sampling and analog-to-digital conversion control signal, and generate and export correlated-double-sampling and analog-to-digital conversion driving signal according to control signal content, the input of image output timing generator module is connected with the output of main controller module, for receiving image timing control signal, and generates and output image sequential driving signal according to control signal content.
Described parameter register array module comprises frequency parameter register, phase parameter register, duty cycle parameters register, programmable gate array inside is respectively equipped with frequency parameter register to the source driving signal of each road output at the scene, phase parameter register, duty cycle parameters register, and be provided with and driven the population parameter register of electron multiplication charge coupled device to comprise: total line number parameter register, effectively line number parameter register, total columns parameter register, effectively columns parameter register, time for exposure parameter register, synchronous mode parameter register, output mode parameter register, pixel merges parameter register.
Use single-chip microcomputer to drive the source driving signal of electron multiplication charge coupled device grid to carry out corresponding parameter register initial setting up to each road of output, realize the complete control to this source driving signal characteristic.
Described main controller module to wiping fast in electron multiplication charge coupled device imaging process, exposure, the preparation of charge packet vertical transitions, charge packet vertical transitions, the invalid electric charge of level empty, charge packet horizontal transfer, charge packet signal amplifies, charge packet is read Process Design state machine, level of control drives generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion to drive generator module and image output timing generator module under electron multiplication charge coupled device different operating state, to produce corresponding driving signal.
Described horizontal drive generator module produces one group of strict sequential of the needed relation of charge packet horizontal transfer under main controller module control, while transfer, close horizontal drive generator module, reduce rear class driver module power consumption, for improving the reliability of whole EMCCD camera electronic system;
Described vertical drive generator module produces one group of strict sequential of the needed relation of charge packet vertical transitions under main controller module control, while transfer, close vertical drive generator module, reduce rear class driver module power consumption, for improving the reliability of whole EMCCD camera electronic system;
Described correlated-double-sampling and analog-to-digital conversion drive generator module under main controller module control, to complete the analog signal that the front end preliminary treatment of electron multiplication charge coupled device is read to amplifying circuit to carry out correlated-double-sampling processing, eliminate reset noise, and control correlated-double-sampling and analog-to-digital conversion and drive and module occurs the image representing with analog signal is converted to digital picture.
The digital picture generating after the number conversion of described image output timing generator module mating die provides clock signal, so that Digital Image Transmission is arrived this device outside by CameraLink interface circuit.
After EMCCD camera powers on, first by a global reset signal of FPGA inside, all modules in FPGA inside are resetted, enter an initial condition, single-chip microcomputer is accessed the parameter register array of FPGA inside successively by data/address bus and address bus afterwards, concrete property for the CCD object of practical application carries out parameter setting to all related registers, completes the initialization of this sequential generating means.
External active crystal oscillator is for FPGA provides the clock of a road 27MHz, by DCM module, this clock signal carried out to 10 times of phase-locked amplifications after entering FPGA, obtains the stable 270MHz system dominant frequency clock CLK in a road and reverse clock CLKN thereof;
Single-chip microcomputer is mainly to provide a data path for communicating by letter between single-chip microcomputer and FPGA with the communication interface modules of FPGA, complete the exchanges data between single-chip microcomputer and internal hardware module, implementation is: the address signal to single-chip microcomputer in interface communication module, reading and writing data signal carries out Real-Time Monitoring, in the time that FPGA detects that single-chip microcomputer address signal is effective, address date in latch address bus immediately, afterwards when monitoring again single-chip microcomputer read-write when effective, again the data on data/address bus are carried out to latch, and the address of all parameter registers in the address being latched and FPGA inner parameter register array module is compared one by one, the parameter register module that data are write direct identical with latch address, complete the access to parameter register module,
The state machine of main controller module of the present invention inside as shown in Figure 2, main controller module is the core of whole sequential generation module, design a state machine according to the course of work of electron multiplication charge coupled device, this state machine has 8 states, as shown in Figure 2, mainly divide according to the course of work of electron multiplication charge coupled device, the time that each state machine is gone through is mainly to calculate by a public down counter, under each state, in the time that the value of this down counter is decremented to 0 from initial value, enter immediately next state:
1. idle condition: idle condition is not done any action.After receiving the internal reset signal of field programmable gate array or previous frame image transfer, state machine enters immediately idle condition, and the quick sassafras of next state is set immediately except the going through the time of state (public down counter initial value is set), wait for that common counter is decremented to 0, once be that instruction is taken in 0 inter-sync of just sending EMCCD camera, or under synchronous regime, receive the outer synchronous instruction of taking outside, once receive instruction, enter immediately next state;
2. quick erase status: wiping is fast before electron multiplication charge coupled device exposes, the noise charge of CCD imaging area and memory block to be transferred to and rushed down lotus raceway groove, empty the invalid electric charge of all potential wells, avoid these electric charges to affect effective photoproduction charge generation, noise decrease electronics.Once main controller module receives shooting instruction under idle condition, enter immediately quick sassafras except state, first going through the time of NextState exposure status be set, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state;
3. exposure status: under exposure status, electron multiplication charge coupled device is collected the useful signal electronics being produced by photoelectric effect, and adopt potential barrier to keep apart the charge packet in neighbor potential well; Main controller module enters immediately exposure status after quick sassafras is decremented to 0 except the common counter of state, first NextState is set and shifts going through the time of standby condition, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state.
4. shift standby condition: when after end exposure, need to wait for a period of time, to reserve time enough, light induced electron be flowed in its nearest potential well, avoid effective charge not fall into potential well completely and the image blurring and transfer efficiency decline that causes; Main controller module enters immediately transfer standby condition after the common counter of exposure status is decremented to 0, first going through the time of NextState vertical transitions state be set, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state;
5. vertical transitions state: need the signal electron image that photosensitive area is produced to transfer to rapidly memory block under this state, the memory block of electron multiplication charge coupled device is consistent with photosensitive area scale and have photomask, can prevent the interference of spuious photon to effective electron image; Main controller module enters immediately vertical transitions state after the common counter that shifts standby condition is decremented to 0, first NextState level is set and empties going through the time of state, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state;
6. level empties state: level empties state and the noise electronics that falls into horizontal transfer when the vertical transitions and deposit inside modules shifted clean, avoids sneaking in effective charge bag in the time shifting the first row signal charge the phenomenon that causes the first row noise to increase; Main controller module after the common counter of vertical transitions state is decremented to 0 immediately the level of entering empty state, first going through the time of next state line transfering state be set, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state;
7. row transfering state: row transfering state is transferred to horizontal transfer by a line charge packet that closes on horizontal transfer and deposit module and deposited in module, shifts to carry out the horizontal serial of signal charge bag; After being decremented to 0, the common counter that main controller module empties state in level enters immediately row transfering state, first going through the time of NextState horizontal transfer state be set, just export afterwards 8 conditional codes and drive generator module and image output timing generator module to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, modules produces the corresponding signal that drives according to current state machine state; When common counter is decremented to 0, just enter next state;
8. horizontal transfer state: when completing after row transfer, horizontal transfer is deposited and in module, has been had the effective signal charge of a line, now need that these electric charges are transferred to electron multiplication one by one successively and deposit the amplification of module settling signal electric charge, transfer to and read in amplification module, settling signal electric charge is to the conversion of signal voltage.Main controller module is expert at after the common counter of transfering state is decremented to 0 and is entered immediately horizontal transfer state, first judge whether current line is last column of CCD, if NextState is set to idle condition, otherwise NextState is set to row transfering state, going through the time of NextState is just set afterwards, just export afterwards 8 conditional codes to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion drive generator module and image output timing generator module, modules produces the corresponding signal that drives according to current state machine state, when common counter is decremented to 0, just enter next state,
Above 8 states are in sequence, once enter quick erase status, will sequentially experience all 8 states until all charge packets are all migrated out to CCD, the time that each state is gone through deposits module value according to parameters and estimates and write common counter, once experience the time of place state, enter immediately next state, complete next step operation.
Horizontal drive generator module judges the current residing state of electron multiplication charge coupled device according to 8 conditional codes of main controller module state machine output, and then produce one group of horizontal transfer driving signal taking pixel as transfer unit: above-mentioned 5,6, under 8 states, deposit block configuration according to the parameter of each road source driving signal self and produce square-wave pulse signal, with the horizontal transfer of control signal charge packet; Under other states, according to actual conditions or set high, or drag down, do not produce square-wave pulse signal, to reduce system power dissipation;
Vertical drive generator module judges the current residing state of electron multiplication charge coupled device according to 8 conditional codes of main controller module state machine output, produce one group of vertical transitions with behavior transfer unit and drive signal: above-mentioned 5, under 7 states, deposit block configuration according to the parameter of each road source driving signal and produce square-wave pulse signal, with the vertical transitions of control signal charge packet; Under other states, according to actual conditions or set high, or drag down, do not produce square-wave pulse signal, to reduce system power dissipation;
Correlated-double-sampling and analog-to-digital conversion drive generator module to judge the current residing state of electron multiplication charge coupled device according to 8 conditional codes of main controller module state machine output, produce one group of driving signal taking pixel as unit: as follow-up CCD pre-process circuit provides corresponding correlated-double-sampling pulse signal and analog-to-digital conversion enabling signal, analog voltage signal is converted to digital signal;
Image output timing generator module judges the current residing state of electron multiplication charge coupled device according to 8 conditional codes of main controller module state machine output, and output frame useful signal FVAL, row useful signal LVAL, pixel useful signal PVALID, for the digital picture after analog-to-digital conversion is added corresponding data format, so that follow-up CameraLink interface circuit arrives Digital Image Transmission beyond EMCCD camera.
For 2 × 2 pixels of realizing EMCCD camera merge (BIN) patterns output, adopt the method for electron multiplication charge coupled device pixel merging patterns output principle and sequential chart as shown in Figure 3.In the time that pixel merging output mode is activated, first read pixel and merge the numerical value 2 of depositing in module, Fig. 3 (a) is vertical pixel merging schematic diagram, wherein a, b is the charge packet of adjacent two row of row second from the bottom in electron multiplication charge coupled device, c, and d is the charge packet of adjacent two row of row last in electron multiplication charge coupled device, SG is level summation grid, and arrow represents the shift direction of charge packet; Fig. 3 (b) is horizontal pixel merging schematic diagram, and arrow represents charge packet shift direction; Fig. 3 (c) is the time program process that 2 × 2 pixels merge, S1, S2 is row clock transfer gate, R1, R2 and R3 are horizontal clock transfer gate, SG is level summation grid, and RST is reset gate, is divided into three sequential stages: exposure, vertical direction pixel merge, horizontal direction pixel merges.In the vertical direction under pixel merging phase, corresponding to the vertical direction pixel merging phase of Fig. 3 (a) and Fig. 3 (c), first send continuously two vertical transitions pulses to row clock transfer gate S1 and S2, by the pixel a of two row reciprocal on electron multiplication charge coupled device, b, c, d merges in corresponding horizontal transfer register and forms a+c, two of b+d merge pixel, complete the pixel union operation of vertical direction; Carry out again afterwards horizontal transfer, corresponding to the horizontal direction pixel merging phase of Fig. 3 (b) and Fig. 3 (c), first to R1, R2, R3 horizontal drive grid sends Continuous Drive pulse signal, drive pixel to enter successively summation grid, and summation grid SG carries out sum operation one time at interval of a high impulse of 2 pixel clocks transmissions, reset gate RST sends a high impulse reset CCD sense amplifier every 2 pixel clocks, thereby completes the pixel union operation of horizontal direction.
The above; it is only the embodiment in the present invention; but protection scope of the present invention is not limited to this; any people who is familiar with this technology is in the disclosed technical scope of the present invention; can understand conversion or the replacement expected; all should be encompassed in of the present invention comprise scope within, therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (9)
1. for driving a sequential generating means for charge coupled device, it is characterized in that: mainly comprise single-chip microcomputer, active crystal oscillator and field programmable gate array, wherein:
Active crystal oscillator is connected with field programmable gate array input, for field programmable gate array provides clock signal;
Single-chip microcomputer is accessed the parameter register array of field programmable gate array inside successively by data/address bus and address bus, finishing device initialization, based on the actual application requirements for field programmable gate array provides all on-the-spot parameters of setting that need;
The input of field programmable gate array is connected with single-chip microcomputer output, receive the needed parameter of the inner modules of field programmable gate array of single-chip microcomputer output, and generate and export horizontal drive signals, vertical driving signal, correlated-double-sampling and analog-to-digital conversion driving signal and image output timing signal according to the parameter of inner parameter register array.
2. according to claim 1 for driving the sequential generating means of charge coupled device, it is characterized in that: field programmable gate array inside comprises data communication interface module, parameter register array module, digital dock manager module, main controller module, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion and drives generator module, image output timing generator module, wherein:
The input of communication interface modules is connected with the data terminal of single-chip microcomputer output, parameter register array, the output of digital dock administration module respectively, assist single-chip microcomputer to complete the access to the arbitrary register in field programmable gate array inside, realize the independent configuration of each the road source driving signal to field programmable gate array output;
The input of digital dock manager module is connected with the output of active crystal oscillator, clock signal to active crystal oscillator input is carried out frequency multiplication, phase-locked, generate high frequency clock signal drives generator module and image output timing generator module master clock signal as main controller module, communication interface modules, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, control the timing synchronization between modules;
The output of digital dock manager module drives the input of generator module, image output timing generator module to be connected with communication interface modules, main controller module, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion, communication interface modules receives the high frequency master clock signal of digital dock manager module output, the data that single-chip microcomputer is sended over are carried out simultaneous decoding, and corresponding registers in write parameters register array; Main controller module, horizontal drive signals generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion drive generator module, image output timing generation module to receive the high frequency master clock signal of digital dock manager module output, drive module described in each to produce corresponding action;
The input of main controller module is connected with the output of communication interface modules output, parameter register array module, the supplemental characteristic of the control signal of received communication interface module output and the output of parameter register array, control the running of main controller module internal state machine, main controller module output drives generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion to drive the control signal of generator module and image output timing generator module for level of control;
The input of horizontal drive generator module is connected with the output of main controller module, for receiving horizontal control signal, and generates and export horizontal drive signals according to control signal content;
The input of vertical drive generator module is connected with the output of main controller module, for receiving vertical control signal, and generates and export vertical driving signal according to control signal content;
Correlated-double-sampling and analog-to-digital conversion drive the input of generator module and the output of main controller module to be connected, be used for receiving correlated-double-sampling and analog-to-digital conversion control signal, and generate and export correlated-double-sampling and analog-to-digital conversion driving signal according to control signal content;
The input of image output timing generator module is connected with the output of main controller module, for receiving image timing control signal, and generates and output image sequential driving signal according to control signal content.
3. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: parameter register array module comprises frequency parameter register, phase parameter register, duty cycle parameters register, programmable gate array inside is respectively equipped with frequency parameter register to the source driving signal of each road output at the scene, phase parameter register, duty cycle parameters register, and be provided with and driven the population parameter register of charge coupled device to comprise: total line number parameter register, effectively line number parameter register, total columns parameter register, effectively columns parameter register, time for exposure parameter register, synchronous mode parameter register, output mode parameter register, pixel merges parameter register.
4. according to claim 3 for driving the sequential generating means of charge coupled device, it is characterized in that: use single-chip microcomputer to drive the source driving signal of charge coupled device grid to carry out corresponding parameter register initial setting up to each road of output, realize the complete control to this source driving signal characteristic.
5. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: main controller module is to wiping fast in charge coupled device imaging process, exposure, charge packet vertical transitions is prepared, charge packet vertical transitions, the invalid electric charge of level empties, charge packet horizontal transfer, charge packet signal amplifies, the Process Design state machine that charge packet is read, level of control drives generator module, vertical drive generator module, correlated-double-sampling and analog-to-digital conversion drive generator module and image output timing generator module under charge coupled device different operating state, to produce the corresponding signal that drives.
6. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: horizontal drive generator module produces one group of needed sequential of charge packet horizontal transfer under main controller module control, closes horizontal drive generator module while transfer.
7. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: vertical drive generator module produces one group of needed sequential of charge packet vertical transitions under main controller module control, closes vertical drive generator module while transfer.
8. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: correlated-double-sampling and analog-to-digital conversion drive generator module under main controller module control, to complete the analog signal that the front end preliminary treatment of charge coupled device is read to amplifying circuit to carry out correlated-double-sampling processing, eliminate reset noise, and control correlated-double-sampling and analog-to-digital conversion and drive and module occurs the image representing with analog signal is converted to digital picture.
9. according to claim 2 for driving the sequential generating means of charge coupled device, it is characterized in that: the digital picture generating after the number conversion of image output timing generator module mating die provides clock signal, so that Digital Image Transmission is arrived this device outside by CameraLink interface circuit.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104394333A (en) * | 2014-11-26 | 2015-03-04 | 中国科学院国家天文台南京天文光学技术研究所 | Control system of CCD drive in South Pole Telescope |
| CN104469196A (en) * | 2014-11-26 | 2015-03-25 | 哈尔滨工程大学 | Drive device for image collecting system of interline transfer CCD sensor |
| CN104796640A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Multifunctional column sequence control circuit of oversized area-array CMOS (complementary metal oxide semiconductor) image sensor |
| CN105407274A (en) * | 2015-11-02 | 2016-03-16 | 深圳怡化电脑股份有限公司 | Method for achieving image acquisition by utilizing FPGA |
| CN106791499A (en) * | 2016-11-22 | 2017-05-31 | 北京空间机电研究所 | A kind of method for realizing improving electron multiplication CCD camera output image signal to noise ratio |
| CN106791505A (en) * | 2016-12-29 | 2017-05-31 | 中国科学院西安光学精密机械研究所 | Time sequence generator and time sequence driving method for two-channel CCD imaging system |
| CN110516810A (en) * | 2019-08-29 | 2019-11-29 | 合肥本源量子计算科技有限责任公司 | A kind of processing method, device, storage medium and the electronic device of quantum program |
| CN111405208A (en) * | 2020-03-20 | 2020-07-10 | 中国电子科技集团公司第四十四研究所 | Internally frame transferred CCD |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101839768A (en) * | 2010-05-14 | 2010-09-22 | 浙江工业大学 | Portable fiber-optic spectrometer based on CPLD and LABVIEW |
| US20100283882A1 (en) * | 2009-05-08 | 2010-11-11 | Photon Etc., Inc. | Apparatus and method for low noise imaging |
-
2014
- 2014-03-20 CN CN201410106542.7A patent/CN103888688B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100283882A1 (en) * | 2009-05-08 | 2010-11-11 | Photon Etc., Inc. | Apparatus and method for low noise imaging |
| CN101839768A (en) * | 2010-05-14 | 2010-09-22 | 浙江工业大学 | Portable fiber-optic spectrometer based on CPLD and LABVIEW |
Non-Patent Citations (2)
| Title |
|---|
| 王明富，杨世洪，吴钦章，夏默: "一种高帧频EMCCD驱动电路设计", 《光电工程》 * |
| 王明富，杨世洪，吴钦章: "大面阵CCD图像实时显示系统的设计", 《光学精密工程》 * |
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| CN104469196A (en) * | 2014-11-26 | 2015-03-25 | 哈尔滨工程大学 | Drive device for image collecting system of interline transfer CCD sensor |
| CN104796640A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Multifunctional column sequence control circuit of oversized area-array CMOS (complementary metal oxide semiconductor) image sensor |
| CN105407274A (en) * | 2015-11-02 | 2016-03-16 | 深圳怡化电脑股份有限公司 | Method for achieving image acquisition by utilizing FPGA |
| CN105407274B (en) * | 2015-11-02 | 2018-08-24 | 深圳怡化电脑股份有限公司 | The method for realizing Image Acquisition using FPGA |
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| CN106791499B (en) * | 2016-11-22 | 2019-06-18 | 北京空间机电研究所 | A method of realizing that improving electron multiplication CCD camera exports signal noise ratio (snr) of image |
| CN106791505A (en) * | 2016-12-29 | 2017-05-31 | 中国科学院西安光学精密机械研究所 | Time sequence generator and time sequence driving method for two-channel CCD imaging system |
| CN106791505B (en) * | 2016-12-29 | 2023-09-05 | 中国科学院西安光学精密机械研究所 | Time sequence generator and time sequence driving method for double-channel CCD imaging system |
| CN110516810A (en) * | 2019-08-29 | 2019-11-29 | 合肥本源量子计算科技有限责任公司 | A kind of processing method, device, storage medium and the electronic device of quantum program |
| CN110516810B (en) * | 2019-08-29 | 2022-08-12 | 合肥本源量子计算科技有限责任公司 | Quantum program processing method and device, storage medium and electronic device |
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