CN103888688A - Time sequence generating device for driving charge coupled device - Google Patents

Abstract

The present invention is a timing generating device for driving a charge-coupled device, comprising a single-chip microcomputer, an active crystal oscillator and a field programmable logic gate array, wherein the active crystal oscillator is connected to the input end of the field programmable logic gate array, for The field programmable logic gate array provides the clock signal; the single-chip microcomputer accesses the parameter register array inside the field programmable logic gate array in turn through the data bus and the address bus, completes the device initialization, and provides all the parameters that need to be set on site for the field programmable logic gate array. Parameters; the input terminal of the field programmable logic gate array is connected with the output terminal of the single-chip microcomputer to realize the data exchange between the internal parameter register array of the field programmable logic gate array and the single-chip computer, and the field programmable logic gate array is generated according to the parameters of the internal parameter register array And output horizontal and vertical driving signals, correlated double sampling and analog-to-digital conversion driving signals and image output timing signals.

Description

A timing generator for driving a charge-coupled device

technical field

The invention belongs to the technical field of low-light imaging, and relates to a general electronic multiplier charge-coupled element drive sequence generation device, which is mainly used in the sequence generation process of charge-coupled device camera design.

Background technique

Electron Multiplying Charge Coupled Device (EMCCD) is a new technology that has emerged in the field of charge-coupled devices (CCD) in the past ten years. The high-voltage electric field formed by the adjacent two gates can amplify the signal electrons by more than 1000 times before the signal electrons are converted into signal voltage by the sense amplifier, thereby suppressing the post-gain noise introduced by the sense amplifier and circuit noise, and obtaining very high Sensitivity, especially suitable for low-light imaging. Compared with the traditional CCD with image intensifier, its structure and volume are greatly simplified, which has great advantages in some weight and volume sensitive applications.

The timing generator of CCD is the brain of the whole CCD camera. It controls the process of generation, collection, transfer, readout and quantification of charge packets, and is an essential core part of the camera. At present, there are mainly two kinds of drive timing generators for CCD: dedicated integrated timing generators for CCD and self-designed generators using programmable logic gate array devices. The former has the advantages of high integration, fast speed, low power consumption, and high phase control accuracy. Advantages, but it can provide fewer driving sources, which often cannot meet the application requirements of some multi-driving CCDs, and the application is not flexible and not universal. It is necessary to re-select the driving sequence every time a different CCD is designed. devices, the design efficiency is low; the method of using programmable logic gate array devices to generate CCD timing signals is very flexible, and can generate more driving source channels according to actual needs, and has good versatility and reusability. Self-designed design has high requirements for the designers themselves and is challenging.

Electron multiplying charge-coupled device is a special frame-transfer charge-coupled device. Compared with ordinary frame-transfer CCD, there are hundreds more electron multiplying registers, so the timing control is more complicated. Taking the charge-coupled device of model CCD201 as an example, it needs 6 channels for horizontal transfer drive, 8 channels for vertical transfer drive, and at least 14 channels of drive signals, and the total number of channels of some multi-output charge-coupled devices even reaches 20. Above the road, the existing dedicated integrated CCD driver cannot meet the application requirements at all. In order to achieve the purpose of generality, the best method is to solve the problem of the timing generator of the charge-coupled device by using the programmable logic gate array to design the timing sequence of the charge-coupled device.

Contents of the invention

(1) Solved technical problems

Aiming at the disadvantages that the existing charge-coupled device-specific integrated timing generator cannot meet the requirements of the charge-coupled device on the number of driving sources, as well as its inflexibility and lack of versatility, a field-programmable logic gate array (FPGA)-based implementation was invented. A timing generator for driving a charge-coupled device.

(2) Technical solutions

The invention provides a timing generating device for driving a charge-coupled device, which mainly includes a single-chip microcomputer, an active crystal oscillator and a field programmable logic gate array, wherein: the active crystal oscillator is connected to the input end of the field programmable logic gate array , to provide clock signals for the FPGA; the single-chip microcomputer accesses the parameter register array inside the FPGA through the data bus and the address bus in sequence, and completes the initialization of the device. According to the actual application requirements, the FPGA provides All parameters that need to be set on site; the input terminal of the field programmable logic gate array is connected with the output terminal of the single-chip microcomputer, and the parameters required by each module in the field programmable logic gate array output by the single-chip microcomputer are received, and are generated according to the parameters of the internal parameter register array And output horizontal drive signal, vertical drive signal, correlated double sampling and analog-to-digital conversion drive signal and image output timing signal.

(3) Beneficial effects

The present invention aims to solve the defects that the existing CCD-specific integrated timing generation module cannot meet the requirements for the number of driving sources of frame-transfer charge-coupled elements, and is inflexible in use and lacks versatility. Compared with CCD-specific integrated timing generation modules, the present invention Modules have the following advantages:

The device uses a single-chip microcomputer to set the parameter register module of the FPGA internal timing generation module, and can flexibly customize the frequency, phase, and duty cycle of each drive source according to the specific charge-coupled device object, and has good versatility;

The device can provide more than 30 driving sources, has good versatility and reusability, and is very suitable for generating driving timing signals as a timing generation module of a frame-transfer charge-coupled element or other large area array CCDs with multiple driving channels. . It can flexibly control the frequency, phase, and duty cycle of each driving source, and the phase adjustment resolution can reach 1.85ns, and the maximum driving frequency can reach 54MHz, which can meet the current application requirements of various special CCDs for timing generation modules, such as It is very suitable as a timing generation module for electron multiplying charge-coupled devices and other large area array CCDs with multiple driving channels to generate driving timing signals.

It is realized by field programmable logic gate array (FPGA), which has very good portability and reusability.

Description of drawings

Fig. 1 is a structural block diagram of a timing generating device for driving a charge-coupled device according to the present invention;

Fig. 2 is the internal state machine of main controller module of the present invention;

Fig. 3 is an output principle and sequence diagram of the 2×2 pixel binning (BIN) mode of the electron multiplying charge-coupled device.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The present invention is directed at the embodiments of charge-coupled devices (CCD), and the charge-coupled devices are planar charge-coupled devices. Those skilled in the art can realize the timing related to driving any planar charge-coupled device through the following embodiments of the present invention. Generating device, the timing generating device of electron multiplying charge-coupled device in the driving CCD camera is described as an example below:

As shown in Fig. 1, the present invention is a timing generator for driving an electron multiplying charge-coupled device (EMCCD), and the device mainly includes a single-chip microcomputer (MCU), an active crystal oscillator and a field programmable logic gate array (FPGA), wherein : The active crystal oscillator is connected with the input end of the field programmable logic gate array to provide a clock signal for the field programmable logic gate array; the single-chip microcomputer sequentially accesses the internal parameter register array of the field programmable logic gate array through the data bus and the address bus, Complete the initialization of the device, and provide all the parameters that need to be set on site for the field programmable logic gate array according to the actual application requirements; The parameters required by each module, and according to the parameters of the internal parameter register array, generate and output the horizontal drive signal, vertical drive signal, correlated double sampling and analog-to-digital conversion drive signal and image used to drive the electron multiplying charge-coupled device in the EMCCD camera output timing signal.

The field programmable logic gate array includes a data communication interface module, a parameter register array module, a digital clock manager module, a main controller module, a horizontal drive generator module, a vertical drive generator module, correlated double sampling and analog-to-digital conversion Drive generator module, image output timing generator module, wherein: the input end of the communication interface module is respectively connected with the output end of the single-chip microcomputer, the data end of the parameter register array, and the output end of the digital clock management module, assisting the single-chip microcomputer to complete the field programmable logic The access to any register inside the gate array realizes the individual configuration of each drive signal source output by the field programmable logic gate array; the input terminal of the digital clock manager module is connected to the output terminal of the active crystal oscillator, and the active The clock signal input by the crystal oscillator is frequency-multiplied and phase-locked to generate a high-frequency clock signal as the main controller module, communication interface module, horizontal drive generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generation The main control clock signal of the controller module and the image output timing generator module controls the timing synchronization between each module; the output terminal of the digital clock manager module is connected with the communication interface module, the main controller module, the horizontal drive generator module, and the vertical drive The generator module, correlated double sampling and analog-to-digital conversion drive generator module, and the input terminal of the image output timing generator module are connected, and the communication interface module receives the high-frequency main control clock signal output by the digital clock manager module, and sends it to the microcontroller. The data is decoded synchronously and written into the corresponding registers in the parameter register array; main controller module, horizontal drive signal generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator module, image output timing The generation module receives the high-frequency main control clock signal output by the digital clock manager module, and drives each of the modules to generate corresponding actions; the input end of the main controller module is connected with the output end of the communication interface module and the output end of the parameter register array module , receive the control signal output by the communication interface module and the parameter data output by the parameter register array, control the operation of the internal state machine of the main controller module, and the output of the main controller module is used to control the horizontal drive generator module, vertical drive generator module, related Double sampling and analog-to-digital conversion drive the control signals of the generator module and the image output timing generator module; the input terminal of the horizontal drive generator module is connected with the output terminal of the main controller module for receiving the horizontal control signal, and according to the control signal The content generates and outputs the horizontal driving signal; the input terminal of the vertical driving generator module is connected with the output terminal of the main controller module, which is used to receive the vertical control signal, and generates and outputs the vertical driving signal according to the content of the control signal; the correlation double sampling and analog The input end of the digital conversion drive generator module is connected with the output end of the main controller module, and is used to receive the relevant double sampling and analog-to-digital conversion control signals, and generate and output the relevant double sampling and analog-to-digital conversion drive signals according to the content of the control signals; The input end of the image output timing generator module is connected with the output end of the main controller module to receive the image timing control signal, and According to the content of the control signal, the image timing driving signal is generated and output.

The parameter register array module includes a frequency parameter register, a phase parameter register, and a duty cycle parameter register. In the field programmable logic gate array, a frequency parameter register, a phase parameter register, and a duty cycle parameter register are respectively provided for each output driving signal source. Ratio parameter registers, and the overall parameter registers of the driven electron multiplier charge-coupled device include: total row number parameter register, effective row number parameter register, total column number parameter register, effective column number parameter register, exposure time parameter register, synchronous mode Parameter register, output mode parameter register, pixel merge parameter register.

Using a single-chip microcomputer to initially set the corresponding parameter registers for each output drive signal source that drives the gate of the electron multiplying charge-coupled device, so as to realize complete control over the characteristics of the drive signal source.

The main controller module performs rapid erasing, exposure, charge packet vertical transfer preparation, charge packet vertical transfer, horizontal invalid charge emptying, charge packet horizontal transfer, charge packet signal amplification, charge packet Readout process design state machine, control horizontal drive generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator module and image output timing generator module to generate in different working states of electron multiplying charge-coupled device corresponding drive signal.

The horizontal drive generator module generates a group of strict time sequences required for the horizontal transfer of charge packets under the control of the main controller module. When the transfer does not occur, the horizontal drive generator module is turned off to reduce the power consumption of the subsequent drive module. To improve the reliability of the entire EMCCD camera electronic system;

The vertical drive generator module generates a set of strict time sequences required for the vertical transfer of charge packets under the control of the main controller module. When the transfer does not occur, the vertical drive generator module is turned off to reduce the power consumption of the subsequent drive module. To improve the reliability of the entire EMCCD camera electronic system;

Under the control of the main controller module, the correlated double sampling and analog-to-digital conversion drive generator module performs correlated double sampling processing on the analog signal of the front-end preprocessing read amplifier circuit of the electron multiplication charge-coupled device, eliminates reset noise, and controls The correlative double sampling and analog-to-digital conversion drive generation module converts the image represented by the analog signal into a digital image.

The image output timing generator module cooperates with the digital image generated after analog-to-digital conversion to provide timing signals, so that the CameraLink interface circuit can transmit the digital image to the outside of the device.

After the EMCCD camera is powered on, first reset all modules inside the FPGA through a global reset signal inside the FPGA and enter an initial state, and then the single-chip microcomputer accesses the parameter register array inside the FPGA through the data bus and the address bus in sequence. The specific characteristics of the CCD object set parameters for all relevant registers to complete the initialization of the timing generator.

The external active crystal oscillator provides a 27MHz clock for the FPGA. After entering the FPGA, the DCM module performs a 10-fold phase-locked amplification on the clock signal to obtain a stable 270MHz system main frequency clock CLK and its reverse clock CLKN;

The communication interface module between the single-chip microcomputer and FPGA mainly provides a data path for the communication between the single-chip microcomputer and the FPGA, and completes the data exchange between the single-chip microcomputer and the internal hardware module. The read and write signals are monitored in real time. When the FPGA detects that the address signal of the microcontroller is valid, it immediately latches the address data on the address bus, and then when it detects that the read and write signals of the microcontroller are valid, it latches the data on the data bus. Compare the latched address with the addresses of all parameter registers in the FPGA internal parameter register array module one by one, write the data directly into the parameter register module with the same latch address, and complete the access to the parameter register module;

Figure 2 shows the internal state machine of the main controller module of the present invention, the main controller module is the core part of the whole timing generation module, a state machine is designed according to the working process of the electron multiplication charge-coupled device, and this state machine has 8 The state, as shown in Figure 2, is mainly divided according to the working process of the electron multiplying charge-coupled device. The time elapsed by each state machine is mainly calculated by a common down-counter. In each state, when the down-counter When the value is decremented from the initial value to 0, immediately enter the next state:

1. Idle state: The idle state does not perform any action. When the state machine receives the internal reset signal of the field programmable logic gate array or the transfer of the previous frame image, it immediately enters the idle state, and immediately sets the elapsed time of the next state to quickly erase the state (that is, the initial value of the common decrement counter is set ), wait for the public counter to be decremented to 0, once it is 0, send the internal synchronous shooting instruction of the EMCCD camera, or receive the external synchronous shooting instruction under the external synchronous state, once the instruction is received, enter the next state immediately;

2. Fast erasing state: Fast erasing is to transfer the noise charges in the CCD imaging area and storage area to the discharge channel before the exposure of the electron multiplier charge-coupled device, and clear the invalid charges in all potential wells to prevent these charges from effectively Photogenerated charges have an effect, reducing noise electrons. Once the main controller module receives the shooting command in the idle state, it immediately enters the fast erasing state, firstly sets the elapsed time of the next state exposure state, and then outputs an 8-bit state code to the horizontal drive generator module and vertical drive generator module Module, correlated double sampling and analog-to-digital conversion drive generator module and image output timing generator module, each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

3. Exposure state: In the exposure state, the electron multiplying charge-coupled device collects the effective signal electrons generated by the photoelectric effect, and isolates the charge packets in the potential well of adjacent pixels with a potential barrier; the main controller module is in the fast erasing state. Enter the exposure state immediately after the public counter decrements to 0, first set the elapsed time of the next state transfer preparation state, and then output the 8-bit state code to the horizontal drive generator module, vertical drive generator module, related double sampling and analog-to-digital conversion The drive generator module and the image output timing generator module, each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state.

4. Transfer preparation state: when the exposure is over, you need to wait for a period of time to allow enough time for the photogenerated electrons to flow into the nearest potential well to avoid image blur and transfer caused by the effective charge not completely falling into the potential well Efficiency drops; the main controller module enters the transfer preparation state immediately after the public counter in the exposure state is decremented to 0, first sets the elapsed time of the next state vertical transfer state, and then outputs an 8-bit state code to the horizontal drive generator module, vertical Drive generator module, correlated double sampling and analog-to-digital conversion drive generator module and image output timing generator module, each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

5. Vertical transfer state: In this state, the signal electronic image generated by the photosensitive area needs to be quickly transferred to the storage area. The storage area of the electron multiplying charge-coupled device is the same size as the photosensitive area and has a light-shielding film to prevent stray photons from affecting the effective electrons. Image interference; the main controller module enters the vertical transfer state immediately after the public counter in the transfer preparation state is decremented to 0, first sets the elapsed time of the next state horizontal clear state, and then outputs an 8-bit state code to the horizontal drive generator module , vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator module, and image output timing generator module. Each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

6. Horizontal clearing state: The horizontal clearing state transfers the noise electrons that fall into the horizontal transfer register module during vertical transfer, and avoids being mixed into the effective charge packet when transferring the first row of signal charges, resulting in increased noise in the first row Phenomenon: the main controller module immediately enters the horizontal clearing state after the common counter in the vertical transfer state is decremented to 0, and first sets the elapsed time of the next state line transfer state, and then outputs an 8-bit status code to the horizontal drive generator module, vertical Drive generator module, correlated double sampling and analog-to-digital conversion drive generator module and image output timing generator module, each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

7. Row transfer state: the row transfer state transfers a row of charge packets adjacent to the horizontal transfer register module to the horizontal transfer register module for horizontal serial transfer of signal charge packets; the common counter of the main controller module in the horizontal clear state is decremented After it is 0, enter the line transfer state immediately, first set the elapsed time of the next state horizontal transfer state, and then output the 8-bit state code to the horizontal drive generator module, vertical drive generator module, related double sampling and analog-to-digital conversion drive generation The generator module and the image output timing generator module, each module generates a corresponding driving signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

8. Horizontal transfer state: After the row transfer is completed, there is already a row of effective signal charges in the horizontal transfer register module. At this time, these charges need to be transferred one by one to the electron multiplication register module to complete the signal charge amplification, and then transferred to the readout amplifier. In the module, the conversion of signal charge to signal voltage is completed. The main controller module enters the horizontal transfer state immediately after the common counter of the row transfer state is decremented to 0, firstly judges whether the current row is the last row of the CCD, if the next state is set to the idle state, otherwise the next state is set to the row transfer state , then set the elapsed time of the next state, and then output the 8-bit status code to the horizontal drive generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator module and image output timing generator module, Each module generates a corresponding drive signal according to the current state machine state; when the common counter is decremented to 0, it enters the next state;

The above 8 states are carried out sequentially. Once entering the fast erasing state, it will go through all 8 states in sequence until all the charge packets are transferred out of the CCD. The time elapsed in each state is based on the value of each parameter register module. It is estimated that it is written into the public counter, and once the time in the current state is over, it immediately enters the next state and completes the next step.

The horizontal drive generator module judges the current state of the electron multiplying charge-coupled device according to the 8-bit state code output by the state machine of the main controller module, and then generates a set of horizontal transfer drive signals with pixels as the transfer unit: in the above 5, In the 6 and 8 states, a square wave pulse signal is generated according to the configuration of the parameter register module of each driving signal source to control the horizontal transfer of the signal charge packet; in other states, according to the actual situation, either set high or pull low, No square wave pulse signal is generated to reduce system power consumption;

The vertical drive generator module judges the current state of the electron multiplier charge-coupled device according to the 8-bit state code output by the state machine of the main controller module, and generates a set of vertical transfer drive signals in line transfer units: in the above 5 and 7 states In this state, the square wave pulse signal is generated according to the configuration of the parameter register module of each driving signal source to control the vertical transfer of the signal charge packet; in other states, the square wave pulse is not generated according to the actual situation or set high or low signal to reduce system power consumption;

The relevant double sampling and analog-to-digital conversion drive generator module judges the current state of the electron multiplication charge-coupled device according to the 8-bit status code output by the state machine of the main controller module, and generates a set of drive signals in units of pixels: for the follow-up The CCD preprocessing circuit provides corresponding correlated double-sampling pulse signals and analog-to-digital conversion start signals to convert analog voltage signals into digital signals;

The image output timing generator module judges the current state of the electron multiplying charge-coupled device according to the 8-bit state code output by the state machine of the main controller module, and outputs the frame valid signal FVAL, the line valid signal LVAL, and the pixel valid signal PVALID, as The corresponding data format is added to the digital image after analog-to-digital conversion, so that the subsequent CameraLink interface circuit can transmit the digital image to the outside of the EMCCD camera.

In order to realize the 2×2 binning (BIN) mode output of the EMCCD camera, the principle and sequence diagram of the binning mode output of the electron multiplier charge-coupled device as shown in Figure 3 are adopted. When the pixel binning output mode is activated, the value 2 in the pixel binning register module is first read out. Figure 3(a) is a schematic diagram of vertical pixel binning, where a and b are the penultimate row phases in the electron multiplier charge-coupled device The charge packets in two adjacent columns, c and d are the charge packets in the penultimate row and two adjacent columns in the electron multiplication charge-coupled device, SG is the horizontal summation gate, and the arrow indicates the transfer direction of the charge packet; Fig. 3(b) It is a schematic diagram of horizontal pixel merging, and the arrow indicates the direction of charge packet transfer; Figure 3(c) is the timing process of 2×2 pixel merging, S1 and S2 are row clock transfer gates, R1, R2 and R3 are horizontal clock transfer gates , SG is the horizontal summation gate, and RST is the reset gate, which is divided into three timing stages: exposure, vertical pixel merging, and horizontal pixel merging. In the state of combining pixels in the vertical direction, corresponding to the phase of combining pixels in the vertical direction in Fig. The pixels a, b, c, and d of the last two rows on the doubled charge-coupled device are merged into the corresponding horizontal transfer register to form two merged pixels a+c, b+d, and the pixel merge operation in the vertical direction is completed; then Perform horizontal transfer, corresponding to the horizontal pixel merging stage in Figure 3(b) and Figure 3(c), firstly send continuous drive pulse signals to the R1, R2, R3 horizontal drive gates, and the drive pixels enter the summation gate in turn The summing gate SG sends a high pulse every 2 pixel clocks for a summation operation, and the reset gate RST sends a high pulse every 2 pixel clocks to reset the CCD readout amplifier, thereby completing the image in the horizontal direction Meta merge operation.

The above is only a specific implementation mode in the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technology can understand the conceivable transformation or replacement within the technical scope disclosed in the present invention. All should be covered within the scope of the present invention, therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (9)

1. A timing generator for driving a charge-coupled device, characterized in that: it mainly includes a single-chip microcomputer, an active crystal oscillator and a field programmable logic gate array, wherein: The active crystal oscillator is connected to the input end of the field programmable logic gate array to provide a clock signal for the field programmable logic gate array; The single-chip microcomputer sequentially accesses the parameter register array inside the field programmable logic gate array through the data bus and the address bus, completes device initialization, and provides all parameters that need to be set on site for the field programmable logic gate array according to actual application requirements; The input end of the field programmable logic gate array is connected with the output end of the single-chip microcomputer, receives the parameters required by each module in the field programmable logic gate array output by the single-chip microcomputer, and generates and outputs horizontal drive signals and vertical drive signals according to the parameters of the internal parameter register array. signal, correlated double sampling and analog-to-digital conversion drive signal and image output timing signal. 2. The timing generating device for driving charge-coupled devices according to claim 1, characterized in that: the Field Programmable Logic Gate Array includes a data communication interface module, a parameter register array module, a digital clock manager module, and a main controller Module, horizontal drive generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator module, image output timing generator module, in which: The input terminal of the communication interface module is respectively connected with the output terminal of the single-chip microcomputer, the data terminal of the parameter register array, and the output terminal of the digital clock management module, assisting the single-chip computer to complete the access to any register inside the field programmable logic gate array, and realizing the field programmable Individual configuration of each driving signal source output by the logic gate array; The input terminal of the digital clock manager module is connected to the output terminal of the active crystal oscillator, and the clock signal input by the active crystal oscillator is frequency-multiplied and phase-locked to generate a high-frequency clock signal as the main controller module and communication interface module , the main control clock signal of the horizontal drive generator module, the vertical drive generator module, the correlated double sampling and analog-to-digital conversion drive generator module and the image output timing generator module, to control the timing synchronization between each module; The output of the digital clock manager module and the input of the communication interface module, the main controller module, the horizontal drive generator module, the vertical drive generator module, the correlated double sampling and analog-to-digital conversion drive generator module, and the image output timing generator module The communication interface module receives the high-frequency main control clock signal output by the digital clock manager module, decodes the data sent by the single-chip microcomputer synchronously, and writes it into the corresponding register in the parameter register array; the main controller module, horizontal drive The signal generator module, the vertical drive generator module, the correlated double sampling and analog-to-digital conversion drive generator module, and the image output timing generation module receive the high-frequency main control clock signal output by the digital clock manager module, and drive each of the modules to generate corresponding action; The input terminal of the main controller module is connected with the output terminal of the communication interface module and the output terminal of the parameter register array module, receives the control signal output by the communication interface module and the parameter data output by the parameter register array, and controls the operation of the internal state machine of the main controller module , the main controller module outputs control signals for controlling the horizontal drive generator module, the vertical drive generator module, the correlated double sampling and analog-to-digital conversion drive generator module and the image output timing generator module; The input terminal of the horizontal driving generator module is connected with the output terminal of the main controller module, and is used for receiving the horizontal control signal, and generating and outputting the horizontal driving signal according to the content of the control signal; The input terminal of the vertical drive generator module is connected to the output terminal of the main controller module, and is used to receive the vertical control signal, and generate and output the vertical drive signal according to the content of the control signal; The input terminal of the correlated double sampling and analog-to-digital conversion drive generator module is connected to the output terminal of the main controller module for receiving correlated double sampling and analog-to-digital conversion control signals, and generating and outputting correlated double sampling and analog-to-digital conversion signals according to the content of the control signal Digital conversion drive signal; The input end of the image output timing generator module is connected with the output end of the main controller module, and is used for receiving the image timing control signal, and generating and outputting the image timing driving signal according to the content of the control signal. 3. The timing generating device for driving charge-coupled devices according to claim 2, characterized in that: the parameter register array module includes a frequency parameter register, a phase parameter register, and a duty cycle parameter register, and is inside the Field Programmable Logic Gate Array There are frequency parameter registers, phase parameter registers, and duty cycle parameter registers for each output driving signal source, and the overall parameter registers of the driven charge-coupled device include: total row number parameter register, effective row number parameter register, The total column number parameter register, the effective column number parameter register, the exposure time parameter register, the synchronous mode parameter register, the output mode parameter register, and the pixel merging parameter register. 4. The timing generating device for driving a charge-coupled device according to claim 3, characterized in that: use a single-chip microcomputer to carry out corresponding parameter register initial settings for each output drive signal source driving the gate of a charge-coupled device, so as to realize Complete control over the characteristics of the drive source. 5. The timing generating device for driving a charge-coupled device according to claim 2, characterized in that: the main controller module performs fast erasing, exposure, charge packet vertical transfer preparation, charge packet vertical Process design state machine for transfer, horizontal invalid charge emptying, charge packet horizontal transfer, charge packet signal amplification, charge packet readout, control horizontal drive generator module, vertical drive generator module, correlated double sampling and analog-to-digital conversion drive generator The module and the image output timing generator module generate corresponding driving signals under different working states of the charge-coupled device. 6. The timing generating device for driving charge-coupled devices according to claim 2, characterized in that: the horizontal drive generator module generates the required timing for a group of charge packets horizontally transferred under the control of the main controller module, and no transfer occurs turn off the horizontal drive generator module. 7. The timing generating device for driving charge-coupled devices according to claim 2, characterized in that: the vertical drive generator module produces the required timing for vertical transfer of a group of charge packets under the control of the main controller module, and no transfer occurs Turn off the vertical drive generator module at this time. 8. The timing generating device for driving charge-coupled devices according to claim 2, characterized in that: correlated double sampling and analog-to-digital conversion drive generator module completes the front-end preprocessing of charge-coupled devices under the control of the main controller module The analog signal of the readout amplification circuit is processed by correlated double sampling to eliminate reset noise, and the correlated double sampling and analog-to-digital conversion drive generation module is controlled to convert the image represented by the analog signal into a digital image. 9. The timing generating device for driving a charge-coupled device according to claim 2, characterized in that: the image output timing generator module cooperates with the digital image generated after the analog-to-digital conversion to provide timing signals, so that the CameraLink interface circuit transmits the digital image to the outside of the device.

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