CN103888688B - Time sequence generating device for driving charge-coupled device - Google Patents
Time sequence generating device for driving charge-coupled device Download PDFInfo
- Publication number
- CN103888688B CN103888688B CN201410106542.7A CN201410106542A CN103888688B CN 103888688 B CN103888688 B CN 103888688B CN 201410106542 A CN201410106542 A CN 201410106542A CN 103888688 B CN103888688 B CN 103888688B
- Authority
- CN
- China
- Prior art keywords
- module
- generator module
- charge
- signal
- drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a time sequence generating device for driving a charge-coupled device. The time sequence generating device comprises a single chip microcomputer, an active crystal oscillator and a field-programmable logic gate array, wherein the active crystal oscillator is connected with the input end of the field-programmable logic gate array and provides a clock signal for the field-programmable logic gate array, the single chip microcomputer sequentially has access to parameter register arrays inside the field-programmable logic gate array through a data bus and an address bus to complete device initialization and provides all parameters needing field setting for the field-programmable logic gate array, the input end of the field-programmable logic gate array is connected with the output end of the single chip microcomputer to achieve data exchange between the parameter register arrays inside the field-programmable logic gate array and the single chip microcomputer, the field-programmable logic gate array generates and outputs a horizontal driving signal, a perpendicular driving signal, a correlated double-sampling and analog-digital conversion driving signal and an image output time sequence signal according to parameters of the parameter register arrays inside the field-programmable logic gate array.
Description
Technical field
The invention belongs to low-light level imaging technical field, is related to a kind of general electron multiplying charge coupling element driver' s timing
Generating meanss, the sequential generating process being mainly used in when charge-coupled device camera is designed.
Background technology
Electron multiplying charge coupled apparatus (Electron Multiplying Charge Couple Device, EMCCD)
It is the new technique for occurring in charge-coupled image sensor (CCD) field nearly ten years, it is individually integrated with hundreds of levels on silicon chip
Electron multiplication depositor, the high voltage electric field formed using two neighboring grid can be converted in signal electron by sense amplifier
Signal electron is amplified into more than 1000 times before signal voltage, so as to suppress because sense amplifier and circuit noise are introduced
Noise after gain, obtains very high sensitivity, is particularly suitable for low-light level imaging.Compared to the CCD of conventional belt image intensifier, its
Structure and volume are greatly simplified, and have greater advantage in the sensitive application scenario of some weight and volumes.
The timing sequencer of CCD is the brain of whole CCD camera, and it controls generation, collection, transfer, the reading of charge packet
Go out, quantizing process, be the requisite core of camera.At present, mainly have two for the driver' s timing generating meanss of CCD
Kind：Special integrated timing sequencers of CCD and using programmable gate array device designed, designed generator, the former has integrated
The advantages of degree height, fast, low in energy consumption speed, phase controlling high precision, but its driving source way that can be provided is less, tends not to
Meet the application requirement of some many driving ways CCD, and using dumb, not with versatility, need during per secondary design difference CCD
Driving schedule generator is reselected, design efficiency is low；CCD clock signals are produced using programmable gate array device
Method is very flexible, can according to actual needs produce more driving source way, with preferable versatility and repeatable utilization
Property, but due to needing designed, designed, it is higher to designer's oneself requirement, with certain challenge.
Electron multiplying charge coupled apparatus is a kind of special frame transfer type charge coupled cell, relatively common frame transfer type
Many hundreds of grade of the electron multiplication depositors of CCD, therefore sequencing contro is also increasingly complex.With the Charged Couple of model CCD201
As a example by device, its horizontal transfer drives needs 6 tunnels, and vertical transitions drive needs 8 tunnels, needs at least 14 road drive signals, and certain
A bit the total way of multiple-channel output type charge-coupled image sensor has been even up to more than 20 tunnels, and existing Special integrated CCD drivers are basic
Application requirement cannot be met.To reach versatility purpose, the best way is to design electric charge coupling using programmable gate array
The mode of clutch part driver' s timing is solving the problems, such as the timing sequencer of charge-coupled image sensor.
The content of the invention
(1) technical problem for solving
For existing charge-coupled image sensor Special integrated timing sequencer charge-coupled image sensor cannot be met to driving source
The requirement of quantity, and using dumb, lack the shortcoming of versatility, invent a kind of based on field programmable gate array
(FPGA) the sequential generating meanss for driving charge coupled cell realized.
(2) technical scheme
The present invention provides a kind of sequential generating meanss for driving charge-coupled image sensor, mainly including single-chip microcomputer, active
Crystal oscillator and field programmable gate array, wherein：Active crystal agitator is defeated with field programmable gate array
Enter end connection, for field programmable gate array clock signal is provided；Single-chip microcomputer is by data/address bus and address bus to existing
Parameter register array inside field programmable logic gate array is accessed successively, finishing device initialization, will according to practical application
Seek the parameter that scene setting in need is provided for field programmable gate array；The input of field programmable gate array
End is connected with single-chip microcomputer output, required for receiving the field programmable gate array inside modules of single-chip microcomputer output
Parameter, and generated according to the parameter of inner parameter register array and output level drive signal, vertical driving signal, correlation pair
Sampling and analog digital conversion drive signal and image output timing signal.
(3) beneficial effect
Present invention seek to address that existing CCD Special integrateds sequential occurs module cannot meet frame transfer type Charged Couple unit
Requirement of the part to driving source quantity, and using dumb, lack the defect of versatility, the present invention is relative to CCD Special integrateds
Sequential occurs for module, has the advantage that：
The device arranges the parameter register module that FPGA inside sequential occurs module by single-chip microcomputer, can be according to specific
Charge-coupled image sensor object implementatio8 drives source frequency, phase place, the flexible customization of dutycycle to every road, with preferable versatility；
The device can provide 30 tunnel above driving sources, with preferable versatility and repeatable usability, be especially suitable for making
There is module generation driver' s timing letter in the sequential for frame transfer type charge coupled cell or large area array CCD of other many driving ways
Number.The frequency of every road driving source, phase place, dutycycle can flexibly be controlled, and phase adjusted resolution can reach 1.85ns, it is maximum
Driving frequency can reach 54MHz, can meet the application requirement that current all kinds of special CCD occur module to sequential, such as fit very much
Cooperate as during the sequential generation module generation driving of electron multiplying charge coupled apparatus and other large area arrays CCD for driving way more
Sequential signal.
Realized using field programmable gate array (FPGA), with extraordinary portable and repeatable utilization
Property.
Description of the drawings
Fig. 1 is the present invention for driving the sequential generating meanss structure composition block diagram of charge-coupled image sensor；
Fig. 2 is the state machine inside main controller module of the present invention；
Fig. 3 is that the pixel of electron multiplying charge coupled apparatus 2 × 2 merges (BIN) pattern output principle and sequential chart.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
The present invention be directed to the embodiment of charge-coupled image sensor (CCD), the charge-coupled image sensor is surface array charge-coupled
Device, those skilled in the art can realize being related to drive arbitrary surface array charge-coupled device by the following examples of the present invention
Sequential generating meanss, below only by drive CCD camera in electron multiplying charge coupled apparatus sequential generating meanss as a example by be situated between
Continue embodiment：
As Fig. 1 illustrates that the present invention is the sequential generating meanss for driving electron multiplying charge coupled apparatus (EMCCD), should
Device mainly includes single-chip microcomputer (MCU), active crystal agitator and field programmable gate array (FPGA), wherein：It is active
Crystal oscillator is connected with field programmable gate array input, and for field programmable gate array clock letter is provided
Number；Single-chip microcomputer by data/address bus and address bus to the parameter register array inside field programmable gate array successively
Access, finishing device initialization provides scene in need and sets for field programmable gate array based on the actual application requirements
Fixed parameter；The input of field programmable gate array is connected with single-chip microcomputer output, receives the scene of single-chip microcomputer output
Parameter required for the modules of programmable gate array inside, and generated simultaneously according to the parameter of inner parameter register array
Export horizontal drive signals, vertical driving signal, the correlation to drive the magazine electron multiplying charge coupled apparatuses of EMCCD
Double sampled and analog digital conversion drive signal and image output timing signal.
Field programmable gate array inside comprising data communication interface module, parameter register array module,
Digital dock manager module, main controller module, horizontal drive generator module, vertical drive generator module, correlation are double
Sampling and analog digital conversion drive generator module, image output timing generator module, wherein：The input of communication interface modules
It is connected with the outfan of single-chip microcomputer output, the data terminal of parameter register array, digital dock management module respectively, assists single
Piece machine completes the access to the arbitrary depositor in field programmable gate array inside, realizes to field programmable gate array
Being separately configured per source driving signal all the way of output；The input of digital dock manager module and active crystal agitator
Outfan connects, and to the clock signal of active crystal agitator input frequency multiplication, lock phase are carried out, and generates high frequency clock signal as master
Controller module, communication interface modules, horizontal drive generator module, vertical drive generator module, correlated-double-sampling and mould
Number conversion drives the master clock signal of generator module and image output timing generator module, between control modules
Timing synchronization；The outfan of digital dock manager module and communication interface modules, main controller module, horizontal drive generator
Module, vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator module, image output timing generator
The input connection of module, communication interface modules receives the high frequency master clock signal of digital dock manager module output, right
The data that single-chip microcomputer is sended over synchronize the corresponding registers in decoding, and write parameters register array；Master controller
Module, horizontal drive signals generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator
There is the high frequency master clock signal that module receives the output of digital dock manager module in module, image output timing, drive every
One module produces corresponding action；The input of main controller module and communication interface modules outfan, parameter register
The outfan connection of device array module, receives the control signal of communication interface modules output and the ginseng of parameter register array output
Number data, control the operating of main controller module internal state machine, and main controller module is exported to be occurred for controlling horizontal drive
Device module, vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator module and image output timing to send out
The control signal of raw device module；The input of horizontal drive generator module is connected with the outfan of main controller module, is used for
Level control signal is received, and is generated according to control signal content and output level drive signal；Vertical drive generator module
Input be connected with the outfan of main controller module, for receiving vertical control signal, and given birth to according to control signal content
Into and export vertical driving signal；Correlated-double-sampling and analog digital conversion drive the input and main controller module of generator module
Outfan connection, for receiving correlated-double-sampling and analog digital conversion control signal, and generated according to control signal content and defeated
Go out correlated-double-sampling and analog digital conversion drive signal；The input of image output timing generator module and main controller module
Outfan connects, and for receiving image timing control signal, and is generated according to control signal content and output image Timing driver
Signal.
The parameter register array module includes that frequency parameter depositor, phase parameter depositor, duty cycle parameters are posted
Storage, at the scene to being respectively equipped with frequency parameter deposit per the source driving signal for exporting all the way inside programmable gate array
Device, phase parameter depositor, duty cycle parameters depositor, and be provided with by the population parameter of driving electron multiplying charge coupled apparatus
Depositor includes：Total line number parameter register, effective line number parameter register, total columns parameter register, effective columns parameter
Depositor, exposure time parameter depositor, synchronous mode parameter register, output mode parameter register, pixel merges parameter
Depositor.
The source driving signal per driving electron multiplying charge coupled apparatus grid all the way of output is carried out using single-chip microcomputer
Corresponding parameter register initial setting up, realizes the complete control to the source driving signal characteristic.
The main controller module is to quick erasing, exposure, the electric charge in electron multiplying charge coupled apparatus imaging process
The preparation of bag vertical transitions, charge packet vertical transitions, the invalid electric charge of level are emptied, charge packet horizontal transfer, charge packet signal amplify,
The Process Design state machine that charge packet reads, control horizontal drive generator module, vertical drive generator module, correlation are double to adopt
Sample and analog digital conversion drive generator module and image output timing generator module different in electron multiplying charge coupled apparatus
Corresponding drive signal is produced under working condition.
Described horizontal drive generator module produces one group of charge packet horizontal transfer institute under main controller module control
The strict sequential of the relation of needs, closes horizontal drive generator module when not shifting, reduce rear class drive module power consumption,
For improving the reliability of whole EMCCD cameras electronic system；
Described vertical drive generator module produces one group of charge packet vertical transitions institute under main controller module control
The strict sequential of the relation of needs, closes vertical drive generator module when not shifting, reduce rear class drive module power consumption,
For improving the reliability of whole EMCCD cameras electronic system；
The correlated-double-sampling and analog digital conversion drive generator module complete paired electronss under main controller module control
The front end pretreatment of multiplying charge coupled apparatus reads the analogue signal of amplifying circuit and carries out correlated-double-sampling process, eliminates and resets
Noise, and control correlated-double-sampling and analog digital conversion and drive module to occur the image represented with analogue signal is converted to into digitized map
Picture.
Described image output timing generator module coordinates the digital picture generated after analog digital conversion to provide clock signal, with
Just CameraLink interface circuits are by outside Digital Image Transmission to the device.
On EMCCD cameras after electricity, first by a global reset signal inside FPGA to all modules in FPGA inside
Resetted, into an original state, afterwards single-chip microcomputer is posted the parameter inside FPGA by data/address bus and address bus
Storage array is accessed successively, and parameter setting is carried out to all related registers for the concrete property of the CCD objects of practical application,
Complete the initialization of the sequential generating meanss.
External active crystal oscillator provides the clock of 27MHz all the way for FPGA, into after FPGA by DCM modules to this when
Clock signal carries out 10 times of locks and mutually amplifies, and obtains 270MHz systems dominant frequency clock CLK and its reverse clock CLKN stable all the way；
The communication interface modules of single-chip microcomputer and FPGA mainly provides a data for the communication between single-chip microcomputer and FPGA
Path, completes the data exchange between single-chip microcomputer and internal hardware module, and implementation is：To monolithic in interface communication module
The address signal of machine, reading and writing data signal carry out real-time monitoring, when FPGA detect single-chip microcomputer address signal it is effective when, lock immediately
The address date on address bus is deposited, afterwards when monitoring that single-chip microcomputer read-write is effective again, then by the number on data/address bus
According to being latched, and by the address of all parameter registers in the address being latched and FPGA inner parameter register array modules
It is compared one by one, data is write direct and latch address identical parameter register module, completes to parameter register mould
The access of block；
State machine inside main controller module of the present invention as shown in Figure 2, main controller module is that whole sequential occurs mould
The core of block, according to the course of work of electron multiplying charge coupled apparatus a state machine is devised, and the state machine has 8
Individual state, as shown in Fig. 2 it is main according to the course of work of electron multiplying charge coupled apparatus dividing, each state machine institute
After time mainly calculated by a public down counter, in each state when the value of the down counter
When being decremented to 0 from initial value, next state is immediately entered：
1. idle condition：Idle condition does not do any action.When state machine receives field programmable gate array
Internal reset signal or the transfer of previous frame image immediately enter idle condition after finishing, and arrange the quick sassafras of next state immediately
Except the elapsed time (arranging public down counter initial value) of state, common counter is waited to be decremented to 0, once it is 0
Just the interior sync pulse jamming instruction of EMCCD cameras is sent, or outer sync pulse jamming instruction is received under outer synchronous regime, upon receipt of
Instruction, immediately enters next state；
2. quick erase status：Quick erasing is to be imaged CCD before electron multiplying charge coupled apparatus is exposed
The noise charge of area and memory block is transferred to rushes down lotus raceway groove, empties the invalid electric charge of all potential wells, it is to avoid these electric charges are to having
Effect photogenerated charge produces impact, reduces noise electronics.Main controller module upon receipt of instruction is shot, stands in an idle state
Enter quick sassafras and remove state, the elapsed time of NextState exposure status is set first, 8 conditional codes are just exported afterwards to water
It is flat to drive generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion to drive generator module and image
Output timing generator module, modules produce corresponding drive signal according to current state machine state；Work as common counter
0 is decremented to, just into next state；
3. exposure status：Electron multiplying charge coupled apparatus collects the useful signal produced by photoelectric effect under exposure status
Electronics, and the charge packet in neighbor potential well is kept apart using potential barrier；Main controller module is in quick sassafras except the public affairs of state
Altogether enumerator immediately enters exposure status after being decremented to 0, the elapsed time that NextState shifts SBR is arranged first, afterwards
Just export 8 conditional codes to drive to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion
Dynamic generator module and image output timing generator module, modules produce corresponding driving according to current state machine state
Signal；When common counter is decremented to 0, just into next state.
4. SBR is shifted：After end exposure, need to wait for a period of time, to reserve time enough photoproduction electricity is made
Subflow enters in the potential well of its nearest neighbours, it is to avoid the image blurring and transfer efficiency that effective charge does not fall completely within potential well and causes
Decline；Main controller module immediately enters transfer SBR after the common counter of exposure status is decremented to 0, arranges first
The elapsed time of NextState vertical transitions state, just exports afterwards 8 conditional codes to horizontal drive generator module, vertical drive
Dynamic generator module, correlated-double-sampling and analog digital conversion drive generator module and image output timing generator module, each
Module produces corresponding drive signal according to current state machine state；When common counter is decremented to 0, just into next shape
State；
5. vertical transitions state：Need for the signal electron image that photosensitive area produces to be quickly transferred to memory block under the state,
The memory block of electron multiplying charge coupled apparatus is consistent with photosensitive area scale and with photomask, can prevent spuious photon to effective
The interference of electronic image；Main controller module immediately enters vertical turning after the common counter of transfer SBR is decremented to 0
Shifting state, arranges first the elapsed time of the horizontal empty of NextState, 8 conditional codes is just exported afterwards and is sent out to horizontal drive
Raw device module, vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator module and image output timing
Generator module, modules produce corresponding drive signal according to current state machine state；When common counter is decremented to 0,
Just next state is entered；
6. horizontal empty：Horizontal empty will fall into making an uproar inside horizontal transfer registration module in vertical transitions
Sound electron transfer is clean, it is to avoid be mixed in effective charge bag when the first row signal charge is shifted, and causes the first row noise to increase
Phenomenon；Main controller module immediately enters horizontal empty after the common counter of vertical transitions state is decremented to 0, first
The elapsed time of next state line transfering state is first set, 8 conditional codes are just exported afterwards to horizontal drive generator module, vertical
It is straight to drive generator module, correlated-double-sampling and analog digital conversion to drive generator module and image output timing generator module,
Modules produce corresponding drive signal according to current state machine state；When common counter is decremented to 0, just into the next one
State；
7. row transfering state：A line charge packet for closing on horizontal transfer registration module is transferred to level and is turned by row transfering state
In moving registration module, so that the horizontal serial for carrying out signal charge bag is shifted；Public affairs of the main controller module in horizontal empty
Altogether enumerator immediately enters row transfering state after being decremented to 0, and the elapsed time of NextState horizontal transfer state is arranged first, it
8 conditional codes are just exported afterwards to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion
Generator module and image output timing generator module, modules is driven to produce corresponding drive according to current state machine state
Dynamic signal；When common counter is decremented to 0, just into next state；
8. horizontal transfer state：After row transfer is completed, the effective signal of existing a line in horizontal transfer registration module
Electric charge, now needs successively to be transferred to these electric charges one by one electron multiplication registration module and completes signal charge amplification, is then transferred to
In reading amplification module, signal charge is completed to the conversion of signal voltage.Main controller module is expert at the public meter of transfering state
Number devices immediately enter horizontal transfer state after being decremented to 0, first determine whether that whether current line is last column of CCD, if next
State is set to idle condition, and otherwise NextState is set to row transfering state, and the elapsed time of NextState is just arranged afterwards,
Just export 8 conditional codes afterwards to turn to horizontal drive generator module, vertical drive generator module, correlated-double-sampling and modulus
Driving generator module and image output timing generator module are changed, modules produce corresponding according to current state machine state
Drive signal；When common counter is decremented to 0, just into next state；
8 states of the above are that order is carried out, once into quick erase status, it will sequentially experience all 8 states
Until all of charge packet is all transferred out of into CCD, each state after time be according to parameters deposit mould
Block value estimates write common counter, once having experienced the time of place state, immediately enters next state, completes
Next step is operated.
8 conditional codes that horizontal drive generator module is exported according to main controller module state machine are judging electron multiplication
The state that charge-coupled image sensor is presently in, and then produce one group of horizontal transfer drive signal with pixel as transfer unit：
Above-mentioned 5, under 6,8 states, square-wave pulse signal is produced according to the parameter register module configuration per source driving signal itself all the way,
With the horizontal transfer of control signal charge packet；Under other states, according to practical situation or height is put, or dragged down, do not produce square wave
Pulse signal, to reduce system power dissipation；
8 conditional codes that vertical drive generator module is exported according to main controller module state machine are judging electron multiplication
The state that charge-coupled image sensor is presently in, produces one group of vertical transitions drive signal with behavior transfer unit：Above-mentioned 5,7
Under state, square-wave pulse signal is produced according to the parameter register module configuration per source driving signal all the way, with control signal electricity
The vertical transitions of pocket；Under other states, according to practical situation or height is put, or dragged down, do not produce square-wave pulse signal, to drop
Low system power dissipation；
Correlated-double-sampling and analog digital conversion drive 8 states that generator module is exported according to main controller module state machine
Code produces one group of drive signal in units of pixel judging the state that electron multiplying charge coupled apparatus is presently in：For
Follow-up CCD pretreatment circuit provides corresponding correlated-double-sampling pulse signal and analog digital conversion enabling signal, by analog voltage
Signal is converted to digital signal；
8 conditional codes that image output timing generator module is exported according to main controller module state machine are judging electronics
The state that multiplying charge coupled apparatus is presently in, and output frame useful signal FVAL, row useful signal LVAL, pixel is effectively believed
Number PVALID, is that the digital picture after analog digital conversion adds corresponding data form, so that follow-up CameraLink connects
Mouth circuit is by beyond Digital Image Transmission to EMCCD cameras.
To realize that 2 × 2 pixels of EMCCD cameras merge the output of (BIN) pattern, electron multiplication electricity as shown in Figure 3 is employed
The method of lotus coupled apparatus pixel merging patterns output principle and sequential chart.When pixel merges output mode to be activated, first
The numerical value 2 that pixel merges in registration module is read, Fig. 3 (a) is that vertical pixel merges schematic diagram, wherein a, and b is electron multiplication electricity
The charge packet that row second from the bottom adjacent two is arranged in lotus coupled apparatus, c, d are row last in electron multiplying charge coupled apparatus
The charge packet of adjacent two row, SG is level summation grid, and arrow represents the shift direction of charge packet；Fig. 3 (b) is horizontal pixel conjunction
And schematic diagram, arrow represents charge packet shift direction；Fig. 3 (c) is the when program process that 2 × 2 pixels merge, and S1, S2 are row clock
Transfer gate, R1, R2 and R3 are horizontal clock transfer gate, and SG is level summation grid, and RST is reset gate, is divided into three
The sequential stage：Exposure, vertical direction pixel merge, horizontal direction pixel merges.Under vertical direction pixel merging phase, correspondence
In Fig. 3 (a) and the vertical direction pixel merging phase of Fig. 3 (c), two vertical transitions pulses are continuously transmitted first and is turned to row clock
Grid S1 and S2 are moved, by pixel a of two row reciprocal on electron multiplying charge coupled apparatus, b, c, d are merged into corresponding level and turn
Move and a+c is formed in depositor, two merging pixels of b+d complete the pixel union operation of vertical direction；Carry out level again afterwards to turn
Move, corresponding to Fig. 3 (b) and the horizontal direction pixel merging phase of Fig. 3 (c), first to R1, R2, R3 horizontal drive grid sends
Continuous Drive pulse signal, drives pixel to sequentially enter summation grid, and the grid SG that sues for peace sends one at interval of 2 pixel clocks
Secondary high impulse carries out a sum operation, and reset gate RST sends a high impulse reset CCD and reads every 2 pixel clocks
Amplifier, so as to complete the pixel union operation of horizontal direction.
The above, the only specific embodiment in the present invention, but protection scope of the present invention is not limited thereto, and appoints
What be familiar with the people of the technology disclosed herein technical scope in, it will be appreciated that the conversion expected or replacement, all should cover
The present invention include within the scope of, therefore, protection scope of the present invention should be defined by the protection domain of claims.
Claims (8)
1. a kind of sequential generating meanss for driving charge-coupled image sensor, it is characterised in that：Mainly include single-chip microcomputer, active crystalline substance
Oscillation body device and field programmable gate array, wherein：
Active crystal agitator is connected with field programmable gate array input, provides for field programmable gate array
Clock signal；
Single-chip microcomputer by data/address bus and address bus to the parameter register array inside field programmable gate array according to
Secondary access, finishing device initialization, provides scene in need for field programmable gate array based on the actual application requirements
The parameter of setting；
The input of field programmable gate array is connected with single-chip microcomputer output, receives the field-programmable of single-chip microcomputer output
Parameter required for the modules of logic gate array inside, and water is generated and exported according to the parameter of inner parameter register array
Flat drive signal, vertical driving signal, correlated-double-sampling and analog digital conversion drive signal and image output timing signal；
The field programmable gate array inside includes data communication interface module, parameter register array module, numeral
Timer manager module, main controller module, horizontal drive generator module, vertical drive generator module, correlated-double-sampling
And analog digital conversion drives generator module, image output timing generator module, wherein：
The input of communication interface modules respectively with single-chip microcomputer output, the data terminal of parameter register array, digital dock pipe
The outfan connection of reason module, assists single-chip microcomputer to complete the access to the arbitrary depositor in field programmable gate array inside,
Realize being separately configured per source driving signal all the way to field programmable gate array output；
The input of digital dock manager module is connected with the outfan of active crystal agitator, defeated to active crystal agitator
The clock signal for entering carries out frequency multiplication, lock phase, generates high frequency clock signal as main controller module, communication interface modules, level
Generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion is driven to drive generator module and image defeated
Go out the master clock signal of timing sequencer module, control the timing synchronization between modules；
The outfan of digital dock manager module and communication interface modules, main controller module, horizontal drive generator module,
Vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator module, image output timing generator module
Input connection, communication interface modules receives the high frequency master clock signal of digital dock manager module output, to monolithic
The data that machine is sended over synchronize the corresponding registers in decoding, and write parameters register array；Main controller module,
Horizontal drive signals generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion driving generator module,
There is the high frequency master clock signal that module receives the output of digital dock manager module in image output timing, drive each institute
State module and produce corresponding action；
The input of main controller module is connected with the outfan of communication interface modules outfan, parameter register array module,
The control signal of communication interface modules output and the supplemental characteristic of parameter register array output are received, main controller module is controlled
The operating of internal state machine, main controller module is exported for controlling horizontal drive generator module, vertical drive generator mould
Block, correlated-double-sampling and analog digital conversion drive the control signal of generator module and image output timing generator module；
The input of horizontal drive generator module is connected with the outfan of main controller module, for receiving level control letter
Number, and generated according to control signal content and output level drive signal；
The input of vertical drive generator module is connected with the outfan of main controller module, for receiving vertical control letter
Number, and vertical driving signal is generated and exported according to control signal content；
Correlated-double-sampling and analog digital conversion drive the input of generator module to be connected with the outfan of main controller module, are used for
Correlated-double-sampling and analog digital conversion control signal are received, and correlated-double-sampling and modulus are generated and exported according to control signal content
Transition drive signal；
The input of image output timing generator module is connected with the outfan of main controller module, for receiving image sequential
Control signal, and generated according to control signal content and output image Timing driver signal.
2. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Parameter register
Device array module includes frequency parameter depositor, phase parameter depositor, duty cycle parameters depositor, at the scene FPGA
Gate array internal per the source driving signal for exporting all the way to being respectively equipped with frequency parameter depositor, phase parameter depositor, duty
Than parameter register, and it is provided with and is included by the population parameter depositor of driving charge-coupled image sensor：Total line number parameter register, have
Effect line number parameter register, total columns parameter register, effective columns parameter register, exposure time parameter depositor, synchronization
Mode parameter depositor, output mode parameter register and pixel merge parameter register.
3. it is used to according to claim 2 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Using monolithic
Machine carries out corresponding parameter register initial setting up to the source driving signal per driving charge-coupled image sensor grid all the way of output,
Realize the complete control to the source driving signal characteristic.
4. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Master controller
Module to charge-coupled image sensor imaging process in quick erasing, exposure, charge packet vertical transitions prepare, charge packet vertically turns
Move, the invalid electric charge of level empty, charge packet horizontal transfer, charge packet signal amplify, charge packet read Process Design state machine,
Control horizontal drive generator module, vertical drive generator module, correlated-double-sampling and analog digital conversion drive generator module
And image output timing generator module produces corresponding drive signal under charge-coupled image sensor different working condition.
5. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Horizontal drive
Generator module produce one group of charge packet horizontal transfer under main controller module control required for sequential, when not shifting
Close horizontal drive generator module.
6. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Vertical drive
Generator module produce one group of charge packet vertical transitions under main controller module control required for sequential, when not shifting
Close vertical drive generator module.
7. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Related pair is adopted
Sample and analog digital conversion drive generator module that the front end pretreatment to charge-coupled image sensor is completed under main controller module control
Reading the analogue signal of amplifying circuit carries out correlated-double-sampling process, eliminates reset noise, and controls correlated-double-sampling and modulus
Conversion drives generation module that the image represented with analogue signal is converted to into digital picture.
8. it is used to according to claim 1 drive the sequential generating meanss of charge-coupled image sensor, it is characterised in that：Image is exported
Timing sequencer module coordinates the digital picture generated after analog digital conversion to provide clock signal, so as to CameraLink interface circuits
Outside Digital Image Transmission to the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410106542.7A CN103888688B (en) | 2014-03-20 | 2014-03-20 | Time sequence generating device for driving charge-coupled device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410106542.7A CN103888688B (en) | 2014-03-20 | 2014-03-20 | Time sequence generating device for driving charge-coupled device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103888688A CN103888688A (en) | 2014-06-25 |
| CN103888688B true CN103888688B (en) | 2017-04-26 |
Family
ID=50957389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410106542.7A Active CN103888688B (en) | 2014-03-20 | 2014-03-20 | Time sequence generating device for driving charge-coupled device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103888688B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104394333A (en) * | 2014-11-26 | 2015-03-04 | 中国科学院国家天文台南京天文光学技术研究所 | Control system of CCD drive in South Pole Telescope |
| CN104469196A (en) * | 2014-11-26 | 2015-03-25 | 哈尔滨工程大学 | Drive device for image collecting system of interline transfer CCD sensor |
| CN104796640A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Multifunctional column sequence control circuit of oversized area-array CMOS (complementary metal oxide semiconductor) image sensor |
| CN105407274B (en) * | 2015-11-02 | 2018-08-24 | 深圳怡化电脑股份有限公司 | The method for realizing Image Acquisition using FPGA |
| CN106791499B (en) * | 2016-11-22 | 2019-06-18 | 北京空间机电研究所 | A method of realizing that improving electron multiplication CCD camera exports signal noise ratio (snr) of image |
| CN106791505B (en) * | 2016-12-29 | 2023-09-05 | 中国科学院西安光学精密机械研究所 | Time sequence generator and time sequence driving method for double-channel CCD imaging system |
| CN110516810B (en) * | 2019-08-29 | 2022-08-12 | 合肥本源量子计算科技有限责任公司 | Quantum program processing method and device, storage medium and electronic device |
| CN111405208B (en) * | 2020-03-20 | 2021-12-14 | 中国电子科技集团公司第四十四研究所 | Internally frame transferred CCD |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8537260B2 (en) * | 2009-05-08 | 2013-09-17 | Photon Etc, Inc. | Apparatus and method for low noise imaging |
| CN101839768A (en) * | 2010-05-14 | 2010-09-22 | 浙江工业大学 | Portable fiber-optic spectrometer based on CPLD and LABVIEW |
-
2014
- 2014-03-20 CN CN201410106542.7A patent/CN103888688B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103888688A (en) | 2014-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103888688B (en) | Time sequence generating device for driving charge-coupled device | |
| CN102934364B (en) | A/D converter, A/D conversion method, solid-state imaging element and camera system | |
| CN101365073B (en) | Solid-state image capture device, analog/digital conversion method for solid state image capture device, and image capture device | |
| CN102845055B (en) | Row A/D converter, row A/D conversion method, solid-state imaging element and camera system | |
| CN102307283B (en) | Solid state imaging element and camera system | |
| CN104159043B (en) | A kind of double two field picture acquisition methods of ultrahigh speed | |
| US10270987B2 (en) | System and methods for dynamic pixel management of a cross pixel interconnected CMOS image sensor | |
| US10542231B2 (en) | Method of driving image pickup device, image pickup device, image pickup system | |
| CN105144699A (en) | Threshold-monitoring, conditional-reset image sensor | |
| CN102801930A (en) | Low-power-consumption time delay integral type CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor | |
| CN103108138B (en) | Charge inducing accumulation is adopted to realize the method for area array CCD fast driving | |
| TW201735623A (en) | Method and system for reducing analog-to-digital conversion time for dark signals | |
| CN103400153A (en) | Serial filtering matching method and system for real-time image identification | |
| US20090009646A1 (en) | Configurable timing generator | |
| CN103795944A (en) | Universal area array CCD timing sequence driven generator | |
| JP2004040317A (en) | Timing signal generating apparatus, system, and imaging apparatus | |
| CN106791505A (en) | A kind of timing sequencer and sequential driving method for binary channels CCD imaging systems | |
| CN108495065B (en) | Driving time sequence control method of frame transfer type area array CCD | |
| CN102868865A (en) | Circuit and method for combining image pixels | |
| CN104580947B (en) | Reduce the method and image sensing system of the harmonic tones of the noise in imaging sensor | |
| Li et al. | Method to implement the CCD Timing Generator Based on FPGA | |
| CN101198206B (en) | Data acquiring and control circuit for radiation imaging and method thereof | |
| JP2004228874A (en) | Image processor, image processing method and solid-state imaging apparatus | |
| CN102300056A (en) | Method for improving area array charge coupled device (CCD) frame frequency and high-frame-frequency CCD device | |
| JP2004228872A (en) | Image processor, image processing method and solid-state imaging apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |