CN108184081A - A kind of high-speed data reading circuit in cmos image sensor - Google Patents
A kind of high-speed data reading circuit in cmos image sensor Download PDFInfo
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- CN108184081A CN108184081A CN201810036986.6A CN201810036986A CN108184081A CN 108184081 A CN108184081 A CN 108184081A CN 201810036986 A CN201810036986 A CN 201810036986A CN 108184081 A CN108184081 A CN 108184081A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/767—Horizontal readout lines, multiplexers or registers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Abstract
The present invention relates to a kind of high-speed data reading circuit in cmos image sensor, the circuit is for carrying out the voltage that photosurface battle array exports sampling holding, AD conversion, high-speed interface output, suitable for the high frame rate cmos image sensor using row grade ADC.The high speed data transfer is electrically connected to after each column pixel, is made of sampling hold circuit, row adc circuit, row LVDS output circuits.Reset signal that circuit exports each column pixel, photogenerated signals carry out analog-to-digital conversion by assembly line sampling hold circuit, row adc circuit, then latch holding circuit by pipeline system and be output to row LVDS circuits, realize the high-speed transfer of data.The method according to the invention can realize the high speed data transfer of various face battle arrays, and with smaller circuit scale.
Description
Technical field
The present invention relates to cmos image sensor field, a kind of high speed number in cmos image sensor when special
According to transmission reading circuit, suitable for using row grade adc circuit structure, data are effectively improved on the basis of AD conversion precision is ensured
Transmission rate.
Background technology
CMOS (complementary metal oxide semiconductor) imaging sensor generally comprises photosensitive pixel array, row and column decoding electricity
Road, reading circuit etc..Photosensitive pixel array converts optical signal into electric signal, and row/column decoding circuit is completed in pixel array
The addressing of area-of-interest pixel, reading circuit read and handle the pixel photogenerated signals being addressed.
There are two types of Exposure modes for cmos image sensor：Roll exposure and global exposure.4T, which rolls exposure pixel, to be led to
Correlated-double-sampling is crossed to reduce noise, but when often row exposure is different, in silent frame high-speed capture image, the non-concurrent property of exposure
Image fault and deformation can be caused；5T structures pixel can be realized global while be exposed, and ensure signal digital-to-analogue conversion precision
Meanwhile optimization reading circuit structure and sequential can further improve the frame frequency of imaging sensor.
In cmos image sensors, there are mainly three types of frameworks for the integration mode of ADC：Chip-scale, Pixel-level and row are parallel
Grade.Chip-scale ADC integrates core devices and single ADC module on one chip, this structure occupies small, pixel in area and fills out
It is higher to fill the factor, but power consumption height and non-parallel processing, it is very high to ADC conversion speed requirements.Pixel-level ADC, that is, each pixel or several
A pixel shares an ADC, samples the working method of complete parallel, signal-to-noise ratio is high, ADC rate requests are low, small power consumption, but it is filled out
It is low to fill the factor, and dark current and pixel-level fusion influence greatly.Each column pixel shares an ADC in row grade ADC, that is, pel array, as
Pixel array is read line by line, this one-row pixels carries out analog-to-digital conversion by each row ADC concurrent workings, then serially transmits one by one again
It is exported to interface.Row grade ADC is the compromise to chip-scale ADC and Pixel-level ADC, and design difficulty is low and autgmentability is strong, Ke Yishi
Answer the demand of big array high speed data transfer.
Invention content
Present invention solves the technical problem that：It has overcome the deficiencies of the prior art and provide a kind of for cmos image sensor
In high speed data transmission reading circuit, pel array output voltage signal is amplified, sample holding, analog-to-digital conversion,
Interface exports, and message transmission rate can be improved, in the case where ensureing data precision so as to improve the frame of cmos image sensor
Frequently.
The present invention technical solution be：
A kind of high speed data transmission reading circuit in cmos image sensor is provided, cmos image sensor is common
Q is arranged, and high speed data transfer circuit includes Q/N transmission channel, and each transmission channel includes N number of row reading circuit and N roads gate
Module, each row reading circuit include Programmable Gain Amplifier Circuit, sampling hold circuit, row analog to digital conversion circuit wherein：
Programmable Gain Amplifier Circuit receives the pixel unit of externally input reference voltage and respective column imaging sensor
The signal of output, when the signal of pixel unit output is photogenerated signals Vsig, output signal VREF_AFE=Vref1；Work as signal
Output VSIG_AFE=Vref1+K* (Vsig-Vres) when the signal of pixel unit output is reset signal Vres；
The signal of sampling hold circuit acquisition Programmable Gain Amplifier Circuit output, and by VREF_AFE and VSIG_AFE points
It Bao Chi not export；
Row analog to digital conversion circuit obtains K* (Vsig-Vres) after the signal that sampling hold circuit exports is handled, and turns
Change clock signal into, actuation counter, which count, obtains exposure useful signal；
N roads gating module enables the row in N number of row reading circuit, output exposure useful signal.
A kind of high speed data transmission read-out channel in cmos image sensor is provided, electricity is read including N number of row
Road and N roads gating module, each row reading circuit include Programmable Gain Amplifier Circuit, sampling hold circuit, row analog-to-digital conversion
Circuit is wherein：
Programmable Gain Amplifier Circuit receives the pixel unit of externally input reference voltage and respective column imaging sensor
The signal of output, when the signal of pixel unit output is photogenerated signals Vsig, output signal VREF_AFE=Vref1；Work as signal
Output VSIG_AFE=Vref1+K* (Vsig-Vres) when the signal of pixel unit output is reset signal Vres；
The signal of sampling hold circuit acquisition Programmable Gain Amplifier Circuit output, and by VREF_AFE and VSIG_AFE points
It Bao Chi not export；
Row analog to digital conversion circuit obtains K* (Vsig-Vres) after the signal that sampling hold circuit exports is handled, and turns
Change clock signal into, actuation counter, which count, obtains exposure useful signal；
N roads gating module enables the row in N number of row reading circuit, output exposure useful signal.
Preferably, Programmable Gain Amplifier Circuit is switched capacitor amplifier circuit.
Preferably, it is characterised in that：Programmable Gain Amplifier Circuit includes capacitance C0, capacitance C1, switch CTRL0 and compares
The positive input terminal of device P1, comparator P1 receive externally input reference voltage Vref 1, the negative input end of comparator P1 passes through capacitance
C0 receives the pixel unit output Vpixel signals of cmos image sensor.
Preferably, the L periodic signals of sampling hold circuit acquisition Programmable Gain Amplifier Circuit output, and by VREF_
AFE and VSIG_AFE keeps and reads respectively respectively；And read respectively the L periods keep signal while acquisition is programmable increases
The L+1 periodic signals of beneficial amplifying circuit output, and VREF_AFE and VSIG_AFE are kept respectively, while reading L+1
Period keeps the L+2 periodic signals of acquisition Programmable Gain Amplifier Circuit output while signal, so recycles, and N-1 >=L >=
0。
Preferably, including read switch SAS, SAR, RAS, RAR, SBS, SBR, RBS, RBR, capacitance CAS, CAR, CBS,
CBR,
When L period photogenerated signals Vsig is reached, SAS conductings, L periods VREF_AFE signal is sampled through capacitance CAS and is protected
It holds, while RBS is connected, the VREF_AFE signals in L-1 periods are exported to row analog to digital conversion circuit；L cycle reset signals
When Vres is reached, SAR conductings, L periods VSIG_AFE signal is sampled through capacitance CAR and is kept, while RBR is connected, the L-1 periods
VSIG_AFE export to row analog to digital conversion circuit；
When L+1 period photogenerated signals Vsig is reached, SBS conductings, L+1 period VREF_AFE signals are adopted through capacitance CBS
Sample is kept, while RAS is connected, and the VREF_AFE signals in L periods are exported to row analog to digital conversion circuit；L+1 cycle resets are believed
When number Vres is reached, SBR conductings, L+1 periods VSIG_AFE signal is sampled through capacitance CBR and is kept, while RAR is connected, the L weeks
The VSIG_AFE of phase is exported to row analog to digital conversion circuit.
Preferably, row analog to digital conversion circuit includes slope generating circuit, CL Compare Logic circuit and counter circuit；
Slope generating circuit generates the identical first order ramp reference voltage of slope and second level ramp reference voltage respectively
It exports to the normal phase input end of CL Compare Logic circuit, the first order is identical with the initial value of second level ramp reference voltage to be less than
Row grade reference voltage VREF_AFE, the maximum value of second level ramp reference voltage are more than VSIG_AFE, first order ramp reference electricity
The duration of pressure is less than the 1/3 of second level ramp reference voltage duration；
CL Compare Logic circuit compares the VREF_AFE that sampling hold circuit exports with first order ramp reference voltage
Compared with when the equal hour counter circuit of the two is started counting up until first order ramp reference voltage terminates；Sampling hold circuit is defeated
The VSIG_AFE gone out is compared with second level ramp reference voltage, and when the second level, ramp reference voltage starts hour counter circuit
Continue to count, when VSIG_AFE is equal with second level ramp reference voltage, stops counting, the count value of counter circuit is carried out
It latches, on N roads, gating module enables exports under control.
Preferably, counter circuit includes T d type flip flop, shift counter is configured to, in each d type flip flop output terminal
One latch holding circuit of connection, T is the digit for requiring analog-to-digital conversion.
Preferably, holding circuit is latched, including switch S1, S2, S1N, S2N and 4 phase inverters；Two phase inverters reversely connect
Connect composition buffer；
When the signal of L rows is finished through counter circuit counting, S1 conductings, the buffered device of counter circuit output signal
It keeps, S1 turn-on times are more than or equal to the transmission time of S1；S2 is connected, and counter circuit output signal can be read, and S2 is led
The logical time is T1*N, and T1 is the transmission time of S2；
When the signal of L+1 rows is finished through counter circuit counting, S1N conductings, counter circuit output signal is through slow
Device holding, S2N conductings are rushed, counter circuit output signal can be read；
Preferably, it latches holding circuit and further includes output of the triple gate for control counter circuit, multiplexer circuit
Generate the enable signal of triple gate.
The present invention being a little compared with prior art：
(1) present invention by Programmable Gain Amplifier Circuit, sampling hold circuit to the reset signal voltage of each column pixel
It is sampled with photogenerated signals voltage, row adc circuit carries out analog-to-digital conversion, can generate voltage by adjusting timing Design and slope
Module design is supported to roll two kinds of Exposure modes of exposure and global exposure.
(2) feature of switched-capacitor circuit is utilized in Programmable Gain Amplifier Circuit of the present invention, realizes row and reads electricity
The difference of the reset signal Vres and photogenerated signals Vsig of road output, eliminate Pixel-level steady noise, realize simply, in row grade circuit
The area of upper occupancy is small, at low cost.
(3) present invention is by sampling hold circuit by being divided into two groups, and the sampling of one-row pixels is completed in one group of control, another group
Next line pixel sampling is completed in control, and two groups of combinations realize the pipeline system sampling of two row pixels, improve sample rate.
(4) grouping of each row reading circuit is connected to output channel by circuit of the present invention, and serial mode is defeated between respectively being arranged in every group
Go out, data parallel exports between each group, and the reading of entire array, transmission time are the data reading of every group of channel, transmission time.
And every group of channel has control signal to carry out selecting to enable, and can realize that image level direction picture is optional, can reduce chip work(
Consumption reduces data volume.
(5) circuit of the present invention belongs to row grade circuit, and use can be extended in the array CMOS image sensor of bigger face, reduces
Research and develop time and cost.
Description of the drawings
Fig. 1 is image sensor architecture schematic diagram；
Fig. 2 is high speed data transfer electrical block diagram
Fig. 3 is that the sampling of amplifying circuit and sampling hold circuit keeps flow line circuit schematic diagram；
Fig. 4 is latches viewing pipeline circuit diagram in row ADC counters；
Fig. 5 is exposure, sampling, pipeline sequential twice in readout；
Fig. 6 is row ADC counting principle schematic diagrames.
Specific embodiment
The specific embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.
The present invention provides a kind of cmos image sensor high speed data transfer circuit, is exposed suitable for overall situation exposure, rolling
Two kinds of Exposure modes and the imaging sensor using row grade adc circuit.
As shown in Figure 1, speedy carding process transmission circuit includes Programmable Gain Amplifier Circuit PGA, sampling hold circuit SH, row
Analog to digital conversion circuit ADC and output interface circuit, wherein：
Programmable Gain Amplifier Circuit PGA including capacitance C0, capacitance C1, switch CTRL0 and comparator P1, is constituted out
Close capacitor amplifier circuit.
The positive input terminal of comparator P1 receives externally input reference voltage Vref 1, the negative input end of comparator P1 passes through
Capacitance C0 receives the pixel unit output Vpixel signals of cmos image sensor.Under global exposure mode, Vpixel signals
Pixel unit including focal plane cmos image sensor first exports exposure integral voltage signal Vsig, then exports resetting voltage letter
Number Vres, in photogenerated signals Vsig sampling period, reference voltage Vref 1 with output to CAS, is obtained row grade with reference to electricity by SAS
Press VREF_AFE；In reset signal Vres sampling period, the pressure difference of reset signal Vres and photogenerated signals Vsig is obtained, by opening
Powered-down capacitive circuit is amplified K times and adds up output to CAR with row grade reference voltage VREF_AFE, so as to obtain row grade photoproduction electricity
Press VSIG_AFE；Under the control of externally input RAS gating signals and RAR gating signals, successively obtained row grade is referred to
Voltage VREF_AFE and row grade photogenerated signals voltage VSIG_AFE reads out to the negative-phase input of CL Compare Logic circuit；The K >=
1。
Output voltage values finally through Programmable Gain Amplifier Circuit PGA are：
VREF_AFE=Vref1
VSIG_AFE=Vref1+K* (Vsig-Vres)
Wherein, K is the gain of programmable gain circuit, can as needed be designed by designer.In global exposure mode
Under, VSIG_AFE is less than VREF_AFE.By PGA circuits, Pixel-level reset signal and optical signal are made the difference, disappeared
In addition to most of noise such as 1/f noise, KTC noise, the fixed pattern noise for being present in Pixel-level is eliminated, is read so as to reduce
Go out influence of the circuit to image quality.
Sampling hold circuit SH by including read switch SAR, SAS, RAR, RAS, SBR, SBS, RBR, RBS, capacitance CAR,
CAS, CBR, CBS are divided into two groups of A, B, and the sampling of one-row pixels is completed in one group of control, and another group of control is completed next line pixel and adopted
The pipeline system sampling of two row pixels is realized in sample, two groups of combinations.By taking A groups acquire L row pixel samplings as an example, read switch SAR,
The tie point of SAS is the input of sampling hold circuit, and capacitance CAR one end is connected between read switch SAR, RAR, another termination
Ground；Capacitance CAS one end is connected between read switch SAS, RAS, other end ground connection；The tie point of read switch RAR and RAS is adopt
The output of sample holding circuit.
During SAS high level, the exposure of Vpixel output pixels integrated signal Vsig, SAS arrive VREF_AFE Sampling holds
CAS；During SAR high level, Vpixel output pixel resetting voltages Vres, SAR is by VSIG_AFE Sampling holds to CAR；At this point, the
The sampling process for the related useful signal that L rows pixel exposure generates is completed.Then RAS is high level, by the VREF_AFE in CAS
It reads；RAR high level reads the VSIG_AFE in CAR, while SBS, SBR start to sample the pixel exposure output of L+1 rows
Vpixel carries out sampling reading by identical sequential relationship.While L+1 rows signal is by B group SH circuit samplings, L row pixels
During exposure signal is in by the reading of A group SH circuits.After A group SH circuits complete the reading of L row pixel Vpix signals,
The sampling to L+2 row Vpix signals is immediately begun to, B groups SH circuits start the reading of the Vpix to L+1 rows at this time.The first order
Pipeline sampling time sequences are as shown in Figure 5.
The signal transmission that sampled holding circuit SH is sampled out gives row adc circuit.Through CL Compare Logic circuit, logical transition electricity
Road is converted into clock signal clk _ OUT, and CLK_OUT inputs to counter driving shift count, obtains digital signal, such as Fig. 2 again
It is shown.
By the image sensor architecture schematic diagram of Fig. 1 it is found that full figure pixel array Q is arranged, it is divided into Q/N groups, that is, it is a defeated corresponds to Q/N
Go out channel.Every group has N row pixel columns, and the row ADC of each column pixel includes a shift counter；N row reading circuits in every group
Counter is carried out at the same time counting, and N row ADC exports the AD conversion of N number of counter simultaneously as a result, the digital signal of i.e. N number of Tbit；So
Afterwards again by the enabled output signal in N positions in every group, by N number of digital signal Serial output.
As shown in fig. 6, row grade reference voltage VREF_AFE, row grade light that comparator successively exports sampling hold circuit SH
Raw voltage VSIG_AFE is compared with ramp reference voltage signal, is more than row grade reference voltage in first order ramp reference voltage
VREF_AFE, second level ramp reference voltage generate the enabled letter of clock output in the case of being less than row grade photovoltage VSIG_AFE
Number to logic control circuit, output clock signal clk _ OUT is extremely under the control of clock output enable signal for logic control circuit
Counter.
First, row grade reference voltage VREF_AFE is compared with first order ramp voltage, and ramp voltage is since the t1 moment
First order slope Vramp1 when Vramp1 is equal with row grade reference voltage VREF_AFE, is denoted as the t2 moment, starts to export clock
CLK_OUT, counter start counting up；First order slope Vramp1 stops rising in t3, stops output clock CLK_OUT, counts
Device stops counting；Then, signal voltage VSIG_AFE is compared with the ramp voltage Vramp2 of the second level, and Vramp2 is from the t4 moment
Begin, output clock CLK_OUT is continued to output；When Vramp2 is equal with resetting voltage VSIG_AFE, it is denoted as t5 moment, the second level
Ramp voltage stopped rising at the t6 moment, and CL Compare Logic circuit output is in t2~t3, t4~t5 periods effective clock letter at this time
Number CLK_OUT.
The structure of counter is configured to shift counter as shown in figure 4, including T d type flip flop, defeated in each d type flip flop
Outlet, which adds in, latches holding circuit, realizes the output of second level pipeline data.Latch holding circuit include switch S1, S2,
S1N, S2N, 4 reversers and a triple gate.
Clock signal clk _ OUT that clock is CL Compare Logic circuit output is triggered, control counter is in the first effectual time
The t2 moment starts counting up, and the t3 moment stops to count, count value Cnt1；Second effectual time t4 moment started on Cnt1 bases
On start counting up, stop counting to the t5 moment, the value of count value Cnt2, Cnt2 illustrates row grade photovoltage VSIG_AFE
And the difference of row grade reference voltage VREF_AFE：VSIG_AFE-VREF_AFE=Vref+K* (Vsig-Vres)-Vref=K*
(Vsig–Vres)
S1 latches L row signals, S2 outputs；S1N latches L+1 row signals, S2N outputs.Second level pipeline is sampled
Sequential is as shown in Figure 5.TrL be L rows pixel since end exposure, start by reading circuit sample read by LVDS export when
Between, trL+1 is L+1 rows pixel since end exposure, starts to be sampled by reading circuit and read into time for being exported by LVDS.In S2
Between high period, Vrout is the AD conversion of the N row of L rows as a result, i.e. N number of Tbit digital signals.Pass through the enabled letter of triple gate
Number, row ADC transformation results is controlled to export.
By multiplexer circuit, enabled, the output column signal Vrout of control each column triple gate.Vrout is connected to correspondence
LVDS channels, Tbit parallel digital signals are carried out and turn string manipulation, output serial signal OUT.Q/N LVDS Channel Synchronous
It carries out, output OUT0-OUT (Q/N-1).
The above, best specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (10)
1. a kind of high speed data transmission reading circuit in cmos image sensor, the common Q row of cmos image sensor,
It is characterized in that, high speed data transfer circuit includes Q/N transmission channel, and each transmission channel includes N number of row reading circuit and N roads
Gating module, each row reading circuit include Programmable Gain Amplifier Circuit (PGA), sampling hold circuit (SH), row modulus and turn
Change circuit (ADC) wherein：
Programmable Gain Amplifier Circuit (PGA) receives externally input reference voltage (Vref1) and respective column imaging sensor
The signal (Vpixel) of pixel unit output, when the signal (Vpixel) of pixel unit output is photogenerated signals Vsig, output letter
Number VREF_AFE=Vref1；VSIG_ is exported when the signal (Vpixel) of signal pixels unit output is reset signal Vres
AFE=Vref1+K* (Vsig-Vres)；
The signal that sampling hold circuit (SH) acquisition Programmable Gain Amplifier Circuit (PGA) exports, and by VREF_AFE and VSIG_
AFE keeps exporting respectively；
Row analog to digital conversion circuit (ADC) signal that sampling hold circuit (SH) exports is handled after obtain K* (Vsig-
Vres), clock signal is converted into, actuation counter, which count, obtains exposure useful signal；
N roads gating module enables the row in N number of row reading circuit, output exposure useful signal.
2. a kind of high speed data transmission read-out channel in cmos image sensor, including N number of row reading circuit and N roads
Gating module, each row reading circuit include Programmable Gain Amplifier Circuit (PGA), sampling hold circuit (SH), row modulus and turn
Change circuit (ADC) wherein：
Programmable Gain Amplifier Circuit (PGA) receives externally input reference voltage (Vref1) and respective column imaging sensor
The signal (Vpixel) of pixel unit output, when the signal (Vpixel) of pixel unit output is photogenerated signals Vsig, output letter
Number VREF_AFE=Vref1；VSIG_ is exported when the signal (Vpixel) of signal pixels unit output is reset signal Vres
AFE=Vref1+K* (Vsig-Vres)；
The signal that sampling hold circuit (SH) acquisition Programmable Gain Amplifier Circuit (PGA) exports, and by VREF_AFE and VSIG_
AFE keeps exporting respectively；
Row analog to digital conversion circuit (ADC) signal that sampling hold circuit (SH) exports is handled after obtain K* (Vsig-
Vres), clock signal is converted into, actuation counter, which count, obtains exposure useful signal；
N roads gating module enables the row in N number of row reading circuit, output exposure useful signal.
3. high speed data transmission reading circuit or claim 2 in cmos image sensor according to claim 1
High speed data transmission read-out channel in the cmos image sensor, it is characterised in that：Programmable Gain Amplifier Circuit
(PGA) it is switched capacitor amplifier circuit.
4. the high speed data transmission reading circuit or cmos image in cmos image sensor according to claim 3 pass
High speed data transmission read-out channel in sensor, it is characterised in that：Programmable Gain Amplifier Circuit (PGA) including capacitance C0,
Capacitance C1, CTRL0 and comparator P1 is switched, the positive input terminal of comparator P1 receives externally input reference voltage Vref 1, compares
The pixel unit that the negative input end of device P1 receives cmos image sensor by capacitance C0 exports Vpixel signals.
5. high speed data transmission reading circuit or claim 2 in cmos image sensor according to claim 1
High speed data transmission read-out channel in the cmos image sensor, it is characterised in that：Sampling hold circuit (SH) is adopted
Collect the L periodic signals that Programmable Gain Amplifier Circuit (PGA) exports, and VREF_AFE and VSIG_AFE are kept and divided respectively
It does not read；And read respectively the L periods keep signal while acquisition Programmable Gain Amplifier Circuit (PGA) export L+
1 periodic signal, and VREF_AFE and VSIG_AFE are kept respectively, while is adopted while signal is kept in the reading L+1 periods
Collect the L+2 periodic signals that Programmable Gain Amplifier Circuit (PGA) exports, so recycle, N-1 >=L >=0.
6. high speed data transmission reading circuit or claim 2 in cmos image sensor according to claim 1
High speed data transmission read-out channel in the cmos image sensor, it is characterised in that：Including read switch SAS,
SAR, RAS, RAR, SBS, SBR, RBS, RBR, capacitance CAS, CAR, CBS, CBR,
When L period photogenerated signals Vsig is reached, SAS conductings, L periods VREF_AFE signal is sampled through capacitance CAS and is kept, together
When RBS be connected, the VREF_AFE signals in L-1 periods are exported to row analog to digital conversion circuit (ADC)；L cycle reset signals
When Vres is reached, SAR conductings, L periods VSIG_AFE signal is sampled through capacitance CAR and is kept, while RBR is connected, the L-1 weeks
The VSIG_AFE of phase is exported to row analog to digital conversion circuit (ADC)；
When L+1 period photogenerated signals Vsig is reached, SBS conductings, L+1 periods VREF_AFE signal is sampled through capacitance CBS and is protected
It holds, while RAS is connected, the VREF_AFE signals in L periods are exported to row analog to digital conversion circuit (ADC)；L+1 cycle resets are believed
When number Vres is reached, SBR conductings, L+1 periods VSIG_AFE signal is sampled through capacitance CBR and is kept, while RAR is connected, the L weeks
The VSIG_AFE of phase is exported to row analog to digital conversion circuit (ADC).
7. the high speed data transmission reading circuit or cmos image in cmos image sensor according to claim 6 pass
High speed data transmission read-out channel in sensor, it is characterised in that：Row analog to digital conversion circuit (ADC) generates electricity including slope
Road, CL Compare Logic circuit and counter circuit；
Slope generating circuit generates the identical first order ramp reference voltage of slope and second level ramp reference voltage output respectively
To the normal phase input end of CL Compare Logic circuit, the first order is identical with the initial value of second level ramp reference voltage to be less than row grade
Reference voltage VREF_AFE, the maximum value of second level ramp reference voltage are more than VSIG_AFE, first order ramp reference voltage
Duration is less than the 1/3 of second level ramp reference voltage duration；
CL Compare Logic circuit compares the VREF_AFE that sampling hold circuit (SH) exports with first order ramp reference voltage
Compared with when the equal hour counter circuit of the two is started counting up until first order ramp reference voltage terminates；By sampling hold circuit
(SH) VSIG_AFE of output is compared with second level ramp reference voltage, is counted when the second level, ramp reference voltage starts
Device circuit continues to count, and when VSIG_AFE is equal with second level ramp reference voltage, stops counting, by the counting of counter circuit
Value is latched, and on N roads, gating module enables exports under control.
8. the high speed data transmission reading circuit or cmos image in cmos image sensor according to claim 7 pass
High speed data transmission read-out channel in sensor, it is characterised in that：Counter circuit includes T d type flip flop, is configured to shift
Counter connects a latch holding circuit in each d type flip flop output terminal, and T is the digit for requiring analog-to-digital conversion.
9. the high speed data transmission reading circuit or cmos image in cmos image sensor according to claim 8 pass
High speed data transmission read-out channel in sensor, it is characterised in that：Holding circuit is latched, including switching S1, S2, S1N, S2N
With 4 phase inverters；Two phase inverter Opposite direction connections form buffer；
When the signal of L rows is finished through counter circuit counting, S1 conductings, the buffered device of counter circuit output signal is protected
It holds, S1 turn-on times are more than or equal to the transmission time of S1；S2 is connected, and counter circuit output signal can be read, S2 conductings
Time is T1*N, and T1 is the transmission time of S2；
When the signal of L+1 rows is finished through counter circuit counting, S1N conductings, the buffered device of counter circuit output signal
It keeps, S2N conductings, counter circuit output signal can be read.
10. high speed data transmission reading circuit or cmos image in cmos image sensor according to claim 9
High speed data transmission read-out channel in sensor, it is characterised in that：It latches holding circuit and further includes triple gate for controlling
The output of counter circuit, multiplexer circuit generate the enable signal of triple gate.
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