CN106375688A - CMOS image sensor and signal transmission method thereof - Google Patents
CMOS image sensor and signal transmission method thereof Download PDFInfo
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- CN106375688A CN106375688A CN201610803630.1A CN201610803630A CN106375688A CN 106375688 A CN106375688 A CN 106375688A CN 201610803630 A CN201610803630 A CN 201610803630A CN 106375688 A CN106375688 A CN 106375688A
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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Abstract
The invention discloses a full-frame CMOS image sensor comprising: a plurality of effective pixels, wherein each pixel comprises an imaging pixel array; a readout circuit used for carrying out pixel analog signal amplification and analog-digital conversion and comprises a plurality of readout sub-circuits which are respectively configured to correspond to each column of the imaging pixel array; a transmission module comprising a plurality of transmission channels; an interface circuit comprising a plurality of interface sub-circuits; a first control unit used for controlling exposure and signal sampling of the imaging pixels, sequentially selecting rows in the effective pixels, and selecting analog signals of the effective pixels in the selected rows and outputting the analog signals to the readout sub-circuits at the same time; a second control unit used for driving each transmission channel of the transmission module to transmit digital signals of the plurality of effective pixels in sequence, and controlling each interface sub-circuit to sequentially output a plurality of digital signals to the outside, the plurality of transmission channels carry out parallel transmission during each transmission, and the plurality of interface sub-circuits carry out parallel output during each output. The full-frame CMOS image sensor disclosed by the invention can effectively improve the frame rate of the CMOS image sensor.
Description
Technical field
The present invention relates to field of image sensors, particularly to a kind of cmos imageing sensor and its method for transmitting signals.
Background technology
Traditional photographing unit film a size of 35mm, 35mm are the width (including perforation part) of film, 35mm film
Photosensitive area is 36x24mm.The component size of the photosensitive imaging of the cmos of slr camera and 135 films equivalently-sized
36x24mm, referred to as " silent frame ".In slr camera, silent frame belongs to high-grade camera, such as Nikon d5, Sony alpha
7rm2, Canon eos 6d etc., all using silent frame imageing sensor.Typically, since the sensor array size of silent frame
Greatly, the Pixel Dimensions under same pixel quantity are also big, therefore can obtain better image quality and color representation power.
The cmos imageing sensor of camera can adopt two kinds of Exposure modes: rolling exposes (rolling shutter) and complete
Office's exposure (global shutter).Traditional 4t cylinder exposure pixel (rolling shutter pixel), including transmission
This four transistors of pipe, reset transistor, source follower and row gate tube.Its signal-obtaining principle is the signal when reset transistor
When rx moves high level to, the electric charge of suspension node fd is emptied and is resetted, then signal rx of reset transistor be set to low
Level when signal tx of transfer tube is put high, the signal of light sensitive diode pd will be transferred to fd point, subsequently complete letter
Number read.That is, for the pixel array of the imageing sensor x row y row of traditional 4t pixel composition, the first row first
The time of exposure that the time of exposure of row is arranged with xth row y is not simultaneously.This non-concurrent does not have for general camera application
Problematic, but during for silent frame camera high frame per second shooting image, then can cause obvious image fault and deformation.So it is right
In the silent frame imageing sensor of high frame per second, need to realize by overall pixel (global shutter pixel).
Content of the invention
A kind of silent frame overall situation pixel of high frame per second, present invention is primarily targeted at overcoming the defect of prior art, is provided
Cmos imageing sensor.
For reaching above-mentioned purpose, the present invention provides a kind of cmos imageing sensor, comprising: by multiple valid pixels and multiple
The pel array of inactive pixels composition, wherein each described valid pixel and inactive pixels are overall pixel；Described valid pixel
It is arranged as q row；Reading circuit, it includes q reading electronic circuit, corresponds to every string configuration of described valid pixel respectively, each
The described electronic circuit that reads includes the variable gain amplifier for amplifying the analogue signal of valid pixel and is used for amplification
Valid pixel analogue signal is converted to the analog-digital converter of digital signal；Transport module, it includes n transmission channel, each biography
The digital signal of defeated passage q/n valid pixel of corresponding transmission；Interface circuit, including the n corresponding with described n transmission channel
Individual interface subcircuit, the digital signal for being transmitted described transmission channel exports to outside；First control unit, controls each
Described imaging pixel exposes simultaneously, signal sampling, chooses each row of described valid pixel, and control selected line q successively
The analogue signal of valid pixel exports to described q reading electronic circuit simultaneously；Second control unit, makes the of described transport module
I transmission channel transmit successively q × i/n+1 to the digital signal of q × i/n+n valid pixel to described interface circuit and
When transmitting every time, n transmission channel is parallel transmission,；And control i-th interface subcircuit to be sequentially output described q × i/n+
1 is parallel output to the digital signal of q × i/n+n valid pixel to n interface subcircuit during outside and each output；Its
Middle p, q, n, q/n are positive integer, and i is the numbering of transmission channel and is the positive integer being less than or equal to n more than or equal to 1.
Preferably, described silent frame cmos imageing sensor also includes gain module, with described reading circuit and described biography
Defeated module is connected, and the digital signal for changing described analog-digital converter transmits to described transport module after amplifying.
Preferably, described first control unit described reading circuit each variable gain amplifier by amplify after simulation
Signal output chooses next line valid pixel to each analog-to-digital conversion module.
Preferably, described inactive pixels include redundant sub-pixels and isolation pixel, and described valid pixel includes imaging pixel group
Imaging pixel array, dark pixel and the reference pixel becoming；Pass through institute between described reference pixel, dark pixel and imaging pixel array
State isolation pixel and/or redundant sub-pixels isolation；Described dark pixel includes being arranged as multirow along the line direction of described pel array
Part I and the column direction along described pel array are arranged as the Part II of multiple row.
Preferably, described transport module includes m submodule, and each submodule includes n/m transmission channel, wherein m and
N/m is positive integer, and m is more than or equal to 2.
Present invention also offers a kind of method for transmitting signals of above-mentioned silent frame cmos imageing sensor, walk including following
Rapid:
Step s1: make described imaging pixel array simultaneously expose and signal sampling；
Step s2: choose certain a line of described valid pixel, to the analogue signal of each described valid pixel of this row simultaneously
It is amplified processing；
Step s3: the analogue signal of the amplified each described valid pixel of this row is simultaneously converted into digital signal；
Step s4: the digital signal of each described valid pixel of this row is divided into n group, wherein every group of q/n numeral letter
Number be sequentially output, and each when exporting n group digital signal export simultaneously；
Repeat step s2 is to step s4 until the signal of at least this imaging pixel array all exports.
Preferably, also include the step that the digital signal of conversion is amplified before step s4 after step s3.
Preferably, in step 2, the analogue signal of current selected line is amplified and choose next line valid pixel after exporting simultaneously
Amplify its analogue signal.
Preferably, described inactive pixels include redundant sub-pixels and isolation pixel, and described valid pixel includes imaging pixel group
Imaging pixel array, dark pixel and the reference pixel becoming；Pass through institute between described reference pixel, dark pixel and imaging pixel array
State isolation pixel and/or redundant sub-pixels isolation；Described dark pixel includes being arranged as multirow along the line direction of described pel array
Part I and the column direction along described pel array are arranged as the Part II of multiple row.
Preferably, described transport module includes m submodule, and each submodule includes n/m transmission channel, wherein m and
N/m is positive integer, and m is more than or equal to 2.
It is an advantage of the current invention that passing through each transmission channel of controlling transmission module and each electronic circuit of interface circuit
All parallel data processings, further control the variable gain amplifier of reading circuit and analog-digital converter, transmission channel and
Interface subcircuit carries out the work of pipeline system, substantially increases work efficiency, increased the frame per second of cmos imageing sensor.
Brief description
Fig. 1 show the block chart of the overall pixel cmos imageing sensor of one embodiment of the invention；
The circuit that Fig. 2 show an overall pixel in the overall pixel cmos imageing sensor of one embodiment of the invention shows
It is intended to；
Fig. 3 show the structure chart of the overall pixel cmos image sensor pixel array of one embodiment of the invention；
Fig. 4 show the sequential chart of the overall pixel cmos image sensor signal transmission of one embodiment of the invention.
Specific embodiment
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.Certainly the invention is not limited in this specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Fig. 1 is the block chart of the overall pixel cmos imageing sensor of the present invention, as illustrated, cmos imageing sensor bag
Include pel array 10, reading circuit 20, transport module 30, interface circuit 40, the first control unit 51, the second control unit 52.
Pel array 10 is made up of multiple valid pixels and inactive pixels, and wherein each pixel is overall pixel, and valid pixel is q
Row.Refer to Fig. 3, in the present embodiment, each Pixel Dimensions of pel array are 6.0um, pel array includes 4124 × 6116 altogether
Individual pixel, imaging pixel array includes 4000 × 6000 imaging pixels.Inactive pixels include redundant sub-pixels (dummy
Pixel), isolation pixel (barrier pixel)；Valid pixel includes the imaging being made up of imaging pixel (active pixel)
Pel array, dark pixel (dark pixel), redundant sub-pixels (dummy pixel).Wherein, dark pixel (dark pixel), superfluous
After image element (dummy pixel), isolation pixel (barrier pixel) and reference pixel (reference pixel) all can not
For photosensitive.In the present embodiment, dark pixel includes effective dark pixel and edge dark pixel, and the effect of effective dark pixel is to neutralize
The striped (although the signal output of edge dark pixel but inoperative or its effect is less) of column direction and/or line direction, reference
Can be used for after pixel applied voltage neutralizing the striped of column direction or can be used for testing analog-to-digital conversion module.Redundant sub-pixels
For preventing edge effect, isolation pixel is ground connection to prevent pixel-level fusion.In the present embodiment, reference pixel is set to edge
The line direction of pel array is arranged as multirow.Dark pixel is set to two parts, Part I is along the line direction row of pel array
It is classified as multirow, Part II is arranged as multiple row along the column direction of pel array.Imaging pixel array is surrounded by redundant sub-pixels, reference
Pass through to isolate pixel isolation between pixel and dark pixel and between dark pixel and the redundant sub-pixels surrounding imaging pixel array.Please
Referring to Fig. 2, each imaging pixel is 8t (8 transistor) overall situation pixel, including for the optical signal of reception is converted to the signal of telecommunication
Light sensitive diode pd, transfer tube m1, suspension node fd, reset transistor m2, the first source follower m3, preliminary filling fulgurite m4, first open
Close pipe m5, second switch pipe m6, the first sampling holding capacitor c1, the second sampling holding capacitor c2, the second source follower m7 and row
Gate tube m8.The annexation of each transistor is as follows:
The source electrode of transfer tube m1 connects light sensitive diode, drain electrode and the grid of the first source follower m3 and the source of reset transistor m2
Pole is commonly connected to suspension node fd, grid is controlled by control signal tx；
The drain electrode of preliminary filling fulgurite m4 and the source electrode of the first source follower m3 are connected to the source electrode of first switch pipe, source electrode connects
Ground, grid are controlled by control signal pc；
The drain electrode of reset transistor m2 meets supply voltage vdd, and grid is controlled by control signal rst；
The drain electrode of the first source follower m3 meets supply voltage vdd；
The source electrode of the drain electrode of first switch pipe m5 and second switch pipe m6 and one end phase of the first sampling holding capacitor c1
Even, grid is controlled by first switch signal s1；The other end ground connection of the first sampling holding capacitor c1；
The grid of the drain electrode of second switch pipe m6 and the second source follower m7 and one end of the second sampling holding capacitor c2
It is connected, grid is controlled by second switch signal s2；The other end ground connection of the second sampling holding capacitor c2；
The drain electrode of the second source follower m7 meets supply voltage vdd, source electrode connects the source electrode of row gate tube m8；
The drain electrode of row gate tube m8 is the outfan of overall pixel.
Wherein, signal tx, rst, pc, s1, s2 and rs are sent by the first control unit 51, by these signal controls
Make the conducting of each transistor and cut-off state thus choosing the row of pel array, and make each of selected line overall situation pixel
Second sampling holding capacitor c2 can successively export reset signal and the mixed signal of this overall pixel, and this mixed signal is to reset
Signal vreset is mixed with light sensitive diode signal vsignal, vMixing=1/2 (vreset+vsignal), and the letter that resets
Analogue signal vout=1/2 (vreset-vsignal) of overall pixel number can be characterized with the difference of mixed signal.Implement other
In example, imaging pixel can also be other structures, and the present invention is not any limitation as.Additionally, reference pixel and dark pixel are also 8t
Overall pixel,, without exposure process, analog signal output is to reading circuit after application of a voltage for it.
Reading circuit 20 reads the picture element signal of valid pixel it should be noted that reading circuit will not read redundancy picture
Element and isolation these inactive pixels signals of pixel.Specifically, as shown in figure 3, in column direction (horizontal direction in Fig. 3), being in
Totally 8 row of reference pixel the right and left isolate pixel, 8 row isolation pixels being between dark pixel and imaging pixel and redundancy picture
Plain, rightmost 4 row redundant sub-pixels and 8 row isolation pixel will not be read by reading circuit.In line direction (the vertical side in Fig. 3
To), the 4 row redundant sub-pixels going up most and 8 row isolation pixel, nethermost 8 row isolation pixels, the dark pixel of Part II and imaging
4 row isolation pixels between pel array and 4 row redundant sub-pixels will not be read by reading circuit.In this enforcement, reading circuit 20
It is set to including 6080 reading electronic circuits, 80 arranging along column direction with the 6000 of imaging pixel array row and dark pixel respectively
Row correspond configuration.As known from the above, the valid pixel finally being read by reading circuit 20 in the present embodiment be 4096 ×
6080.
Further, each reads variable gain amplifier pga and the analog-digital converter adc that electronic circuit includes connecting, its
The effect of middle variable gain amplifier pga is to be amplified pixel simulation signal, such as in the present embodiment, gain amplifier is 16
Times, the effect of analog-digital converter adc is that the analogue signal after amplifying is carried out the number that analog digital conversion makes 12 or 10
Word signal.In the present embodiment, have 6080 variable gain amplifier pga and 6080 analog-digital converter ad.Through analog digital conversion
6080 digital signals wait and being transmitted.
Transport module 30 includes n transmission channel column selector (csel), each transmission channel corresponding transmission q/
The digital signal of n valid pixel.In the present embodiment, transport module 30 includes 16 transmission channels, and preferably this 16
Individual transmission channel is divided into two submodules, and each submodule is 8 passages.Transport module is divided into multiple submodule and can mitigate biography
Defeated channels drive, the burden of transmission.8 passages of upper sub-module be csel_up1, csel_up2 ..., csel_up8, under
8 passages of portion's submodule be csel_down1, csel_down 2 ..., csel_down 8.Interface circuit 40 includes and n
N corresponding interface subcircuit of individual transmission channel.In the present embodiment, 16 interface subcircuits are also accordingly divided into 2 parts, top
Point 8 interface subcircuits be lvds_up1, lvds_up2 ..., lvds_up8,8 interface subcircuits of lower part are
Lvds_down1, lvds_down 2 ..., lvds_down 8 wherein, the data that the corresponding csel_up1 of lvds_up1 releases,
The data ... ... that the corresponding csel_up2 of lvds_up2 releases, the data that the corresponding csel_up8 of lvds_up8 releases.lvds_down
The data that 1 corresponding csel_down 1 releases, the data ... ... that the corresponding csel_down 2 of lvds_down 2 releases, lvds_
The data that the corresponding csel_down 8 of down 8 releases.Additionally, interface circuit 40 can also include memory module, pass for storage
The frame head of transmission of data and trailer information, so that the alignment of data of transmission.It is preferred that the setting letter of memory module also storage sensor
Breath, status information, clock information etc..
First control unit 51 controls whole imaging pixels to expose simultaneously, signal sampling, and rest of pixels does not need to expose
Sampling.Specifically, in the present embodiment, signal tx, rst, pc, s1, s2, rs are sent by the first control unit 51.The
One control unit 51 first control signal tx/rst of whole imaging pixels is put height simultaneously so that the transmission of whole imaging pixel
Transistor m1, reset transistor m2 open simultaneously, and now, supply voltage vdd is charged to light sensitive diode resetting, and hangs simultaneously
Floating node fd (i.e. the grid of the first transistor m3) is resetted.Afterwards, tx signal is set low by the first control unit 51 makes all
The first transistor m1 of imaging pixel closes, and light sensitive diode is initially located in exposure status.Then by the control of imaging pixel array
Signal pc processed, s1, s2 put height, and transistor m4, m5, m6 open, the equal storage reset signal of electric capacity c1 and c2.Then crystal will be switched
Pipe m6 closes, and reset signal is stored in electric capacity c2.Transmission transistor m1 is opened, completes exposure process.Crystal will be switched again
Pipe m5 opens, and is again switched off switching transistor m5 after the signal of light sensitive diode is stored in c1 electric capacity.Carry out signal afterwards
Output, switching transistor m6 remains turned-off, the reset signal vreset output of electric capacity c2 storage；Then by switching transistor m6
Open, the reset signal of storage in the light sensitive diode signal vsignal now storing in electric capacity c1 and electric capacity c2 electric capacity
Vreset is mixed so that the signal of storage is changed into=1/2 (vreset+vsignal) exporting again in electric capacity c2.And this
Difference vout=1/2 (vreset-vsignal) of output signal is the analogue signal of overall pixel twice.Thus, whole imaging
Pel array can carry out pixel exposure, signal sampling simultaneously.
On the other hand, the first control unit also chooses each row of valid pixel successively, and controls the q of selected line individual effectively
The analogue signal of pixel exports to q electronic circuit of reading circuit simultaneously.
Second control unit 52 controls reading circuit to carry out signal amplification and analog digital conversion, wherein when the son electricity of reading circuit
When driving difficulty larger pass by, the second control unit can go to drive the work of each electronic circuit by drive module, such as Fig. 1 more
In be drive module pointed by the second control module 52 arrow.In addition, the second control unit 52 is gone back controlling transmission module, is connect
The work of mouth circuit.Second control unit 52 chooses whole transmission channels of transport module simultaneously, with each transmission channel successively
Transmit q × i/n+1 to q × i/n+n valid pixel digital signal (wherein i be transmission channel numbering, i be 1～n
Positive integer), the mode of n transmission channel parallel transmission by digital data transmission to interface circuit.As front institute in the present embodiment
6080 valid pixels stating selected line are transmitted through reading to be converted to wait after digital signal, and the second control unit 52 controls biography
The data of the 1st row of valid pixel is transferred to interface circuit within the t+1 time period by defeated passage csel_up1, in t+2
In the individual time period, the data of the 2nd row of valid pixel is transferred to interface circuit ... ..., will have within the t+380 time period
The data of the 380th row of effect pixel is transferred to interface circuit；Controlling transmission passage csel_up2 will have within the t+1 time period
The data of the 381st row of effect pixel is transferred to interface circuit, by the data of valid pixel the 382nd row within the t+2 time period
It is transferred to interface circuit ... ..., within the t+380 time period, the data of the 760th row of valid pixel is transferred to interface electricity
Road；……；Control csel_up8, within the t+1 time period, the data of the 2661st row of valid pixel is transferred to interface electricity
The data of the 2662nd row of valid pixel is transferred to interface circuit ... ..., at t+375 within the t+2 time period by road
In time period, the data of the 3040th row of valid pixel is transferred to interface circuit；Controlling transmission passage csel_down 1 is in t
In+1 time period, the data of the 3040+1 row of valid pixel is transferred to interface circuit, will have within the t+2 time period
The data of the 3040+2 row of effect pixel is transferred to interface circuit ... ..., by the of valid pixel within the t+380 time period
The data of 3040+380 row is transferred to interface circuit；Csel_down2 is within the t+1 time period by the 3040+ of valid pixel
The data of 381 row is transferred to interface circuit, by the data transfer of the 3040+382 row of valid pixel within the t+2 time period
To interface circuit ... ..., within the t+375 time period, the data of the 3040+760 row of valid pixel is transferred to interface electricity
Road；……；The data of the 3040+2661 row of valid pixel is transferred to interface within the t+1 time period by csel_down8
The data of the 3040+2662 of valid pixel row is transferred to interface circuit ... ... within the t+2 time period by circuit, the
In t+380 time period, the data of the 6080th row is transferred to interface circuit.In the above process, the second control unit 52 is also controlled
Transmission channel lvds_up1 processed will be extremely outside for the data output of the 1st row of valid pixel within the t+2 time period, in t+3
By the data output of the 2nd row of valid pixel to outside in the individual time period ... ..., by effective picture within the t+381 time period
The data output of the 380th row of element is to outside；Controlling transmission passage lvds_up2 is within the t+2 time period by valid pixel
The data output of the 381st row to outside, by the 382nd of valid pixel the data output arranging to outer within the t+3 time period
Portion ... ..., by the data output of the 760th row of valid pixel to outside within the t+381 time period；……；Control lvds_
Up8 will be extremely outside for the data output of the 2661st row of valid pixel within the t+2 time period, will within the t+3 time period
The data output of the 2662nd row of valid pixel is to outside ... ..., by the 3040th of valid pixel the within the t+381 time period
The data output of row is to outside；Controlling transmission passage lvds_down 1 is within the t+2 time period by the 3040th of valid pixel the
To outside, the data output that arranges the 3040+2 of valid pixel within the t+3 time period is to outer for the data output of+1 row
Portion ... ..., by the data output of the 3040+380 row of valid pixel to outside within the t+381 time period；lvds_
Down2 will be extremely outside for the data output of the 3040+381 row of valid pixel within the t+2 time period, the t+3 time
By the data output of the 3040+382 row of valid pixel to outside in section ... ..., by effective picture within the t+381 time period
The data output of the 3040+760 row of element is to outside；……；Lvds_down8 is within the t+2 time period by valid pixel
The data output of 3040+2661 row is to number that is outside, arranging the 3040+2662 of valid pixel within the t+3 time period
According to output to outside ... ..., within the t+381 time period will valid pixel the 6080th row data transfer to outside.
In a preferred embodiment, silent frame cmos imageing sensor also includes gain module (digital gain), its
Be connected with reading circuit and transport module, for after analog-digital converter carries out analog digital conversion, data reach transport module before,
Each digital signal is carried out with numeral amplification, for example, 8 times of the multiple that numeral is amplified.
It is further preferred that the first control unit 51 reading circuit each variable gain amplifier by amplify after simulation
Signal output chooses next line valid pixel so that variable gain amplifier proceeds letter immediately to each analog-to-digital conversion module
Number amplify.
Cmos imageing sensor also includes auxiliary circuit 60, and auxiliary circuit mainly includes reference clock, by pll module group
Become；Reference voltage, is made up of band gap (bg)；Reference pulse, is made up of ramp, analog driver, wherein ramp module
Produce comparator required for reference pulse waveform, analog driver module by this reference pulse possess enough driving forces,
Each analog-to-digital conversion module can be driven；Electrification reset, is made up of por (power on reset), for sensor chip
After the upper electricity of 1.2v or when 1.2v power supply has saltus step, the second control unit is resetted.
Cmos imageing sensor also includes multiple input and output (io) interface 70, and io interface includes vddh, vssh, pixel
Vdd, pixel vss, power io, analog vdd, analog vss, digital vdd, digital vss, spi io etc.
Various io interfaces.
The sequencing contro of cmos imageing sensor is shown in Figure 4:
(1) in time period t 1, the first control unit chooses the simulation of the 1st 6080 valid pixels being about to the 1st row to believe
Number it is simultaneously transferred to 6080 variable gain amplifier pga on the right side of pel array, the second control unit controls 6080 pga will
6080 analogue signals are amplified；
(2) in time period t 2,6080 exaggerated analogue signals of the 1st row are processed into by analog-to-digital conversion module adc
6080 digital signals, and optionally pass through numeral amplification；Meanwhile, the first control unit chooses the 2nd be about to the 2nd row 6080
The analogue signal of valid pixel is simultaneously transferred to 6080 pga on right side, and pga completes 6080 valid pixel simulations of the 2nd row
The processing and amplifying of signal；
(3) in time period t 3,6080 exaggerated digital signals of the 1st row are passed to by transmission channel csel and connect
Mouth circuit lvds；Meanwhile, 6080 exaggerated analogue signals of the 2nd row are processed into 6080 digital signals by adc, and optional
Ground amplifies through numeral；Meanwhile, the first control unit chooses the 3rd to be about to 6080 valid pixel analogue signals of the 3rd row simultaneously
Pass to 6080 pga on right side, pga completes the processing and amplifying of 6080 valid pixel analogue signals of the 3rd row；
(4) in time period t 4, lvds is by 6080 exaggerated digital data transmission of the 1st row out；Meanwhile, the 2nd
6080 exaggerated digital signals of row pass to interface subcircuit lvds by transmission channel csel；Meanwhile, the 3rd row
6080 exaggerated analogue signals are processed into 6080 digital signals by adc, and optionally pass through numeral amplification；Meanwhile,
One control unit chooses the 4th 6080 valid pixel analogue signals being about to the 4th row to be simultaneously transferred to 6080 pga on right side,
Pga completes the processing and amplifying of 6080 valid pixel analogue signals of the 4th row.
By that analogy until the signal of all of valid pixel all exports.By above-mentioned sequencing contro, can be by variable increasing
Beneficial amplifier pga, analog-digital converter adc, transmission channel csel, 4 different work schedules of interface subcircuit lvds are carried out
Superposition, so that this four modules carry out the work of pipeline system, substantially increases work efficiency, increased the frame of imageing sensor
Rate.
Although the present invention is disclosed as above with preferred embodiment, so described many embodiments are illustrated only for the purposes of explanation
, it is not limited to the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention
Some changes and retouching, the protection domain that the present invention is advocated should be to be defined described in claims.
Claims (10)
1. a kind of silent frame cmos imageing sensor is it is characterised in that include:
The pel array being made up of multiple valid pixels and multiple inactive pixels, wherein each described valid pixel and inactive pixels are equal
For overall pixel；Described valid pixel is arranged as q row；
Reading circuit, it includes q reading electronic circuit, corresponds to every string configuration of described valid pixel, each described reading respectively
Go out electronic circuit to include the variable gain amplifier for amplifying the analogue signal of valid pixel and be used for the effective picture that will amplify
Plain analogue signal is converted to the analog-digital converter of digital signal；
Transport module, it includes n transmission channel, the digital signal of each transmission channel q/n valid pixel of corresponding transmission；
Interface circuit, including the n interface subcircuit corresponding with described n transmission channel, for by described transmission channel institute
The digital signal of transmission exports to outside；
First control unit, each described imaging pixel of control exposes simultaneously, signal sampling, chooses each of described valid pixel successively
OK, and control selected line q valid pixel analogue signal export simultaneously to described q read electronic circuit；
Second control unit, makes i-th transmission channel of described transport module transmit q × i/n+1 to q × i/n+n successively
When the digital signal of individual valid pixel extremely described interface circuit and each transmission, n transmission channel is parallel transmission,；And control
I-th interface subcircuit be sequentially output described q × i/n+1 to the digital signal of q × i/n+n valid pixel to outside and
When exporting every time, n interface subcircuit is parallel output；Wherein p, q, n, q/n are positive integer, i be transmission channel numbering and
It is the positive integer being less than or equal to n more than or equal to 1.
2. silent frame cmos imageing sensor according to claim 1 is it is characterised in that also include gain module, with institute
State reading circuit to be connected with described transport module, the digital signal for changing described analog-digital converter transmits to institute after amplifying
State transport module.
3. silent frame cmos imageing sensor according to claim 1 is it is characterised in that described first control unit is in institute
Analog signal output after amplifying is chosen next to each analog-to-digital conversion module by each variable gain amplifier stating reading circuit
Row valid pixel.
4. silent frame cmos imageing sensor according to claim 1 is it is characterised in that described inactive pixels include redundancy
Pixel and isolation pixel, described valid pixel includes imaging pixel array, dark pixel and the reference pixel of imaging pixel composition；Institute
State between reference pixel, dark pixel and imaging pixel array by described isolation pixel and/or redundant sub-pixels isolation；Described dark picture
Element includes being arranged as Part I and the column direction arrangement along described pel array of multirow along the line direction of described pel array
Part II for multiple row.
5. silent frame cmos imageing sensor according to claim 1 is it is characterised in that described transport module includes m
Submodule, each submodule includes n/m transmission channel, and wherein m and n/m is positive integer, and m is more than or equal to 2.
6. a kind of method for transmitting signals of silent frame cmos imageing sensor as claimed in claim 1 is it is characterised in that wrap
Include:
Step s1: make described imaging pixel array simultaneously expose and signal sampling；
Step s2: choose certain a line of described valid pixel, the analogue signal of each described valid pixel of this row is carried out simultaneously
Processing and amplifying；
Step s3: the analogue signal of the amplified each described valid pixel of this row is simultaneously converted into digital signal；
Step s4: the digital signal of each described valid pixel of this row is divided into n group, wherein every group of q/n digital signal according to
Secondary output, and during each output, n group digital signal exports simultaneously；
Repeat step s2 is to step s4 until the signal of at least this imaging pixel array all exports.
7. method for transmitting signals according to claim 6 is it is characterised in that also include before step s4 after step s3
The step that the digital signal of conversion is amplified.
8. method for transmitting signals according to claim 6 is it is characterised in that believe the simulation of current selected line in step 2
Number amplify and choose after exporting next line valid pixel and amplify its analogue signal.
9. method for transmitting signals according to claim 6 it is characterised in that described inactive pixels include redundant sub-pixels and every
From pixel, described valid pixel includes imaging pixel array, dark pixel and the reference pixel being made up of imaging pixel；Described reference
By described isolation pixel and/or redundant sub-pixels isolation between pixel, dark pixel and imaging pixel array；Described dark pixel includes
Line direction along described pel array is arranged as the Part I of multirow and is arranged as multiple row along the column direction of described pel array
Part II.
10. method for transmitting signals according to claim 6 is it is characterised in that described transport module includes m submodule,
Each submodule includes n/m transmission channel, and wherein m and n/m is positive integer, and m is more than or equal to 2.
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