CN107071324A - A kind of visual pattern processing system and its design method - Google Patents
A kind of visual pattern processing system and its design method Download PDFInfo
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- CN107071324A CN107071324A CN201710056159.9A CN201710056159A CN107071324A CN 107071324 A CN107071324 A CN 107071324A CN 201710056159 A CN201710056159 A CN 201710056159A CN 107071324 A CN107071324 A CN 107071324A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/68—Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
- H04N23/682—Vibration or motion blur correction
- H04N23/683—Vibration or motion blur correction performed by a processor, e.g. controlling the readout of an image memory
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Abstract
The invention provides a kind of visual pattern processing system, it includes processor module and programmable module integrated on piece, and the processor module is connected with the programmable module, for the programmable module is configured and with its data interaction；The programmable module is used for the reception, processing and output of view data.The visual pattern processing system of the present invention is integrated on a single chip by functions such as IMAQ, caching, processing, outputs, and integrated level is high, and communication speed is fast in piece, it is low in energy consumption, system has high speed real-time, and highest picture-taken frequency is up to 1000fps, most short process cycle 1ms.Present invention also offers a kind of design method of visual pattern processing system.
Description
Technical field
The present invention relates to machine vision hardware art, more particularly to a kind of high speed monocular vision processing system and its design side
Method.
Background technology
Machine vision is fast-developing branch of artificial intelligence.In simple terms, machine vision is exactly to use machine
Measure and judge instead of human eye.NI Vision Builder for Automated Inspection is will to be ingested target by machine vision product to be converted into image letter
Number, send special image processing system to, obtain the shape information of target subject, according to pixel distribution and brightness, color etc.
Information, is transformed into digitized signal；Picture system carries out various computings to these signals to extract clarification of objective, and then according to
The result of differentiation come control scene device action.
German Silicon Software companies released a user based on PCI-E buses can FPGA (Field
Programmable Gate Array) programming high-performance image capture card MicroEnable IV VD4-CL, the product pair
The visual processes platform answered is based on FPGA+PC frameworks.Capture card is the user's customized development for having realtime graphic pre-processing requirements, will
Camera image is come in certain frame frequency collection, and the image of input is carried out after real-time FPGA image preprocessings, passes through PCIe
Result images are transferred to calculator memory by interface again, after making for graphical Visual Applet development platforms supporting on PC
Continuous software analysis and processing.
The function of IMAQ and image preprocessing is cured to by Silicon Software visual processes platform scheme
It is automatically performed in FPGA, and follow-up image processing algorithm is realized on PC.The problem of bringing is the resolution ratio and biography when image
When defeated frequency is improved, the process bandwidth of image is dramatically increased, and Calculation bottleneck occurs in the serial process pattern of PC processing frameworks, meter
Calculate to take and greatly increase, treatment effeciency is relatively low.And this scheme visual performance integrated level is low, in FPGA image pick-up cards and
It is implemented separately on PC, communication speed is slower between PC and FPGA, information transmission is complicated.
The content of the invention
In view of the drawbacks described above of prior art, the technical problems to be solved by the invention are to provide a kind of universal high speed
Visual processes solution, be this invention provides a kind of visual pattern processing system, it includes processor integrated on piece
Module and programmable module, the processor module are connected with the programmable module, for being carried out to the programmable module
Set and with its data interaction；The programmable module is used for the reception, processing and output of view data.
Further, the programmable module includes storage control module, image processing module, image output module；Institute
Stating storage control module is used for the storage of data, reads control；Described image processing module is received from the storage control mould
The view data of block, and the view data after being processed is output to described image output module and/or the processor die
Block.
Further, the processor module is connected with the programmable module by bus mode.
Further, described image processing module includes image data format conversion module, and described image processing module will
The view data received first carries out format conversion processing by described image data format conversion module.
Further, described image data format conversion module turns RGB block, RGB including Bayer and turns gray scale module and ash
Degree turns gradient modules.
Further, the gray scale turns gradient modules using 3 end to end FIFO (First Input First
Output) as the buffer area of gradation data, and the data of each clock cycle are kept in for 8*3 register using 3 groups of long degree,
The gradient that gradient calculation obtains 8 pixels is carried out in each clock cycle.
Further, the storage control module also includes the data-interface of connection inside or external memory.
Further, the programmable module also includes camera configuration module, for decoding and preserving camera configuration letter
Breath.
Further, the programmable module also includes data transmission interface, for providing data message to external equipment.
Further, described upper integrated processor module and programmable module are serial using the Zynq of company of match SEL
SoC (System on Chip) device.
Present invention also offers a kind of design method of visual pattern processing system, it is characterised in that is handled from having
The SoC devices of device module and programmable module, the processor module be used for the programmable module is configured and and its
Data interaction；The programmable module is provided for the reception, processing and output of view data.
Further, the programmable module includes storage control module, image processing module, image output module；Institute
Stating storage control module is used for the storage of data, reads control；Described image processing module is received from the storage control mould
The view data of block, and the view data after being processed is output to described image output module and/or the processor die
Block.
Further, the processor module is connected with the programmable module by bus mode.
Further, described image processing module includes image data format conversion module, and described image processing module will
The view data received first carries out format conversion processing by described image data format conversion module.
Further, described image data format conversion module turns RGB block, RGB including Bayer and turns gray scale module and ash
Degree turns gradient modules.
Further, the gray scale turns gradient modules using 3 end to end FIFO (First Input First
Output) as the buffer area of gradation data, and the data of each clock cycle are kept in for 8*3 register using 3 groups of long degree,
The gradient that gradient calculation obtains 8 pixels is carried out in each clock cycle.
Further, the storage control module also includes the data-interface of connection inside or external memory.
Further, the programmable module also includes camera configuration module, for decoding and preserving camera configuration letter
Breath.
Further, the programmable module also includes data transmission interface, for providing data message to external equipment.
Further, the SoC devices with processor module and programmable module are using the Zynq for matching company of SEL
Serial SoC (System on Chip) device.
The invention has the advantages that：
1st, the functions such as IMAQ, caching, processing, output is integrated on a single chip, integrated level is high, communication speed in piece
It hurry up, it is low in energy consumption；
2nd, system has high speed real-time, and highest picture-taken frequency is up to 1000fps, most short process cycle 1ms；
3rd, IP kernel modularization, is advantageously integrated and calls；
4th, RGB, gray scale, three kinds of picture format inputs of gradient are supported to be used for image procossing；
5th, gray scale turns gradient image format conversion completely by hardware programmable logic realization；
6th, Bayer turns the 8 circuit-switched data parallel processings of support of RGB image format conversion.
The technique effect of the design of the present invention, concrete structure and generation is described further below with reference to accompanying drawing, with
It is fully understood from the purpose of the present invention, feature and effect.
Brief description of the drawings
Fig. 1 is the design frame chart of a preferred embodiment of the visual pattern processing system of the present invention；
In Fig. 2 in Fig. 1 DDR3 control modules general frame figure；
Fig. 3 is the flow chart of data processing figure that gray scale turns gradient modules in Fig. 1；
Fig. 4 is the design frame chart for using a kind of vision servo system of visual pattern processing system in Fig. 1；
Fig. 5 is the image preprocessing and locating effect figure of Fig. 4 vision servo system.
Embodiment
In the description of embodiments of the present invention, it is to be understood that term " on ", " under ", "front", "rear", " left side ",
The orientation of the instruction such as " right side ", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " clockwise ", " counterclockwise " or position are closed
It is to be described based on orientation shown in the drawings or position relationship, to be for only for ease of the description present invention and simplifying, rather than indicates
Or imply that the device or element of meaning must have specific orientation, with specific azimuth configuration and operation, therefore be not understood that
For limitation of the present invention.Accompanying drawing is schematic diagram or concept map, the relation between each several part thickness and width, and each several part
Between proportionate relationship etc., it is not completely the same with its actual value.
Fig. 1 is a kind of design frame chart of visual pattern processing system of the present invention, and the design is based on having ARM+FPGA framves
Match SEL (Xilinx) company Zynq series SoC of structure are as carrier, including integrated double ARM in single module
Cortex A9 processors and FPGA, pass through high bandwidth between the twoBus interconnection, so can be with extremely low
Power consumption supports data transfer.The hardware logic part set in FPGA includes：
Camera configuration module, configuration information includes resolution ratio, passage, frame per second etc.；
DDR3 control modules, connect DDR3 memories；
Image data format conversion module, turns that RGB block, RGB turn gray scale module and gray scale turns gradient including Bayer
Module；
Image algorithm processing module；
HDMI output modules, for the configuration of HDMI forms and output control；
AXI_UART interfaces, plug-in type interface, reserved self defined interface.
The system of the present embodiment supports Cameralink Full camera interfaces, and it is former to gather Bayer format by high speed camera
Beginning image sequence, realizes the DDR cachings of view data, at image preprocessing (data format conversion), image at FPGA ends successively
The functions such as reason, HDMI outputs and camera configuration.The operation principle and process of whole system include：
1st, complete to postpone matching somebody with somebody for camera at PC ends, the data that ARM ends issue PC ends are decoded, and a part is passed to
FPGA ends are used, and another part is transmitted directly to camera by AXI UART interfaces.
2nd, the data that camera configuration module is transmitted to ARM ends carry out decoding and obtain camera configuration information, and mould is controlled for DDR3
Block, image data format conversion module and HDMI output modules are used.
3rd, the configuration information in camera configuration module, such as resolution ratio, passage, frame per second, and HDMI averagely show and adopted
Sample frame period, the DDR storages of the two channel datas of camera and the two field picture of average sample are completed by DDR3 control modules
With reading control.
4th, the two paths of data to reading carries out image data format conversion respectively, and the wherein two field picture of average sample is completed
Bayer, which turns to export by the HDMI output modules being configured after rgb format conversion, to be shown；Camera image data is successively
Progress Bayer turns RGB, RGB and turns the conversion that gray scale, gray scale turn gradient, RGB, gray scale, three kinds of lattice of gradient that each step conversion is obtained
Formula view data is available for successive image algorithm processing module and used.
5th, the related image processing algorithm of image algorithm processing modules implement field of machine vision, and can be by obtained result
ARM ends are passed to, subsequent arithmetic and control or output display is run by.
Fig. 2 shows the general frame of DDR3 control modules, and DDR3 control modules realize view data in the present embodiment
The control operation such as reception, transmission, storage, reading, it includes three submodules：DDR3 memories respectively by configuration connect
Mouth solution mig_7series_v1_9 modules, ui_signal_gen modules and CamInCtrl modules.Wherein, ui_
Signal_gen modules realize that the data (second reading two is write) of four-way work simultaneously, and it is by the way of poll, and each passage is held
Go after the data volume operation of current channel single, just into the operation of next passage, execution is circulated with this.CamInCtrl moulds
Block completes the control operation of camera data read/write channel, while completing to extract the frame of camera image data, as logical to HDMI
The Read-write Catrol operation in road.The two modules collectively constitute the inner control logic of DDR3 control modules, pass through configured IP kernel
The interface that mig_7series_v1_9 is provided rapidly is set up to access and is connected with peripheral hardware DDR3SDRAM memories.
Camera shoot image be transmitted with Bayer format, but its cannot be used directly in image processing algorithm, it is necessary to
Picture format is changed, the process of form conversion constitutes the pretreatment of image, i.e. image data format conversion module, this
Bayer of the module comprising serial connection turns that RGB, RGB turn gray scale and gray scale turns three sub-function modules of gradient.
Bayer is turned RGB block and is turned Bayer format using the method (prior art will not be repeated here) of interpolation arithmetic
It is changed in rgb format, the present embodiment, sets camera to input 8 pixels in a clock cycle, Bayer turns RGB block and also existed
Interior 8 pixels of parallel processing simultaneously of same clock cycle, so as to realize 8*8bit Bayer to 8*24bit RGB form
Conversion.
RGB turns in the processing procedure of gray scale module, in order to avoid floating-point operation and division arithmetic, and for precision aspect
Consideration, using algorithm Gray=(R*76+G*151+B*28)>>8, so processing both ensure that the precision of processing in permission
In the range of, hardware process speed is accelerated again.
Gray scale turn gradient modules need and meanwhile before and after totally 3 rows data, design cycle is as shown in Figure 3.In order to from figure
As data flow restores the two dimensional surface information of image, it is used as the buffer area of gradation data using 3 end to end FIFO,
And the data of each clock cycle are kept in for 8*3 register using 3 groups of long degree, gradient calculation is carried out in each clock cycle
The gradient of 8 pixels is obtained, the result of gradient calculation is stored in two-port RAM.Thus achieve gradient calculation and reading
It is parallel, saved the space required for storage image.
HDMI output modules complete the configuration to HDMI chips by IIC interfaces, as being configured as RGB444,8bit
Data format.The Bayer of HDMI passages turn RGB block output signal be 8*32bit RGB image, by HdmiFifo by its
The RGB image for being converted into 1*32bit is exported one by one.User produces 1920*1080 output timing according to USB interface sequential,
Corresponding region will read HdmiFifo and enable, so that the input picture of camera is shown in HDMI display.
A kind of vision servo system that Fig. 4 is shown, including the visual pattern processing system in above-described embodiment, with
And interconnected camera, PC ends and head, the system can realize that IMAQ, caching, pretreatment, processing, HDMI outputs are aobvious
Show, the function such as camera configuration and encoder feedback.
By taking a specific operating process as an example, DDR3 control modules obtain image with the speed of 1000 frame per second from camera
And cached in DDR3 SDRAM；Image data format conversion module is carried out successively to the raw image data from camera
Bayer turns RGB, RGB and turns the conversion that gray scale, gray scale turn gradient form；Image algorithm processing module implants the positioning of circle fitting
Algorithm is simultaneously positioned with the speed of 1000 frame per second to image object；HDMI output modules are with the speed of 60 frame per second by image
The display for being sent to PC ends is shown；The camera configuration information that camera configuration module is sent to PC ends carries out being decoded for other moulds
Block is used；The reserved self defined interface of visual pattern processing system in above-described embodiment, is arranged to encoder feedback herein
Module, the head state for obtaining the current image shot moment from head encoder.
Data transfer, three-dimensional localization and cradle head control function are realized in the vision servo system of the present embodiment in ARM ends.
On the one hand TCP data segment obtains positioning result and by serial ports framing result and the three-dimensional subsequently calculated from FPGA
Positioning result is sent to PC ends software interface, and on the other hand obtaining camera configuration information from PC ends forwards it by AXI UART
Give Cameralink camera configurations port；Three-dimensional localization part is demarcated to the parameter of system in advance, is handed over using based on ray
Framing result is converted into world coordinates result by the three-dimensional reconstruction algorithm of remittance method；The three-dimensional of cradle head control part combining target
The result of coordinate and head encoder feedback, calculates the cradle head control instruction that can be maintained target near picture centre,
The convolution and the pitch drive that are sent respectively to head will be instructed by serial ports.So as to the display interface at PC ends realize to
The displaying of track effect, and image and framing result can also together be included on interface.
Fig. 5 shows the image preprocessing and locating effect figure of the vision servo system of the present embodiment, from left to right successively
For original image, gradient image and circle fitting locating effect figure.
Preferred embodiment of the invention described in detail above.It should be appreciated that one of ordinary skill in the art without
Need creative work just can make many modifications and variations according to the design of the present invention.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical scheme, all should be in the protection domain being defined in the patent claims.
Claims (11)
1. a kind of visual pattern processing system, it is characterised in that including processor module and programmable module integrated on piece, institute
Processor module is stated to be connected with the programmable module, for the programmable module is configured and with its data interaction；
The programmable module is used for the reception, processing and output of view data.
2. visual pattern processing system as claimed in claim 1, it is characterised in that the programmable module includes storage and controlled
Module, image processing module, image output module；The storage control module is used for the storage of data, reads control；The figure
As view data of the processing module reception from the storage control module, and the view data after being processed is output to institute
State image output module and/or the processor module.
3. visual pattern processing system as claimed in claim 1, it is characterised in that the processor module may be programmed with described
Module is connected by bus mode.
4. visual pattern processing system as claimed in claim 1, it is characterised in that described image processing module includes picture number
According to format conversion module, described image processing module is by the view data received first by described image data format conversion module
Carry out format conversion processing.
5. visual pattern processing system as claimed in claim 4, it is characterised in that described image data format conversion module bag
Include Bayer and turn that RGB block, RGB turn gray scale module and gray scale turns gradient modules.
6. visual pattern processing system as claimed in claim 5, it is characterised in that the gray scale turns gradient modules using 3
End to end FIFO and keeps in each clock cycle using 3 groups of long degree as the buffer area of gradation data for 8*3 register
Data, carry out gradient calculation in each clock cycle and obtain the gradients of 8 pixels.
7. visual pattern processing system as claimed in claim 1, it is characterised in that the storage control module also includes connection
The data-interface of internal or external memory.
8. visual pattern processing system as claimed in claim 1, it is characterised in that the programmable module is also matched somebody with somebody including camera
Module is put, for decoding and preserving camera configuration information.
9. visual pattern processing system as claimed in claim 1, it is characterised in that the programmable module also includes data and passed
Defeated interface, for providing data message to external equipment.
10. visual pattern processing system as claimed in claim 1, it is characterised in that described upper integrated processor module
With Zynq series SoC device of the programmable module using company of match SEL.
11. a kind of design method of visual pattern processing system, it is characterised in that from processor module and programmable mould
The SOC devices of block, the processor module be used for the programmable module is configured and with its data interaction；Can by described in
Programming module is provided for the reception, processing and output of view data.
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| CN110730304A (en) * | 2019-10-25 | 2020-01-24 | 北京凯视佳光电设备有限公司 | Intelligent camera for accelerating image acquisition and display |
| CN110933333A (en) * | 2019-12-06 | 2020-03-27 | 河海大学常州校区 | Image acquisition, storage and display system based on FPGA |
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| CN111145133A (en) * | 2019-12-05 | 2020-05-12 | 南京理工大学 | ZYNQ-based infrared and visible light co-optical axis image fusion system and method |
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| CN114827625A (en) * | 2022-04-27 | 2022-07-29 | 武汉大学 | High-speed image cloud transmission method based on gray scale image compression algorithm |
| CN115174763A (en) * | 2022-07-05 | 2022-10-11 | 重庆邮电大学 | Image real-time display system based on ZYNQ |
| CN116456093A (en) * | 2023-03-31 | 2023-07-18 | 之江实验室 | Zynq-based image frame rate controllable simulator and method |
| CN116456093B (en) * | 2023-03-31 | 2024-02-09 | 之江实验室 | Zynq-based image frame rate controllable simulator and method |
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