CN104935895B - A kind of video acquisition processing circuit for medical endoscope - Google Patents
A kind of video acquisition processing circuit for medical endoscope Download PDFInfo
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- CN104935895B CN104935895B CN201510374453.5A CN201510374453A CN104935895B CN 104935895 B CN104935895 B CN 104935895B CN 201510374453 A CN201510374453 A CN 201510374453A CN 104935895 B CN104935895 B CN 104935895B
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Abstract
The present invention relates to a kind of video acquisition processing circuits for medical endoscope, including video capture processor, picture processing chip, signal conversion chip and image enhancement chip；Video data after acquisition is sent to picture processing chip and is handled by the video capture processor；The signal conversion chip includes the first signal conversion chip and second signal conversion chip；The first signal conversion chip is used to bt1120 signals being converted to lvds signals；The second signal conversion chip is used to lvds signals being converted to bt1120 signals；By treated, picture signal is sent to the first signal conversion chip to described image processing chip, and is sent to second signal conversion chip by the first signal conversion chip；The second signal conversion chip is sent to image enhancement chip after converting signal.
Description
Technical field
The present invention relates to a kind of video capture circuit, especially a kind of video acquisition for for medical endoscope is handled
Circuit.
Background technology
Endoscope is a kind of common medical instrument, is made of bendable portion, light source and one group of camera lens.Day through human body
The small notch that right duct or underwent operative are done enters in human body, and endoscope is imported to when use the organ of preliminary examination, can be direct
Pry through the variation in relation to position.
Wherein, the quality of picture quality directly affects the using effect of endoscope.It is existing generally using being peeped in electronics
Mirror is observed.Common fujinon electronic video endoscope is using the minimum electronic imaging element-CCD (charge coupling device) of size, by institute
The intracavitary object to be observed is imaged onto by small objective lens optical system on CCD, then by leading as fibre bundle will receive
Picture signal be sent on image processing system, finally output treated image on a monitor, observes and is diagnosed for doctor.
The defect that power consumption is excessively high however, existing CCD chip still has, image quality is not clear enough.
Meanwhile it is existing generally observed using fujinon electronic video endoscope, and the image after observation is sent to external connection
Processing system carry out image procossing.However, when due to carrying out Image Acquisition in human body, it can be due to the various originals of inside of human body
Because, and cause noise jamming occur, brightness can not automatically adjust or image is caused aberration occur due to the color of light, so
Cause in the image procossing in later stage, it is difficult to restore true image, doctor is made to be difficult to recognize in observation.
Invention content
The invention reside in the shortcomings that overcoming the prior art with it is insufficient, provide a kind of high definition, low-power consumption, low-light (level) for curing
With the video acquisition processing circuit of endoscope.
The invention is realized by the following technical scheme：A kind of video acquisition processing circuit for medical endoscope, including
Video capture processor, picture processing chip, signal conversion chip and image enhancement chip；
Video data after acquisition is sent to picture processing chip and is handled by the video capture processor；
The signal conversion chip includes the first signal conversion chip and second signal conversion chip；First signal turns
Chip is changed for bt1120 signals to be converted to lvds signals；The second signal conversion chip is for being converted to lvds signals
Bt1120 signals；
Described image processing chip will treated picture signal is sent to the first signal conversion chip, and first believed by this
Number conversion chip is sent to second signal conversion chip；The second signal conversion chip is sent to image increasing after converting signal
Strong chip.
Compared with the prior art, the present invention is in camera lens part by increasing by a picture processing chip, to the image of acquisition into
Row processing, increases by an image enhancement chip on host backstage, carries out level image enhancing, keeps the image finally exported more clear
It is clear.
First, it is divided into multiple function modules in picture processing chip, is coordinated respectively and independently by each function module
Work, can realize low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile further at the image
A white balance permanent circuit is set in reason device, for the white balance parameter to be fixed, without carrying out white balance at work
Adjusting, to prevent aberration interference the phenomenon that.
Then, it is also divided into multiple function modules in image enhancement chip, is assisted respectively and independently by each function module
Work is adjusted, can realize the enhancing processing to image.Meanwhile image border enhancing is further set in the image intensifier
Circuit, to enhance the clarity of image border.
In addition, in order to improve the stability of signal transmission, the present invention by the way that bt1120 signals are first converted to lvds signals,
To the transmission stablized, and there is low noise ability.Then, it is being bt1120 signals by lvds signals revivifications, to ensure that
The quality of the picture of follow-up play.
As a further improvement on the present invention, include inside the video capture processor：Controller, driver, photoreceptor,
Sampler and follower；
--- the controller is used to receive external trigger signal, sends trigger signal to driver；
--- the driver is used to receive the trigger signal of controller, and photoreceptor is driven to work；
--- the photoreceptor is used to receive extraneous optical signal, and the optical signal is converted to electric signal；
--- the sampler is used to be sampled processing, and the electric signal that will have been handled to the electric signal of photoreceptor
It is sent to follower；
--- the follower is used to the electric signal being converted to digital signal, and carries out output picture processing chip；
Described image processing chip includes：Data sink, master controller, image processor, data logger；
--- the data sink is used to receive external image data；
--- the master controller is used to receive external trigger signal, and accordingly control the data sink,
The working condition of image processor and data logger；
--- described image processor is used to handle image；Described image processor is solid including a white balance
Determine circuit, is used to carry out the fixed adjustment of white balance according to preset parameter；
--- the data logger is used for that image data to export by treated；
The first signal conversion chip includes：Controller, data reader, signal format converter, serializer, data
Follower；
--- the controller is used to receive external trigger signal, and controls data reader, signal format conversion
The work of device, serializer and data logger；
--- the data reader is used to receive external bt1120 transmission signals, and is sent to signal format and turns
Parallel operation；
--- the signal format converter is used to be converted to bt1120 vision signals the vision signal of lvds, and
It is sent to serializer；
--- the serializer is used to convert parallel data into serial data, and is sent to data logger；
--- the data logger, for exporting lvds signal datas to second signal conversion chip；
The second signal conversion chip includes：Controller, data reader, signal format converter, deserializer, data
Follower；
--- the controller is used to receive external trigger signal, and controls data reader, signal format conversion
The work of device, deserializer and data logger；
--- the data reader is used for the lvds video transfer signals of the first signal conversion chip, and is sent to
Signal format converter；
--- the signal format converter is used to be converted to lvds vision signals the vision signal of bt1120, and
It is sent to deserializer；
--- the deserializer is used to convert serial data into parallel data, and is sent to data logger；
--- the data logger, for bt1120 video signal datas to be exported；
Described image enhances chip：Data sink, controller, static memory, image intensifier, data output
Device and clock generator；
--- the data sink is used to receive viewdata signal, and is sent to the image intensifier；
--- the controller is used to receive outer triggering signal, and accordingly control data sink, image enhancement its
With the working condition of data logger；
--- the static memory is used to store the driving data of image intensifier, to drive the image intensifier
Work；
--- described image booster a comprising image border enhances circuit；Described image edge enhancing circuit is used for
Enhance the clarity of image border；
--- the data logger is used to receive image intensifier treated image data, and it is defeated to carry out data
Go out；
--- the clock generator is used to generate clock signal for image enhancement chip.
As a further improvement on the present invention, the video capture processor further includes a frequency multiplier, and being used for will be external defeated
The frequency of the trigger signal entered carries out doubling processing, retransmits to controller；
Described image processing chip further includes a frequency multiplier, is used to increase the frequency of externally input trigger signal
It handles, is retransmited to master controller again；
The first signal conversion chip further includes a phase-locked loop, is connected respectively with signal format converter and serializer
It connects, is used for unified integration clock signal；
The second signal conversion chip further includes a phase-locked loop, is connected respectively with signal format converter and serializer
It connects, is used for unified integration clock signal；
It further includes a de-noising processor that described image, which enhances chip,；Picture number that the data sink receives it is believed that
Number, it is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
As a further improvement on the present invention, the image processor in described image processing chip further includes an exposure gain
Circuit, for increasing exposure gain size；
The first signal conversion chip further includes a clock data restorer, is connect with data reader, for from
Restore data in the distortion of transmission channel and noise；
The second signal conversion chip further includes a clock data restorer, is connect with data reader, for from
Restore data in the distortion of transmission channel and noise；
It further includes a dynamic memory that described image, which enhances chip,；The de-noising processor treated image data, first
It is sent to dynamic memory to be stored, then is forwarded to image intensifier.
As a further improvement on the present invention, described image processor further includes an optical detection circuit and flash detection electricity
Road is used for brightness and the flashing state of detection image, and result of detection is sent to exposure gain circuit；
It further includes the adaptive proofreading equipment of a pixel that described image, which enhances chip,；Described image booster first will treated figure
As data are sent to the adaptive proofreading equipment of the pixel, pixel is carried out by the adaptive proofreading equipment of the pixel and adapts to check and correction, is retransmited
To data logger.
As a further improvement on the present invention, it is equipped with outside the video capture processor：Electricity for receiving supply voltage
Source port, the video signal port for exporting vision signal, the row field signal port for exporting row field signal, for receiving
The reference signal port of reference voltage electricity frequency and a clock signal port for receiving external timing signal；
It is equipped with outside described image processing chip：For receiving the power port of supply voltage, for receiving picture signal
Receiver port, the video signal port for exporting vision signal, the row field signal port for exporting row field signal,
For receiving the clock signal port of external timing signal, the data receiver port for receiving storage data and one is used to receive
The PORT COM of external communication order；
It is equipped with outside the first signal conversion chip：The center processing chip exterior is equipped with：For receiving power supply electricity
The power port of pressure, the receiver port for receiving bt1120 vision signals, the video for exporting lvds vision signals
Signal port and row field signal port for exporting row field signal；
It is equipped with outside the second signal conversion chip：The center processing chip exterior is equipped with：It is supplied for receiving
The power port of piezoelectric voltage, the receiver port for receiving lvds vision signals and for exporting bt1120 vision signals
Video signal port；
Described image enhancing chip exterior is equipped with：For receiving the power port of supply voltage, for receiving picture signal
Receiver port, the video signal port for exporting vision signal, the row field signal port for exporting row field signal,
Clock signal port for receiving external timing signal and the data receiver port for receiving storage data.
As a further improvement on the present invention, the power port of the video capture processor is circumscribed with a filter for voltage stabilizing
Wave circuit；The filter circuit includes an inductance and at least one capacitance；Described inductance one end is connect with external power supply, another
End respectively with each capacitance connection, the other end of each capacitance and ground connection；One end of the inductance and capacitance connection is accessed
Power port；
The power port of described image processing chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes
One inductance and at least one capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, institute
State the other end and the ground connection of each capacitance；Power port is accessed in one end of the inductance and capacitance connection.
As a further improvement on the present invention, the row field signal port of the video capture processor is circumscribed with one for providing
The resistance of signal strength.
As a further improvement on the present invention, the reference signal port of the video capture processor is circumscribed with as voltage electricity
The capacitance of frequency reference data.
As a further improvement on the present invention, the external clock circuit in the clock signal port of the video capture processor,
It includes that a clock shakes chip；The shake power end of chip of the clock is connect by a filter circuit with power supply, which shakes the defeated of chip
Outlet is connect by a debug circuit with the clock signal port；The filter circuit includes by an inductance and capacitance series connection group
At one end of the inductance is connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance；The clock shakes core
Between the power end and connection and inductance and capacitance of piece；The debug circuit is made of resistance and capacitance；The electricity of the debug circuit
One end of resistance and the output end of Zhong Zhen connect, the other end and capacitance connection, and the other end ground connection of the capacitance；The clock signal
Port is connected between the resistance and capacitance；
The external clock circuit in described image processing chip clock signal port a comprising clock shakes chip；The clock shakes
The power end of chip is connect by a filter circuit with power supply, the clock shake chip output end by a debug circuit with it is described when
Clock signal port connects；The filter circuit includes being composed in series by an inductance and capacitance, and one end and the power supply of the inductance connect
It connects, the other end and capacitance connection, and the other end ground connection of the capacitance；The clock shake chip power end with connect with inductance and electricity
Between appearance；The debug circuit is made of resistance and capacitance；One end of the resistance of the debug circuit and the output end of Zhong Zhen connect,
The other end and capacitance connection, and the other end ground connection of the capacitance；The clock signal port is connected between the resistance and capacitance；
Described image enhances the external clock circuit in clock signal port of chip comprising a clock shakes chip；The clock
The power end of chip of shaking is connect by a filter circuit with power supply, which shakes the output end of chip and the clock signal port connects
It connects；The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and electricity
Hold connection, and the other end ground connection of the capacitance.
In order to better understand and implement, the invention will now be described in detail with reference to the accompanying drawings.
Description of the drawings
Fig. 1 is the chip connection diagram of the present invention.
Fig. 2 is the internal module connection diagram of video capture processor.
Fig. 3 is the outside port connection circuit diagram of video capture processor.
Fig. 4 is the circuit diagram of the power unit connection of video capture processor.
The voltage of the 2.7V of Fig. 5 video capture processors accesses circuit diagram.
Fig. 6 is the voltage access circuit diagram of the 1.8V of video capture processor.
Fig. 7 is the voltage access circuit diagram of the 1.2V of video capture processor.
Fig. 8 is the partial enlarged view of the row field signal of video capture processor.
Fig. 9 is the partial enlarged view of the reference signal port of video capture processor.
Figure 10 is the circuit diagram of the clock circuit of video capture processor.
Figure 11 is the circuit diagram of the configuration circuit of video capture processor.
Figure 12 is the internal module connection diagram of picture processing chip.
Figure 13 is the circuit module schematic diagram of the image processor of picture processing chip.
Figure 14 is the voltage segment circuit diagram of picture processing chip.
Figure 15 is the outside port circuit diagram of picture processing chip.
Figure 16 is the circuit diagram of the filter circuit of the 3.3V voltages of picture processing chip.
Figure 17 is the circuit diagram of the filter circuit of the 1.8V voltages of picture processing chip.
Figure 18 is the circuit diagram of the filter circuit of the 1.2V voltages of picture processing chip.
Figure 19 is the partial enlarged view of the receiver port of picture processing chip.
Figure 20 is the partial enlarged view of the video signal port of picture processing chip.
Figure 21 is the partial enlarged view of the row field signal port of picture processing chip.
Figure 22 is the schematic diagram of the clock circuit of picture processing chip.
Figure 23 is the schematic diagram of the storage circuit of picture processing chip.
Figure 24 is the partial enlarged view of the PORT COM of picture processing chip.
Figure 25 is the internal components connection diagram of the first signal conversion chip.
Figure 26 is the internal module connection diagram of second signal conversion chip.
Figure 27 is the outside port connection diagram of the first signal conversion chip.
Figure 28 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 29 is the partial enlarged view of the receiver port of the first signal conversion chip.
Figure 30 is the partial enlarged view of the video signal port of the first signal conversion chip.
Figure 31 is the partial enlarged view of the row field signal port of the first signal conversion chip.
Figure 32 is the external connection circuit diagram of second signal conversion chip.
Figure 33 is the partial enlarged view of the receiver port of second signal conversion chip.
Figure 34 is the partial enlarged view of the video signal port of second signal conversion chip.
Figure 35 is the partial enlarged view of the row field signal port of second signal conversion chip.
Figure 36 is the internal module connection diagram of image enhancement chip.
Figure 37 is first part's external connection circuit diagram of image enhancement chip.
Figure 38 is the second part external connection circuit diagram of image enhancement chip.
Figure 39 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltages of image enhancement chip.
Figure 40 is that the 3.3V of image enhancement chip is converted to the power-switching circuit figure of 1.8V.
Figure 41 is that the 3.3V of image enhancement chip is converted to the power-switching circuit figure of 1.2V.
Figure 42 is the partial enlarged view of the receiver port of image enhancement chip.
Figure 43 a are the partial enlarged views of the video signal port first part of image enhancement chip.
Figure 43 b are the partial enlarged views of the video signal port second part of image enhancement chip.
Figure 44 is the circuit diagram of the clock circuit of image enhancement chip.
Figure 45 is the partial enlarged view of the row field signal port of image enhancement chip.
Specific implementation mode
Referring to Fig. 1, it is the chip connection diagram of invention.The present invention provides a kind of regarding for medical endoscope
Frequency acquisition process circuit, including video capture processor 10, picture processing chip 20, signal conversion chip 30 and image enhancement chip
40。
Video data after acquisition is sent to picture processing chip 20 and is handled by the video capture processor 10；It is described
Signal conversion chip 30 includes the first signal conversion chip 31 and second signal conversion chip 32；
The first signal conversion chip 31 is used to bt1120 signals being converted to lvds signals；The second signal conversion
Chip 32 is used to lvds signals being converted to bt1120 signals；
Described image processing chip 20 will treated picture signal is sent to the first signal conversion chip 31, and by this
One signal conversion chip 31 is sent to second signal conversion chip 32；The second signal conversion chip 32 is sent out after converting signal
It send to image enhancement chip 40.
Referring to Fig. 2, it is the internal module connection diagram of video capture processor.Inside the video capture processor 10
Including：Controller 11, driver 12, photoreceptor 13, sampler 14, follower 15 and frequency multiplier 16；
The controller 11 is used to receive external trigger signal, sends trigger signal to driver；
The driver 12, is used to receive the trigger signal of controller, and photoreceptor is driven to work；
The photoreceptor 13 is used to receive extraneous optical signal, and the optical signal is converted to electric signal；
The sampler 14 is used to be sampled processing to the electric signal of photoreceptor, and the electric signal handled is sent out
It send to follower；
The follower 15 is used to the electric signal being converted to digital signal, and is exported.
The frequency multiplier 16 is used to carry out the frequency of externally input trigger signal to double processing, retransmit to control
Device processed.Further, for convenience in the requirement of the frequency of use of video capture processor, realize that the adjusting of frequency is put by frequency multiplier
Greatly.
It is the outside port circuit diagram of video capture processor please refer to Fig. 3.In addition to adapting to the video acquisition
The application of chip is equipped with outside the video capture processor：For the power port 101 of receiving voltage, for exporting video
The video signal port 102 of signal, the row field signal port 103 for exporting row field signal, for receive reference voltage electricity frequency
Reference signal port 104, the clock signal port 105 for receiving external timing signal and for receiving external operating mode
The communication command port 106 of order.
It is the circuit diagram of the power unit of video capture processor please refer to Fig. 4.Specifically, video capture processor
In power unit use three kinds of voltages, respectively 2.7V, 1.8V and 1.2V simultaneously.
It is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor please refer to Fig. 5-7.Specifically,
The input port 101 of three kinds of voltage of video capture processor is all circumscribed with a filter circuit for voltage stabilizing；The filter circuit
Including an inductance and at least one capacitance；Described inductance one end is connect with external power supply, and the other end connects with each capacitance respectively
It connects, the other end of each capacitance and ground connection；Power port is accessed in one end of the inductance and capacitance connection.Wherein, 2.7V
Voltage access circuit with 1.8V includes four capacitances, and the voltage access circuit of 1.2V includes three capacitances, to filter different frequencies
The interference signal of rate.
Referring to Fig. 8, it is the interface enlarged drawing of row field signal.Further, the row field signal port 103 is circumscribed with one
Resistance for providing signal strength.By the row field signal, frequency and sequence for controlling video output.Such as：It can be with
Vision signal display frequency and display order on the screen is controlled, can be the often row output under upper, can also be from a left side
To right output.
Referring to Fig. 9, its partial enlarged view for the reference signal port of video capture processor.Further, the reference
Signal port 104 is circumscribed with the capacitance as voltage electricity frequency reference data.In the present embodiment, the reference signal port has 7
It is a, the capacitance of each external 1uF in port.
Referring to Fig. 10, its circuit diagram for the clock circuit of video capture processor.The clock signal port 105 is external
One clock circuit a comprising clock shakes chip；The shake power end of chip of the clock is connect by a filter circuit with power supply, the clock
The output end of chip of shaking is connect by a debug circuit with the clock signal port；The filter circuit include by an inductance and
Capacitance is composed in series, and one end of the inductance is connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance；
The clock shake chip power end and connection and inductance and capacitance between；The debug circuit is made of resistance and capacitance；The tune
The output end of one end and Zhong Zhen for trying the resistance of circuit connects, the other end and capacitance connection, and the other end ground connection of the capacitance；Institute
Clock signal port is stated to be connected between the resistance and capacitance.
1 is please referred to Fig.1, is the circuit diagram of the configuration circuit of video capture processor.Further, the communication command port
106, it is circumscribed with an operating mode configuration circuit；The configuration circuit is composed in series by two resistance, the communication command end
Mouth is connected between two resistance.
2 are please referred to Fig.1, is the internal module connection diagram of picture processing chip.Described image processing chip 20 is wrapped
It includes：Data sink 21, master controller 22, image processor 23, data logger 24.
The data sink 21 is used to receive external image data；
The master controller 22 is used to receive external trigger signal, and accordingly controls the data sink, figure
As the working condition of processor and data logger；
Described image processor 23 is used to handle image.
The data logger 24, is used for that image data to export by treated.
Further, the video capture processor further includes a frequency multiplier 25, is used for externally input trigger signal
Frequency carries out doubling processing, retransmits to master controller 22.
3 are please referred to Fig.1, is the circuit module schematic diagram of the image processor of picture processing chip.Specifically, the figure
As processor 23 includes a Lens Shading Compensation circuit 231, optical detection circuit 232, flash detection circuit 233, exposure gain
Circuit 234 and white balance permanent circuit 235.
The Lens Shading Compensation circuit 231 is used to the shade that camera lens generates compensating processing.
The optical detection circuit 232 and flash detection circuit 233 are used for brightness and the flashing state of detection image,
And result of detection is sent to exposure gain circuit.
The exposure gain circuit 234, for increasing exposure gain size.
The white balance permanent circuit 235 is used to carry out the fixed adjustment of white balance according to preset parameter.
Please refer to Figure 14 and Figure 15, be respectively the video capture processor of picture processing chip voltage segment and its
His outside port circuit diagram.In addition, in order in order to adapt to the application of the video capture processor, further in the video acquisition core
It is equipped with outside piece：For receiving the power port 201 of supply voltage, the receiver port 202 for receiving picture signal, using
In the video signal port 203 of output vision signal, the row field signal port 204 for exporting row field signal, for outside receiving
The clock signal port 205 of portion's clock signal is used to receive outside for receiving the data receiver port 206 and one of storage data
The PORT COM 207 of communication command.
6-18 is please referred to Fig.1, the power supply for being respectively picture processing chip is the circuit diagram of 3.3V, 1.8V and 1.2V.Into
One step, the power port 201 are circumscribed with a filter circuit for voltage stabilizing；The filter circuit is including an inductance and at least
One capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, each capacitance it is another
One end and ground connection；Power port is accessed in one end of the inductance and capacitance connection.Specifically, the video capture processor of the present invention
External voltage includes：Tri- kinds of 3.3V, 1.8V and 1.2V.Wherein, 3.3V voltages access circuit includes 2 capacitances, and 1.8V voltages connect
It includes 5 capacitances to enter circuit, and the voltage access circuit of 1.2V includes 6 capacitances, to filter the interference signal of different frequency respectively.
9 are please referred to Fig.1, is the partial enlarged view of the receiver port of picture processing chip.The signal receiving end
Mouth 202 includes 8 pins, for receiving external video signal.
Figure 20 is please referred to, is the partial enlarged view of the video signal port of picture processing chip.The vision signal end
Mouth 203 includes the vision signal of two groups of different-formats, carries out doubleway output, is played and recorded in real time respectively to facilitate.
Figure 21 is please referred to, is the partial enlarged view of the row field signal port of picture processing chip.The row field signal end
Frequencies and sequence of the mouth 204 for controlling video output.Such as：The display frequency of vision signal on the screen can be controlled and shown
Show sequence, can be the often row output under upper, can also be to export from left to right.
Figure 22 is please referred to, is the schematic diagram of the clock circuit of picture processing chip.The clock signal port 205 is external
One clock circuit a comprising clock shakes chip；The shake power end of chip of the clock is connect by a filter circuit with power supply, the clock
The output end of chip of shaking is connect by a debug circuit with the clock signal port；The filter circuit include by an inductance and
Capacitance is composed in series, and one end of the inductance is connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance；
The clock shake chip power end and connection and inductance and capacitance between；The debug circuit is made of resistance and capacitance；The tune
The output end of one end and Zhong Zhen for trying the resistance of circuit connects, the other end and capacitance connection, and the other end ground connection of the capacitance；Institute
Clock signal port is stated to be connected between the resistance and capacitance.
Figure 23 is please referred to, is the schematic diagram of the storage circuit of picture processing chip.Further, the data receiver port
206 are circumscribed with a memory circuit comprising a memory, be connected to the memory voltage port filter circuit, and
It is connected to the resistance of the output port of the memory.
Figure 24 is please referred to, is the partial enlarged view of the PORT COM of picture processing chip.The PORT COM 207 is used for
It receives the external trigger command transmitted, to trigger the picture processing chip work.
Figure 25 is please referred to, is the internal components connection diagram of the first signal conversion chip.The first signal conversion
Chip 31 includes：Controller 311, data reader 312, signal format converter 313, serializer 314, data logger 315,
Phase-locked loop 316 and clock data restorer 317；
The controller 311 is used to receive external trigger signal, and controls data reader 312, signal format turn
The work of parallel operation 313, serializer 314 and data logger 315；
The data reader 312 is used to receive external bt1120 transmission signals, and is sent to signal format conversion
Device；
The signal format converter 313 is used to be converted to bt1120 vision signals the vision signal of lvds, concurrently
It send to serializer；
The serializer 314 is used to convert parallel data into serial data, and is sent to data logger；
The data logger 315, for exporting lvds signal datas to second signal conversion chip.
The phase-locked loop 316, connect with signal format converter and serializer respectively, believes for unified integration clock pulse
Number.
The clock data restorer 317, connect with data reader, for from the distortion and noise of transmission channel
Restore data.
Figure 26 is please referred to, is the internal module connection diagram of second signal conversion chip.The second signal conversion
Chip 32 includes：Controller 321, data reader 322, signal format converter 323, deserializer 324, data logger 325,
Phase-locked loop 326 and clock data restorer 327；
The controller 321 is used to receive external trigger signal, and controls data reader 322, signal format turn
The work of parallel operation 323, deserializer 324 and data logger 325；
The data reader 322, is used for the lvds video transfer signals of the first signal conversion chip, and is sent to letter
Number format converter；
The signal format converter 323 is used to be converted to lvds vision signals the vision signal of bt1120, concurrently
It send to deserializer 324；
The deserializer 324 is used to convert serial data into parallel data, and is sent to data logger；
The data logger 325, for exporting bt1120 video signal datas.
The phase-locked loop 326, connect with signal format converter and deserializer respectively, believes for unified integration clock pulse
Number.
The clock data restorer 327 is connect with data reader 222, for from transmission channel distortion and make an uproar
Restore data in sound.
Figure 27 is please referred to, is the outside port connection diagram of the first signal conversion chip.The first signal conversion
Chip exterior is equipped with：The center processing chip exterior is equipped with：For receiving the power port 3101 of supply voltage, for receiving
It the receiver port 3102 of bt1120 vision signals, the video signal port 3103 for exporting lvds vision signals and is used for
Export the row field signal port 3104 of row field signal.
It is the close-up schematic view of the power port of the first signal conversion chip please refer to Figure 28.The electricity
The capacitance for filtering alternating current is circumscribed at source port 3101.
Figure 29 is please referred to, is the partial enlarged view of the receiver port of the first signal conversion chip.The signal connects
Receiving end mouth 3102 is connect with the data reader 31；Specifically, the receiver port includes 20 pins, it is used for
Receive the vision signal of external bt1120.
Figure 30 is please referred to, is the partial enlarged view of the video signal port of the first signal conversion chip.The video letter
Number port 3103 includes 4 output pins, and for exporting lvds vision signals, and the video signal port is exported with the data
Device connects.
Figure 31 is please referred to, is the partial enlarged view of the row field signal port of the first signal conversion chip.The row field letter
Number port 3104 includes a line signal output pin and a field signal output pin；The row field signal port 3104 is for controlling
The frequency and sequence of video output processed.Such as：The display frequency and display order of vision signal on the screen can be controlled, it can be with
It is the often row output under upper, can also be to export from left to right.
Figure 32 is please referred to, is the external connection circuit diagram of second signal conversion chip.The second signal conversion
Chip exterior is equipped with：For receiving the receiver port 3201 of lvds vision signals, for exporting bt1120 vision signals
Video signal port 3202 and row field signal port 3203.
Figure 33 is please referred to, is the partial enlarged view of the receiver port of second signal conversion chip.The signal connects
Receiving end mouth 3201 is connect with the data reader 321；Specifically, the receiver port includes 4 pins, it is used for
Receive the lvds vision signals of the first signal conversion chip output.
Figure 34 is please referred to, is the partial enlarged view of the video signal port of second signal conversion chip.The video letter
Number port 3202 includes 20 output pins, for exporting bt1120 vision signals, and the video signal port and the data
Follower connects.
Figure 35 is please referred to, is the partial enlarged view of the row field signal port of second signal conversion chip.The row field letter
Number port 3203 includes a line signal output pin and a field signal output pin；The row field signal port 3104 is for controlling
The frequency and sequence of video output processed.Such as：The display frequency and display order of vision signal on the screen can be controlled, it can be with
It is the often row output under upper, can also be to export from left to right.
Figure 36 is please referred to, is the internal module connection diagram of image enhancement chip.Described image enhances chip 40 and wraps
It includes：The adaptive proofreading equipment 45 of data sink 41, de-noising processor 42, dynamic memory 43, image intensifier 44, pixel, number
Occur according to follower 46, static memory 47, controller 48, vision signal multiplier 49, storage signal multiplier 410, clock
Device 411.
The data sink 41 is used to receive viewdata signal, and is sent to de-noising processor 42；
The viewdata signal that the data sink 41 receives is sent to de-noising processor 42 and carries out noise reduction process,
It is forwarded to dynamic memory 43 again.
The dynamic memory 43 is after receiving de-noising processor 42 treated image data, then is forwarded to image increasing
Strong device 44.
Described image booster 44 a comprising image border enhances circuit；Described image edge enhancing circuit is for increasing
The clarity of strong image border.Further, first by treated, image data is sent to the pixel certainly to described image booster
Proofreading equipment 45 is adapted to, carrying out pixel by the adaptive proofreading equipment 45 of the pixel adapts to check and correction, retransmits to data logger 46.
The data logger 46 is used to receive image intensifier treated image data, and carries out data output；
The static memory 47 is used to store the driving data of image intensifier, to drive the image intensifier
Work；
The controller 48, is used to receive outer triggering signal, and accordingly control data sink, image enhancement itself and
The working condition of data logger；
The clock generator 411 is used to generate clock signal for image enhancement chip.Further, the clock hair
The clock signal of generation is respectively sent to vision signal multiplier 49 and storage signal multiplier 410 by raw device, and by the video
Clock signal is sent to data sink by signal multiplier 49, is sent to clock signal by the storage signal multiplier 410
Dynamic memory and static memory.
It is respectively the external connection circuit diagram of image enhancement chip please refer to Figure 37 and Figure 38.
Further, described image enhancing chip exterior is equipped with：For receiving the power port of supply voltage, being used for reception figure
As the receiver port 401 of signal, the video signal port 402 for exporting vision signal, for receiving external clock letter
Number clock signal port 403, the row field signal port 404 for exporting row field signal.
Specifically, in the present embodiment, the external voltage of the power port includes tri- kinds of electricity of 3.3V, 1.8V and 1.2V
Pressure.Figure 39 is please referred to, is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltages.The filter circuit is including an inductance and extremely
A few capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, each capacitance
The other end and ground connection；Power port is accessed in one end of the inductance and capacitance connection.
Figure 40-41 is please referred to, is respectively that 3.3V is converted to the power-switching circuit figure of 1.8V and 3.3V is converted to 1.2V
Conversion circuit figure.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is respectively converted into 1.8V and 1.2V
Voltage.Specifically, the power-switching circuit includes a power conversion chip；The input terminal of the power conversion chip accesses
The voltage of 3.3V, output end export the voltage of 1.8V and 1.2V respectively, to be powered to image enhancement chip.
Figure 42 is please referred to, is the partial enlarged view of the receiver port of image enhancement chip.The signal receiving end
Mouth 401 includes 20 signal pins, is connect with internal data sink 41, the picture signal for receiving input.
Please refer to Figure 43 a and 43b, be respectively the video signal port of image enhancement chip first part and second
The partial enlarged view divided.The video signal port 402 includes 20 signal pins, is connected with internal data logger 46
It connects, for exporting picture signal.
Figure 44 is please referred to, is the circuit diagram of the clock circuit of image enhancement chip.Further, the clock signal port
A 403 external clock circuits a comprising clock shakes chip；The shake power end of chip of the clock passes through a filter circuit and power supply and connects
It connects, the shake output end of chip of the clock is connect with the clock signal port；The filter circuit includes by an inductance and capacitance string
Connection composition, one end of the inductance are connect with power supply, the other end and capacitance connection, and the other end ground connection of the capacitance.
Figure 45 is please referred to, is the partial enlarged view of the row field signal port of image enhancement chip.The row field signal end
Mouth 404 includes a row signal pins and a field signal pin.The row field signal port 404 is used to control video output
Frequency and sequence.Such as：The display frequency and display order of vision signal on the screen can be controlled, can be every under upper
Row output, can also be to export from left to right.
The course of work of the video acquisition processing circuit of the present invention is described below：
S11：It will be to the outside of the video capture processor, picture processing chip, signal conversion chip and image enhancement chip
Port carries out circuit access according to above-mentioned requirement；
S12：When video capture processor is powered, first passes through the frequency multiplier and input voltage frequency is subjected to multiplication adjusting, with
Adapt to current working frequency；
S13：The controller 11 sends trigger signal to driver 12, drives photoreceptor 13 to work by driver 12；
S14：When light is irradiated on photoreceptor 13, electric signal is converted optical signals to by the photoreceptor 13, and transmit
To sampler 14；
S15：When sampler 14 receives the electric signal from photoreceptor 13, processing is sampled to the electric signal, and will
The electric signal handled is sent to follower 15；
S16：The electric signal is converted into digital signal finally by the follower 15, and is exported to image procossing
Chip 30.
S17：The data sink 21 receives external image data；
S8：Described image processor 23 handles image.Specifically pass through the Lens Shading Compensation circuit 231 respectively
The shade that camera lens generates is compensated into processing；Pass through 233 detection image of the optical detection circuit 232 and flash detection circuit
Brightness and flashing state, and result of detection is sent to exposure gain circuit；Then increased by the exposure gain circuit 234
Exposure gain size.Finally again by the white balance permanent circuit 35 according to preset parameter, carries out the fixed of white balance and adjust
It is whole.
S19：By treated, image data is exported to the first signal conversion chip 31 data logger 24.
S20：The bt1120 that the data reader 312 of the first signal conversion chip receives picture processing chip output is passed
Defeated signal, and it is sent to signal format converter；
S21：Bt1120 vision signals are converted to the vision signal of lvds by the signal format converter 313, and are sent
To serializer 314；
S22：The serializer 314 converts parallel data into serial data, and is sent to data logger；
S23：The data logger 315, for exporting lvds signal datas to second signal conversion chip.
S24：The lvds videos of the first signal conversion chip are passed by the data reader 322 in second signal conversion chip
Defeated signal, and it is sent to signal format converter；
S25：Lvds vision signals are converted to the vision signal of bt1120 by the signal format converter 323, and are sent
To deserializer；
S26：The deserializer 324 converts serial data into parallel data, and is sent to data logger；
S27：The data logger 325 exports bt1120 video signal datas to image enhancement chip 40.
S28：External image data is received by the data sink 41 of image enhancement chip 40；
S29：The data sink 41 receives viewdata signal, and is sent to de-noising processor 42；
S30：The de-noising processor 42 carries out noise reduction process, then is forwarded to dynamic memory 43.
S31：The dynamic memory 43 is after receiving de-noising processor 42 treated image data, then is forwarded to figure
Image intensifier 44.
S32：Described image booster 44 a comprising image border enhances circuit；Described image edge enhances circuit and increases
The clarity of strong image border.Described image booster first will treated that image data is sent to the pixel adaptively proofreads
Device 45.
S33：The adaptive proofreading equipment 45 of pixel carries out pixel and adapts to check and correction, retransmits to data logger 46.
S34：By treated, image data exports the data logger 46.
Compared with the prior art, the present invention is in camera lens part by increasing by a picture processing chip, to the image of acquisition into
Row processing, increases by an image enhancement chip on host backstage, carries out level image enhancing, keeps the image finally exported more clear
It is clear.
First, it is divided into multiple function modules in picture processing chip, is coordinated respectively and independently by each function module
Work, can realize low-power consumption, low-light (level), and can be the picture more high definition of output.Meanwhile further at the image
A white balance permanent circuit is set in reason device, for the white balance parameter to be fixed, without carrying out white balance at work
Adjusting, to prevent aberration interference the phenomenon that.
Then, it is also divided into multiple function modules in image enhancement chip, is assisted respectively and independently by each function module
Work is adjusted, can realize the enhancing processing to image.Meanwhile image border enhancing is further set in the image intensifier
Circuit, to enhance the clarity of image border.
In addition, in order to improve the stability of signal transmission, the present invention by the way that bt1120 signals are first converted to lvds signals,
To the transmission stablized, and there is low noise ability.Then, it is being bt1120 signals by lvds signals revivifications, to ensure that
The quality of the picture of follow-up play.
The invention is not limited in the above embodiments, if the various changes or deformation to the present invention do not depart from the present invention
Spirit and scope, if these changes and deformation belong within the scope of the claim and equivalent technologies of the present invention, then this hair
It is bright to be also intended to comprising these changes and deformation.
Claims (9)
1. a kind of video acquisition processing circuit for medical endoscope, it is characterised in that：At video capture processor, image
Manage chip, signal conversion chip and image enhancement chip；
Video data after acquisition is sent to picture processing chip and is handled by the video capture processor；
The signal conversion chip includes the first signal conversion chip and second signal conversion chip；First signal converts core
Piece is used to bt1120 signals being converted to lvds signals；The second signal conversion chip is for being converted to lvds signals
Bt1120 signals；
By treated, picture signal is sent to the first signal conversion chip to described image processing chip, and is turned by first signal
It changes chip and is sent to second signal conversion chip；The second signal conversion chip is sent to image enhancement core after converting signal
Piece；
Include inside the video capture processor：Controller, driver, photoreceptor, sampler and follower；
--- the controller is used to receive external trigger signal, sends trigger signal to driver；
--- the driver is used to receive the trigger signal of controller, and photoreceptor is driven to work；
--- the photoreceptor is used to receive extraneous optical signal, and the optical signal is converted to electric signal；
--- the sampler is used to be sampled processing to the electric signal of photoreceptor, and the electric signal handled is sent
To follower；
--- the follower is used to the electric signal being converted to digital signal, and carries out output picture processing chip；
Described image processing chip includes：Data sink, master controller, image processor, data logger；
--- the data sink is used to receive external image data；
--- the master controller is used to receive external trigger signal, and accordingly controls the data sink, image
The working condition of processor and data logger；
--- described image processor is used to handle image；Described image processor includes that a white balance fixes electricity
Road is used to carry out the fixed adjustment of white balance according to preset parameter；
--- the data logger is used for that image data to export by treated；
The first signal conversion chip includes：Controller, data reader, signal format converter, serializer, data output
Device；
--- the controller is used to receive external trigger signal, and control data reader, signal format converter,
The work of serializer and data logger；
--- the data reader is used to receive external bt1120 transmission signals, and is sent to signal format converter；
--- the signal format converter is used to be converted to bt1120 vision signals the vision signal of lvds, and sends
To serializer；
--- the serializer is used to convert parallel data into serial data, and is sent to data logger；
--- the data logger, for exporting lvds signal datas to second signal conversion chip；
The second signal conversion chip includes：Controller, data reader, signal format converter, deserializer, data output
Device；
--- the controller is used to receive external trigger signal, and control data reader, signal format converter,
The work of deserializer and data logger；
--- the data reader is used for the lvds video transfer signals of the first signal conversion chip, and is sent to signal
Format converter；
--- the signal format converter is used to be converted to lvds vision signals the vision signal of bt1120, and sends
To deserializer；
--- the deserializer is used to convert serial data into parallel data, and is sent to data logger；
--- the data logger, for bt1120 video signal datas to be exported；
Described image enhances chip：Data sink, controller, static memory, image intensifier, data logger and
Clock generator；
--- the data sink is used to receive viewdata signal, and is sent to the image intensifier；
--- the controller is used to receive outer triggering signal, and accordingly controls data sink, image enhancement its sum number
According to the working condition of follower；
--- the static memory is used to store the driving data of image intensifier, to drive the work of the image intensifier
Make；
--- described image booster a comprising image border enhances circuit；Described image edge enhancing circuit is for enhancing
The clarity of image border；
--- the data logger is used to receive image intensifier treated image data, and carries out data output；
--- the clock generator is used to generate clock signal for image enhancement chip.
2. being used for the video acquisition processing circuit of medical endoscope according to claim 1, it is characterised in that：The video is adopted
It further includes a frequency multiplier to collect chip, is used to carry out the frequency of externally input trigger signal to double processing, retransmit to control
Device processed；
Described image processing chip further includes a frequency multiplier, is used to carry out the frequency of externally input trigger signal to double place
Reason, retransmits to master controller；
The first signal conversion chip further includes a phase-locked loop, is connect respectively with signal format converter and serializer, is used
In unified integration clock signal；
The second signal conversion chip further includes a phase-locked loop, is connect respectively with signal format converter and serializer, is used
In unified integration clock signal；
It further includes a de-noising processor that described image, which enhances chip,；The viewdata signal that the data sink receives, hair
It send to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
3. being used for the video acquisition processing circuit of medical endoscope according to claim 1, it is characterised in that：At described image
The image processor managed in chip further includes an exposure gain circuit, for increasing exposure gain size；
The first signal conversion chip further includes a clock data restorer, is connect with data reader, is used for from transmission
Restore data in the distortion of channel and noise；
The second signal conversion chip further includes a clock data restorer, is connect with data reader, is used for from transmission
Restore data in the distortion of channel and noise；
It further includes a dynamic memory that described image, which enhances chip,；The de-noising processor treated image data, first sends
It is stored to dynamic memory, then is forwarded to image intensifier.
4. being used for the video acquisition processing circuit of medical endoscope according to claim 2, it is characterised in that：At described image
It further includes an optical detection circuit and flash detection circuit to manage device, is used for brightness and the flashing state of detection image, and will visit
It surveys result and is sent to exposure gain circuit；
It further includes the adaptive proofreading equipment of a pixel that described image, which enhances chip,；Described image booster first will treated picture number
According to the adaptive proofreading equipment of the pixel is sent to, pixel is carried out by the adaptive proofreading equipment of the pixel and adapts to check and correction, is retransmited to number
According to follower.
5. being used for the video acquisition processing circuit of medical endoscope according to claim 1, it is characterised in that：The video is adopted
Collection chip exterior is equipped with：For receiving the power port of supply voltage, the video signal port for exporting vision signal, being used for
Export the row field signal port of row field signal, the reference signal port for receiving reference voltage electricity frequency and one is used to receive outside
The clock signal port of clock signal；
It is equipped with outside described image processing chip：Power port for receiving supply voltage, the letter for receiving picture signal
Number receiving port, the row field signal port for exporting row field signal, is used for the video signal port for exporting vision signal
Receive the clock signal port of external timing signal, the data receiver port for receiving storage data and one is used to receive outside
The PORT COM of communication command；
It is equipped with outside the first signal conversion chip：The center processing chip exterior is equipped with：For receiving supply voltage
Power port, the receiver port for receiving bt1120 vision signals, the vision signal for exporting lvds vision signals
Port and row field signal port for exporting row field signal；
It is equipped with outside the second signal conversion chip：The center processing chip exterior is equipped with：For receiving power supply electricity
The power port of pressure, the receiver port for receiving lvds vision signals and the video for exporting bt1120 vision signals
Signal port；
Described image enhancing chip exterior is equipped with：Power port for receiving supply voltage, the letter for receiving picture signal
Number receiving port, the row field signal port for exporting row field signal, is used for the video signal port for exporting vision signal
Receive the clock signal port of external timing signal and the data receiver port for receiving storage data.
6. being used for the video acquisition processing circuit of medical endoscope according to claim 5, it is characterised in that：The video is adopted
The power port of collection chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes an inductance and at least one
Capacitance；Described inductance one end is connect with external power supply, the other end respectively with each capacitance connection, the other end of each capacitance
With ground connection；Power port is accessed in one end of the inductance and capacitance connection；
The power port of described image processing chip is circumscribed with a filter circuit for voltage stabilizing；The filter circuit includes one
Inductance and at least one capacitance；Described inductance one end is connect with external power supply, and the other end is described every respectively with each capacitance connection
The other end of a capacitance and ground connection；Power port is accessed in one end of the inductance and capacitance connection.
7. being used for the video acquisition processing circuit of medical endoscope according to claim 5, it is characterised in that：The video is adopted
The row field signal port of collection chip is circumscribed with the resistance for providing signal strength.
8. being used for the video acquisition processing circuit of medical endoscope according to claim 5, it is characterised in that：The video is adopted
The reference signal port of collection chip is circumscribed with the capacitance as voltage electricity frequency reference data.
9. being used for the video acquisition processing circuit of medical endoscope according to claim 5, it is characterised in that：The video is adopted
Collect the external clock circuit in clock signal port of chip comprising a clock shakes chip；The shake power end of chip of the clock passes through
One filter circuit is connect with power supply, and the shake output end of chip of the clock is connect by a debug circuit with the clock signal port；
The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and capacitance
Connection, and the other end ground connection of the capacitance；The clock shake chip power end and connection and inductance and capacitance between；The debugging
Electric routing resistance and capacitance composition；One end of the resistance of the debug circuit and the output end of Zhong Zhen connect, and the other end connects with capacitance
It connects, and the other end ground connection of the capacitance；The clock signal port is connected between the resistance and capacitance；
The external clock circuit in described image processing chip clock signal port a comprising clock shakes chip；The clock shakes chip
Power end connect with power supply by a filter circuit, the shake output end of chip of the clock passes through a debug circuit and the clock and believes
The connection of number port；The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, separately
One end and capacitance connection, and the other end ground connection of the capacitance；The clock shake chip power end with connect with inductance and capacitance it
Between；The debug circuit is made of resistance and capacitance；One end of the resistance of the debug circuit and the output end of Zhong Zhen connect, another
End and capacitance connection, and the other end ground connection of the capacitance；The clock signal port is connected between the resistance and capacitance；
Described image enhances the external clock circuit in clock signal port of chip comprising a clock shakes chip；The clock shakes core
The power end of piece is connect by a filter circuit with power supply, and the shake output end of chip of the clock is connect with the clock signal port；
The filter circuit includes being composed in series by an inductance and capacitance, and one end of the inductance is connect with power supply, the other end and capacitance
Connection, and the other end ground connection of the capacitance.
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Denomination of invention: A Video Acquisition and Processing Circuit for Medical Endoscopes Effective date of registration: 20230524 Granted publication date: 20180807 Pledgee: Zengcheng sub branch of Bank of Guangzhou Co.,Ltd. Pledgor: GUANGZHOU SOFTLINK MEDICAL INNOVATION Co. LTO Registration number: Y2023980041627 |
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