CN105049689B - A kind of image of medical endoscope is processed enhancing, video record and display circuit - Google Patents
A kind of image of medical endoscope is processed enhancing, video record and display circuit Download PDFInfo
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- CN105049689B CN105049689B CN201510385731.7A CN201510385731A CN105049689B CN 105049689 B CN105049689 B CN 105049689B CN 201510385731 A CN201510385731 A CN 201510385731A CN 105049689 B CN105049689 B CN 105049689B
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Abstract
The image that the present invention relates to a kind of medical endoscope is processed enhancing, video record and display circuit, comprises picture processing chip, signal conversion chip, figure image intensifying chip, video record chip and display driver chip; Described signal conversion chip comprises first signal conversion chip and secondary signal conversion chip; Picture signal after treatment is sent to first signal conversion chip by described picture processing chip, and be sent to secondary signal conversion chip by this first signal conversion chip; Described secondary signal conversion chip will be sent to figure image intensifying chip after signal conversion; The video image of reception is strengthened processing by described figure image intensifying chip, and be sent to video record chip and display driver chip simultaneously, recorded by this video record chip, play in real time by this display driver chip; Described video record chip completes after video record, is sent to display driver chip, carries out video playback.
Description
Technical field
The present invention relates to a kind of image processing circuit, particularly a kind of image for medical endoscope is processed enhancing, video recordAnd display circuit.
Background technology
Endoscope is a kind of conventional medicine equipment, is made up of flexible part, light source and an arrangement of mirrors head. Through the natural hole of human bodyRoad, or the little otch that underwent operative is done enters in human body, when use, endoscope imported to the organ of preliminary examination, can directly spy onAbout the variation at position.
When endoscope is during at inside of human body, divide and carry out video acquisition by the camera lens part of this endoscope, and the video after gathering is passedTransport to main frame backstage and carry out image processing, and play in real time. Then,, because doctor is in surgical procedure, it is right to needSome pictures or video repeat to watch.
Wherein, the quality of picture quality directly affects the result of use of endoscope. Existing general use fujinon electronic video endoscope carries outObserve, and the image after observing is sent to the outside treatment system connecting carries out image processing. But, owing to entering in human bodyWhen row IMAQ, can be due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate automatically or byCause image to occur aberration in the color of light, so cause, in the image in later stage is processed, being difficult to the image of rediscover,Make doctor's almost illegible in the time observing. Therefore need to provide one to be specifically designed to enhancing picture quality, and record endoscope collectionThe circuit of video.
Summary of the invention
The invention reside in the shortcoming that overcomes prior art with not enough, provide a kind of image for medical endoscope to process and strengthen and recordCircuit processed.
The present invention is achieved through the following technical solutions: a kind of image of medical endoscope is processed enhancing, video record and display circuit,It is characterized in that: comprise picture processing chip, signal conversion chip, figure image intensifying chip, video record chip and display driverChip; Described signal conversion chip comprises first signal conversion chip and secondary signal conversion chip; Described first signal conversion coreSheet is for being converted to lvds signal by bt1120 signal; Described secondary signal conversion chip is for being converted to bt1120 by lvds signalSignal;
Picture signal after treatment is sent to first signal conversion chip by described picture processing chip, and changed by this first signalChip is sent to secondary signal conversion chip;
Described secondary signal conversion chip will be sent to figure image intensifying chip after signal conversion;
The video image of reception is strengthened processing by described figure image intensifying chip, and be sent to video record chip and demonstration simultaneouslyDrive chip, recorded by this video record chip, play in real time by this display driver chip;
Described video record chip completes after video record, is sent to display driver chip, carries out video playback.
Than prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathering,On main frame backstage, increase by a figure image intensifying chip, carry out secondary figure image intensifying, make the image of last output more clear, lastBe sent to respectively again video record chip and display driver chip, carry out video record and play in real time; And video record chipBe connected with driving display chip, can carry out playing back videos by this driving display chip.
First, in picture processing chip, be divided into multiple functional modules, respectively and by each functional module independence co-ordination,Can realize low-power consumption, low-light (level), and can be the picture high definition more of output. Meanwhile, further at this image processorIn a white balance permanent circuit is set, for this white balance parameter is fixed, without carry out the adjusting of white balance in when work,Thereby prevent the phenomenon that aberration disturbs.
Then, in figure image intensifying chip, be also divided into multiple functional modules, respectively and by each functional module independence co-ordination,Can realize the enhancing processing to image. Meanwhile, an image border intensifier circuit is further set in this image intensifier, usesTo strengthen the definition of image border.
In addition, in order to improve the stability of signal transmission, the present invention is by first bt1120 signal being converted to lvds signal, therebyStable transmission, and there is low noise ability. Then, lvds signal is being reduced to bt1120 signal, thereby is ensureing follow-upThe quality of the picture of playing.
As a further improvement on the present invention, described picture processing chip comprises: data sink, master controller, image placeReason device, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the described data sink of corresponding control, imageThe duty of processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit,It,, for according to default parameter, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting view data after treatment;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data are defeatedGo out device;
---described controller, it is for receiving outside triggering signal, and control data reader, signal format converter,The work of serializer and data logger;
---described data reader, it is for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it is for bt1120 vision signal being converted to the vision signal of lvds, and is sent toSerializer;
---described serializer, it is for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, numberAccording to follower;
---described controller, it is for receiving outside triggering signal, and control data reader, signal format converter,The work of deserializer and data logger;
---described data reader, it is for the lvds video transfer signal of first signal conversion chip, and is sent to signal latticeFormula converter;
---described signal format converter, it is for lvds vision signal being converted to the vision signal of bt1120, and is sent toDeserializer;
---described deserializer, it is for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described figure image intensifying chip comprises: data sink, controller, static memory, image intensifier, data are defeatedGo out device and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and corresponding control data sink, image intensifier and numberAccording to the duty of follower;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is used for strengthening figureThe definition at picture edge;
---described data logger, it is for receiving image intensifier view data after treatment, and carries out data output;
---described clock generator, it is used to figure image intensifying chip clocking;
Described video record chip comprises: data sink, video encoder, Video Decoder, data logger and locateReason device;
---described data sink, for receiving outside vision signal, and is sent to video encoder;
---described video encoder, for encoding video signal is recorded;
---described Video Decoder, for to decoding video signal playback;
---described data logger, for vision signal is exported;
---described processor, for controlling the work of data sink, video encoder, Video Decoder and data logger;
Described display driver chip comprises: receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer, defeatedGo out format converter, data logger and controller;
---described receiver of the analog signal, for receiving analog signal, and is sent to analog-digital converter;
---described analog-digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;
---described data-signal receiver, for receiving data-signal, and is sent to multiplexer;
---described multiplexer, for two paths of signals is integrated, the line output of going forward side by side is to output format converter;
---described output format converter, for signal format is changed, and exports data logger to;
---described data logger, by signal output, and shows;
---described controller, for control simulation signal receiver, digit signal receiver, analog-digital converter, multiplexer,The work of output format converter and data logger.
As a further improvement on the present invention, described picture processing chip also comprises a frequency multiplier, and it is for touching outside inputThe frequency of signaling increases doubly to be processed, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected with signal format converter and serializer respectively, forUnified integration clock signal;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected with signal format converter and serializer respectively, forUnified integration clock signal;
Described figure image intensifying chip also comprises a de-noising processor; The viewdata signal that described data sink receives, sendsCarry out noise reduction process to de-noising processor, then be forwarded to image intensifier;
Described video record chip also comprises an image processor, processes for the video that data sink is received, andImage after treatment is sent to video encoder;
Described display driver chip also comprises a Video Decoder, field flyback data processor and memory;
Described Video Decoder, decodes for the analog signal that receiver of the analog signal is received, and is sent to field flyback numberAccording to processor;
Described field flyback data processor, for by capable decoded analog signal data inserting, and be sent to described memory and enterRow storage;
Described memory, for storing the data after field flyback data processor processes, and is sent to output format converter.
As a further improvement on the present invention, described image processor also comprises an exposure gain circuitry, for increasing exposure gainSize;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for believing from transmissionIn the distortion in road and noise, recover data;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for believing from transmissionIn the distortion in road and noise, recover data;
Described figure image intensifying chip also comprises a dynamic memory; Described de-noising processor view data after treatment, is first sent toDynamic memory is stored, then is forwarded to image intensifier;
The image processor of described video record chip comprises edge intensifier circuit and the interfered circuit that abates the noise;
Described display driver chip also comprises an image border smoothing processing device, for receiving the signal of restorer, and to video figureThe edge of picture carries out smoothing processing, then is sent to format converter.
As a further improvement on the present invention, described image processor also comprises an optical detection circuit and flash detection circuit, itsFor brightness and the flicker situation of detection image, and result of detection is sent to exposure gain circuitry;
Described figure image intensifying chip also comprises a pixel self adaptation proofreading equipment; Described image intensifier is first by view data after treatmentBe sent to described pixel self adaptation proofreading equipment, carry out pixel by this pixel self adaptation proofreading equipment and adapt to check and correction, then it be defeated to be sent to dataGo out device.
As a further improvement on the present invention, described figure image intensifying chip also comprises a vision signal multiplier and a storage signal doublyIncrease device; Described clock generator, is sent to respectively vision signal multiplier and storage signal multiplier by the clock signal of generation,And by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sentTo dynamic memory and static memory.
As a further improvement on the present invention, described picture processing chip outside is provided with: for receive supply voltage power port,For receiving the receiver port of picture signal, for the video signal port of outputting video signal, for exporting row field signalRow field signal port, for receive the clock signal port of external timing signal, for receive storage data data receiverMouth and one is for receiving the PORT COM of external communication order;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receiving the electricity of supply voltageSource port, for receiving the receiver port of bt1120 vision signal, for exporting the video signal port of lvds vision signalWith the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receiving supply voltagePower port, for receiving the receiver port of lvds vision signal and for exporting the vision signal of bt1120 vision signalPort;
Described figure image intensifying chip exterior is provided with: for receiving the power port of supply voltage, for receiving the signal of picture signalReceiving port, for the video signal port of outputting video signal, for exporting the row field signal port of row field signal, for connecingReceive external timing signal clock signal port and for receive storage data data receiver port;
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; InstituteState video input port and be connected with the data sink of this video record chip internal, for receiving outside video data; DescribedVideo-out port, is connected with described data logger, for output video data; Described PORT COM, with described processorConnect, for receiving outside serial port command;
Described display driver chip outside is provided with: power port, video input port, video-out port and PORT COM; InstituteState video input port and be connected with the data sink of this video record chip internal, for receiving outside video data; DescribedVideo-out port, is connected with described data logger, for output video data; Described PORT COM, with described processorConnect, for receiving outside serial port command.
As a further improvement on the present invention, the power port of described picture processing chip is circumscribed with a filter circuit for voltage stabilizing;Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, the other end respectively withEach electric capacity connects, the other end of described each electric capacity and ground connection; One end access power port that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with a filter circuit for voltage stabilizing; Described filter circuit comprises an electricitySense and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, described eachThe other end of electric capacity and ground connection; One end access power port that described inductance is connected with electric capacity;
The power port of described video record chip is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least oneElectric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected in magnetic bead and electricityBetween appearance;
Described display driver chip power port is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electricityHold; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected in magnetic bead and electric capacityBetween.
As a further improvement on the present invention, the external clock circuit of the clock signal port of described picture processing chip, it comprisesThe one clock chip that shakes; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock passes throughOne debug circuit is connected with described clock signal port; Described filter circuit comprises by an inductance and capacitances in series and forming, described electricityOne end of sense is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; The shake power end of chip of described clockBe connected between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit and clockThe output shaking connects, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected in thisBetween resistance and electric capacity;
The external clock circuit of clock signal port of described figure image intensifying chip, it comprises the clock chip that shakes; The described clock chip that shakesPower end be connected with power supply by a filter circuit, the shake output of chip of this clock is connected with described clock signal port; DescribedFilter circuit comprises by an inductance and capacitances in series and forming, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity,And the other end ground connection of this electric capacity.
As a further improvement on the present invention, the data receiver port of described picture processing chip is circumscribed with a memory circuitry, itsComprise a memory, be connected to the filter circuit of the voltage port of this memory, and be connected to the output port of this memoryResistance.
In order to understand better and to implement, describe the present invention in detail below in conjunction with accompanying drawing.
Brief description of the drawings
Fig. 1 is chip connection diagram of the present invention.
Fig. 2 is the internal module connection diagram of picture processing chip.
Fig. 3 is the circuit module schematic diagram of the image processor of picture processing chip.
Fig. 4 is the voltage segment circuit diagram of picture processing chip.
Fig. 5 is the outside port circuit diagram of picture processing chip.
Fig. 6 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Fig. 7 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Fig. 8 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Fig. 9 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 10 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 11 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 12 is the schematic diagram of the clock circuit of picture processing chip.
Figure 13 is the schematic diagram of the memory circuit of picture processing chip.
Figure 14 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 15 is the internal components connection diagram of first signal conversion chip.
Figure 16 is the internal module connection diagram of secondary signal conversion chip.
Figure 17 is the outside port connection diagram of first signal conversion chip.
Figure 18 is the local enlarged diagram of the power port of first signal conversion chip.
Figure 19 is the partial enlarged drawing of the receiver port of first signal conversion chip.
Figure 20 is the partial enlarged drawing of the video signal port of first signal conversion chip.
Figure 21 is the partial enlarged drawing of the row field signal port of first signal conversion chip.
Figure 22 is the outside connecting circuit figure of secondary signal conversion chip.
Figure 23 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 24 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 25 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 26 is the internal module connection diagram of figure image intensifying chip.
Figure 27 is the outside connecting circuit figure of the Part I of figure image intensifying chip.
Figure 28 is the outside connecting circuit figure of the Part II of figure image intensifying chip.
Figure 29 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of figure image intensifying chip.
Figure 30 is the power-switching circuit figure that the 3.3V of figure image intensifying chip is converted to 1.8V.
Figure 31 is the power-switching circuit figure that the 3.3V of figure image intensifying chip is converted to 1.2V.
Figure 32 is the partial enlarged drawing of the receiver port of figure image intensifying chip.
Figure 33 a is the partial enlarged drawing of the video signal port Part I of figure image intensifying chip.
Figure 33 b is the partial enlarged drawing of the video signal port Part II of figure image intensifying chip.
Figure 34 is the circuit diagram of the clock circuit of figure image intensifying chip.
Figure 35 is the partial enlarged drawing of the row field signal port of figure image intensifying chip.
Figure 36 is the internal components connection diagram of video record chip.
Figure 37 is the video input circuit figure of video record chip.
Figure 38 is the video output circuit figure of video record chip.
Figure 39 be video record chip with communication input circuit figure.
Figure 40 is the partial enlarged drawing of the power port of video record chip.
Figure 41 is the partial enlarged drawing of the PORT COM of video record chip.
Figure 42 is the internal components connection diagram of display driver chip.
Figure 43 is the external signal input circuit figure of display driver chip.
Figure 44 is the external signal output circuit figure of display driver chip.
Figure 45 is the partial enlarged drawing of the power port of display driver chip.
Figure 46 is the partial enlarged drawing of the video input port of display driver chip.
Figure 47 is the partial enlarged drawing of the video-out port of display driver chip.
Detailed description of the invention
Refer to Fig. 1, it is chip connection diagram of the present invention. The invention provides a kind of image processing of medical endoscopeEnhancing, video record and display circuit, comprise picture processing chip 10, signal conversion chip 20 and figure image intensifying chip 30;Described signal conversion chip 20 comprises first signal conversion chip 21 and secondary signal conversion chip 22; Described first signal conversionChip 21 is for being converted to lvds signal by bt1120 signal; Described secondary signal conversion chip 22 is for changing lvds signalFor bt1120 signal; Picture signal after treatment is sent to first signal conversion chip 21 by described picture processing chip 10, andBe sent to secondary signal conversion chip 22 by this first signal conversion chip 21; Described secondary signal conversion chip 22 turns signalAfter changing, be sent to figure image intensifying chip 30.
Refer to Fig. 2, the internal module connection diagram that it is picture processing chip. Described picture processing chip comprises: dataReceiver 11, master controller 12, image processor 13, data logger 14.
Described data sink 11, it is for receiving outside view data;
Described master controller 12, it is for receiving outside triggering signal, and the described data sink of corresponding control, image placeThe duty of reason device and data logger;
Described image processor 13, it is for processing image.
Described data logger 14, it is for exporting view data after treatment.
Further, described picture processing chip also comprises a frequency multiplier 15, and it is for entering the frequency of the triggering signal of outside inputRow increases doubly to be processed, then is sent to master controller 12.
Refer to Fig. 3, the circuit module schematic diagram of its image processor that is picture processing chip. Concrete, described image placeReason device 13 comprises a camera lens shading compensation circuit 131, optical detection circuit 132, flash detection circuit 133, exposure gain electricityRoad 134 and white balance permanent circuit 135.
Described camera lens shading compensation circuit 131, it compensates processing for the shade that camera lens is produced.
Described optical detection circuit 132 and flash detection circuit 133, its brightness for detection image and flicker situation, and willResult of detection is sent to exposure gain circuitry.
Described exposure gain circuitry 134, for increasing exposure gain size.
Described white balance permanent circuit 135, it,, for according to default parameter, carries out the fixed adjustment of white balance.
Please refer to Fig. 4 and Fig. 5, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip. SeparatelyFor the application in order to adapt to this picture processing chip, be further provided with in described picture processing chip outside: for receiving outward,The power port 101 of supply voltage, for receiving the receiver port 102 of picture signal, video for outputting video signalSignal port 103, for exporting the row field signal port one 04 of row field signal, for receiving the clock signal terminal of external timing signalMouthfuls 105, for the data receiver port 106 and that receives storage data for receiving the PORT COM 107 of external communication order.
Refer to Fig. 6-8, it is respectively 3.3V, the 1.8V of picture processing chip and the circuit diagram of 1.2V. Further, described electricitySource port 101 is circumscribed with a filter circuit for voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; InstituteState inductance one end and be connected with external power source, the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection;One end access power port that described inductance is connected with electric capacity. Concrete, the external voltage of described picture processing chip comprises: 3.3V,Tri-kinds of 1.8V and 1.2V. Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electricityHold, the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter respectively the interfering signal of different frequency.
Refer to Fig. 9, the partial enlarged drawing of its receiver port that is picture processing chip. Described receiver port 102Comprise 8 pins, for receiving outside video signal.
Refer to Figure 10, the partial enlarged drawing of its video signal port that is picture processing chip. Described video signal port 103Comprise the vision signal of two groups of different-formats, carry out doubleway output, play in real time respectively and record to facilitate.
Refer to Figure 11, the partial enlarged drawing of the row field signal port that it is picture processing chip. Described row field signal port one 04For controlling frequency and the order of video output. Such as: can control display frequency and the DISPLAY ORDER of vision signal on screen,Can be from every line output under upper, can be also to export from left to right.
Refer to Figure 12, the schematic diagram of its clock circuit that is picture processing chip. Described clock signal port 105 external a period of timeClock circuit, it comprises the clock chip that shakes; The shake power end of chip of described clock is connected with power supply by a filter circuit, this Zhong ZhenxinThe output of sheet is connected with described clock signal port by a debug circuit; Described filter circuit comprises by an inductance and electric capacity stringJoint group becomes, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clockShake chip power end be connected between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; This debug circuitOne end of resistance is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock letterNumber port is connected between this resistance and electric capacity.
Refer to Figure 13, the schematic diagram of its memory circuit that is picture processing chip. Further, described data receiver port 106Be circumscribed with a memory circuitry, it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and connectsAt the resistance of the output port of this memory.
Refer to Figure 14, the partial enlarged drawing of its PORT COM that is picture processing chip. Described PORT COM 107 is for receivingThe trigger command of external transmission, to trigger the work of carrying out of this picture processing chip.
Refer to Figure 15, it is the internal components connection diagram of first signal conversion chip. Described first signal conversion chip 21Comprise: controller 211, data reader 212, signal format converter 213, serializer 214, data logger 215,Phase-locked loop 216 and clock data restorer 217;
Described controller 211, it is for receiving outside triggering signal, and controls data reader 212, signal format converter213, the work of serializer 214 and data logger 215;
Described data reader 212, it is for receiving outside bt1120 signal transmission, and is sent to signal format converter;
Described signal format converter 213, it is for bt1120 vision signal being converted to the vision signal of lvds, and is sent toSerializer;
Described serializer 214, it is for parallel data is converted to serial data, and is sent to data logger;
Described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
Described phase-locked loop 216, is connected with signal format converter and serializer respectively, for unified integration clock signal.
Described clock data restorer 217, it is connected with data reader, recovers for the distortion from transmission channel and noiseData.
Refer to Figure 16, it is the internal module connection diagram of secondary signal conversion chip. Described secondary signal conversion chip 22Comprise: controller 221, data reader 222, signal format converter 223, deserializer 224, data logger 225,Phase-locked loop 226 and clock data restorer 227;
Described controller 221, it is for receiving outside triggering signal, and controls data reader 222, signal format converter223, the work of deserializer 224 and data logger 225;
Described data reader 222, it is for the lvds video transfer signal of first signal conversion chip, and is sent to signal latticeFormula converter;
Described signal format converter 223, it is for lvds vision signal being converted to the vision signal of bt1120, and is sent toDeserializer 224;
Described deserializer 224, it is for serial data is converted to parallel data, and is sent to data logger;
Described data logger 225, for exporting bt1120 video signal data.
Described phase-locked loop 226, is connected with signal format converter and deserializer respectively, for unified integration clock signal.
Described clock data restorer 227, it is connected with data reader 222, for the distortion from transmission channel and noiseRecover data.
Refer to Figure 17, it is the outside port connection diagram of first signal conversion chip. Outside described first signal conversion chipPortion is provided with: described center processing chip exterior is provided with: for receiving the power port 2101 of supply voltage, for receiving bt1120The receiver port 2102 of vision signal, for exporting the video signal port 2103 of lvds vision signal and for exporting rowThe row field signal port 2104 of field signal.
Please refer to Figure 18, it is the local enlarged diagram of the power port of first signal conversion chip. Described power port2101 places are circumscribed with the electric capacity for filtering alternating current.
Refer to Figure 19, it is the partial enlarged drawing of the receiver port of first signal conversion chip. Described receiver port2102, it is connected with described data reader 21; Concrete, this receiver port has comprised 20 pins, for receivingThe vision signal of outside bt1120.
Refer to Figure 20, it is the partial enlarged drawing of the video signal port of first signal conversion chip. Described video signal port2103 have comprised 4 output pins, and for exporting lvds vision signal, and this video signal port is connected with this data logger.
Refer to Figure 21, it is the partial enlarged drawing of the row field signal port of first signal conversion chip. Described row field signal port2104 have comprised a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling videoThe frequency of output and order. Such as: can control display frequency and the DISPLAY ORDER of vision signal on screen, can be from upperUnder every line output, can be also to export from left to right.
Refer to Figure 22, it is the outside connecting circuit figure of secondary signal conversion chip. Outside described secondary signal conversion chipPortion is provided with: for receiving the receiver port 2201 of lvds vision signal, believing for the video of exporting bt1120 vision signalNumber port 2202 and row field signal port 2203.
Refer to Figure 23, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip. Described receiver port2201, it is connected with described data reader 221; Concrete, this receiver port has comprised 4 pins, for receivingThe lvds vision signal of first signal conversion chip output.
Refer to Figure 24, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip. Described video signal port2202 have comprised 20 output pins, for exporting bt1120 vision signal, and this video signal port and this data loggerConnect.
Refer to Figure 25, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip. Described row field signal port2203 have comprised a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling videoThe frequency of output and order. Such as: can control display frequency and the DISPLAY ORDER of vision signal on screen, can be from upperUnder every line output, can be also to export from left to right.
Refer to Figure 26, it is the internal module connection diagram of figure image intensifying chip. Described figure image intensifying chip comprises: dataReceiver 31, de-noising processor 32, dynamic memory 33, image intensifier 34, pixel self adaptation proofreading equipment 35, data are defeatedGo out device 36, static memory 37, controller 38, vision signal multiplier 39, storage signal multiplier 310, clock generationDevice 311.
Described data sink 31, it is for receiving viewdata signal, and is sent to de-noising processor 32;
The viewdata signal that described data sink 31 receives, is sent to de-noising processor 32 and carries out noise reduction process, then turnSend to dynamic memory 33.
Described dynamic memory 33 is receiving after de-noising processor 22 view data after treatment, then is forwarded to image intensifier34。
Described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit is used for strengthening imageThe definition at edge. Further, described image intensifier is first sent to view data after treatment described pixel self adaptation check and correctionDevice 35, carries out pixel by this pixel self adaptation proofreading equipment 35 and adapts to check and correction, then be sent to data logger 36.
Described data logger 36, it is for receiving image intensifier view data after treatment, and carries out data output;
Described static memory 37, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 38, it is for receiving outer triggering signal, and corresponding control data sink, image intensifier and dataThe duty of follower;
Described clock generator 311, it is used to figure image intensifying chip clocking. Further, described clock generator,The clock signal of generation is sent to respectively to vision signal multiplier 29 and storage signal multiplier 310, and by this vision signal doublyIncrease device 39 clock signal is sent to data sink, by this storage signal multiplier 310, clock signal is sent to dynamic memoryDevice and static memory.
Please refer to Figure 27 and Figure 28, it is respectively the outside connecting circuit figure of figure image intensifying chip.
Further, described figure image intensifying chip exterior is provided with: for receiving the power port of supply voltage, believing for receiving imageNumber receiver port 301, for the video signal port 302 of outputting video signal, for receive external timing signal timeClock signal port 303, for exporting the row field signal port 304 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and tri-kinds of voltages of 1.2V.Refer to Figure 29, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage. Described filter circuit comprises an inductance and at leastAn electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, described each electric capacity anotherOne end and ground connection; One end access power port that described inductance is connected with electric capacity.
Refer to Figure 30-31, it is respectively power-switching circuit figure and the 3.3V that 3.3V is converted to 1.8V and is converted to turning of 1.2VChange circuit diagram. In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively to 1.8V and 1.2VVoltage. Concrete, described power-switching circuit comprises a power conversion chip; The input access 3.3V of described power conversion chipVoltage, output is exported respectively the voltage of 1.8V and 1.2V, so that figure image intensifying chip is powered.
Refer to Figure 32, it is the partial enlarged drawing of the receiver port of figure image intensifying chip. Described receiver port 301Comprise 20 signal pins, be connected with inner data sink 31, for receiving the picture signal of input.
Refer to Figure 33 a and 33b, it is respectively the Part I of video signal port of figure image intensifying chip and Part IIPartial enlarged drawing. Described video signal port 302 comprises 20 signal pins, and it is connected with inner data logger 36,For output image signal.
Refer to Figure 34, it is the circuit diagram of the clock circuit of figure image intensifying chip. Further, described clock signal port 303An external clock circuit, it comprises the clock chip that shakes; The shake power end of chip of described clock is connected with power supply by a filter circuit,The shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises by an inductance and capacitances in series and forming,One end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 35, it is the partial enlarged drawing of the row field signal port of figure image intensifying chip. Described row field signal port 304Comprise a row signal pins and a field signal pin. Described row field signal port 304 for control video output frequency andSequentially. Such as: can control display frequency and the DISPLAY ORDER of vision signal on screen, can be from every line output under upper,Also can be to export from left to right.
Refer to Figure 36, it is the internal components connection diagram of video record chip. Described video record chip comprises: dataReceiver 41, image processor 42, video encoder 43, Video Decoder 44, data logger 45 and processor 46;
Described data sink 41, for receiving outside vision signal, and is sent to image processor;
Described image processor 42, carries out for the video that receives data sink transmission, and video image is processed, thenBe sent to video encoder; Wherein, described image processor comprises the edge intensifier circuit of the definition for strengthening image borderWith the interfered circuit that abates the noise disturbing for erasure signal.
Described video encoder 43, for recording encoding video signal;
Described Video Decoder 44, for to decoding video signal playback;
Described data logger 45, for exporting vision signal;
Described processor 46, for controlling data sink 41, image processor 42, video encoder 43, Video Decoder44 and the work of data logger 45.
Refer to Figure 37-39, it is video input, video output and the communication input circuit figure of video record chip. Further,Described video record chip exterior is provided with: power port 401, video input port 402, video-out port 403 and communication terminalMouth 404. Described video input port is connected with the data sink of this video record chip internal, for receiving outside videoData; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, withDescribed processor connects, for receiving outside serial port command.
Refer to Figure 40, it is the partial enlarged drawing of the power port of video record chip. Described power port 401 is circumscribed with oneFilter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and this electricityThe other end ground connection of holding; Described power port is connected between magnetic bead and electric capacity.
Refer to Figure 41, it is the partial enlarged drawing of the PORT COM of video record chip. Described PORT COM 404 has comprised twoIndividual pin, carries out communication as serial ports and external command. By the mode of serial communication, the data wire of use is few, can saveCommunications cost.
Refer to Figure 42, the internal components connection diagram that it is display driver chip. Described display driver chip comprises: simulationSignal receiver 51, digit signal receiver 52, analog-digital converter 53, multiplexer 54, image border smoothing processing device 55,Video Decoder 56, field flyback data processor 57, memory 58, output format converter 59, data logger 510 andController 511.
Described receiver of the analog signal 51, for receiving analog signal, and is sent to analog-digital converter 53;
Described digit signal receiver 52, for receiving data-signal, and is sent to multiplexer 54;
Described analog-digital converter 53, for analog signal is converted to data-signal, and is sent to multiplexer 54;
Described multiplexer 54, for two paths of signals is integrated, the line output of going forward side by side is to output image edge-smoothing processor 55;
Described image border smoothing processing device 55, for receiving the signal of restorer, and smoothly locates the edge of video imageReason, then be sent to format converter 59.
Described Video Decoder 56, decodes for the analog signal that receiver of the analog signal is received, and is sent to field flybackData processor 57;
Described field flyback data processor 57, for by capable decoded analog signal data inserting, and is sent to described memory58 store;
Described memory 58, for storing the data after field flyback data processor processes, and is sent to output format converter59。
Described output format converter 59, for signal format is changed, and exports data logger 510 to;
Described data logger 510 carries out color output and the output of lvds vision signal simultaneously.
Described controller 511, for control simulation signal receiver 51, digit signal receiver 52, analog-digital converter 53, multipleWith device 54, image border smoothing processing device 55, Video Decoder 56, field flyback data processor 57, memory 58, outputThe work of format converter 59 and data logger 510.
Refer to Figure 43 and Figure 44, it is respectively external signal input circuit figure and the signal output apparatus figure of display driver chip.Further, the outside of described display driver chip is provided with: power port 501, video reception port 502 and vision signalOutput port 503; Receiver of the analog signal 51 and the numeral of described video reception port 502 and display driver chip insideSignal receiver 52 connects; Described video-out port 503 is connected with the data logger 510 of display driver chip inside.
Refer to Figure 45, the partial enlarged drawing of its power port that is display driver chip. Described power port 501 comprises oneThe power pins of 1.2V and the power pins of 3.3V; Described 1.2V pin is circumscribed with two electric capacity in parallel, for filtering interchangeSignal; Described 3.3V is circumscribed with 5 shunt capacitances, for filtering the AC signal of different frequency.
Refer to Figure 46, the partial enlarged drawing of the video input port that it is display driver chip. Described video input port 502Comprise two groups of pins, one group is used for receiving the recording signal of recording circuit, and another group is for receiving the vision signal of real-time broadcasting.Wherein, pin B5～B8, A5～A8 are for receiving the recording signal of recording circuit, and pin B1～B4, A1～A4 are for receivingThe vision signal of playing in real time.
Refer to Figure 47, the partial enlarged drawing of its video-out port that is display driver chip. Described video-out port 503Comprise 12 groups of pins, be connected with data logger respectively, for exporting playback video signal and real time video signals.
Below the course of work of image processing circuit of the present invention is described:
S1: will be to this picture processing chip, first signal conversion chip, secondary signal conversion chip, and figure image intensifying chipOutside port carries out circuit access according to above-mentioned requirement;
S2: in the time that picture processing chip is switched on, first by this frequency multiplier by the adjusting of doubling of input voltage frequency, work as adapting toFront operating frequency;
S3: first receive outside view data by the data sink 11 of picture processing chip 10;
S4: described image processor 13 is processed image. Specifically pass through respectively described camera lens shading compensation circuit 131 by mirrorThe shade that head produces compensates processing; Bright by described optical detection circuit 132 and flash detection circuit 133 detection imagesDegree and flicker situation, and result of detection is sent to exposure gain circuitry; Then increase exposure by described exposure gain circuitry 134Gain size. Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S5: view data after treatment is exported first signal conversion chip by described data logger 14.
S6: the data reader 212 of described first signal conversion chip receives the bt1120 signal transmission of picture processing chip output,And be sent to signal format converter;
S7: described signal format converter 213 is converted to bt1120 vision signal the vision signal of lvds, and is sent to serialDevice 214;
S8: parallel data is converted to serial data by described serializer 214, and be sent to data logger;
S9: described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
S10: the lvds transmission of video of first signal conversion chip is believed by the data reader 222 in secondary signal conversion chipNumber, and be sent to signal format converter;
S11: described signal format converter 223 is converted to lvds vision signal the vision signal of bt1120, and is sent to alsoRow device;
S12: serial data is converted to parallel data by described deserializer 224, and be sent to data logger;
S13: described data logger 225 exports bt1120 video signal data to figure image intensifying chip.
S14: the data sink 31 by figure image intensifying chip receives outside view data;
S15: described data sink 31, receives viewdata signal, and be sent to de-noising processor 32;
S16: described de-noising processor 32 carries out noise reduction process, then is forwarded to dynamic memory 33.
S17: described dynamic memory 33 is receiving after de-noising processor 32 view data after treatment, then be forwarded to image increasingStrong device 34.
S18: described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens figureThe definition at picture edge. Described image intensifier is first sent to view data after treatment described pixel self adaptation proofreading equipment 35.
S19: described pixel self adaptation proofreading equipment 35 carries out pixel and adapts to check and correction, then is sent to data logger 36.
S20: described data logger 36 exports respectively view data after treatment to video record chip 40 and demonstration is drivenMoving chip 50.
S21: in receiving outside vision signal, and be sent to image place by the described data sink 41 of video record chip 40Reason device 42;
S22: the video that described image processor 42 receives data sink transmission carries out, and video image is processed, thenBe sent to video encoder 43; Wherein, described image processor comprises that the edge of the definition for strengthening image border strengthens electricityRoad and the interfered circuit that abates the noise disturbing for erasure signal.
S23: described video encoder 43 is recorded encoding video signal;
S24: in the time receiving external communication order, described Video Decoder 44 is to decoding video signal playback, and transmissionTo data logger 45;
S25: described data logger 45 exports display driver chip to vision signal.
S26: the receiver of the analog signal 51 of described display driver chip receives analog signal, and be sent to analog-digital converter 53;
S27: described digit signal receiver 52 receives data-signal, and be sent to multiplexer 54;
S28: analog signal is converted to data-signal by described analog-digital converter 53, and be sent to multiplexer 54;
S29: described multiplexer 54 is integrated two paths of signals, the line output of going forward side by side is to output image edge-smoothing processor 55;
S39: described image border smoothing processing device 55 receives the signal of restorer, and the edge of video image is smoothly locatedReason, then be sent to format converter 59.
S31: the analog signal that described Video Decoder 56 receives receiver of the analog signal is decoded, and is sent to field flybackData processor 57;
S32: described field flyback data processor 57, for by capable decoded analog signal data inserting, and described in being sent toMemory 58 is stored;
S33: described memory 58 is stored the data after field flyback data processor processes, and be sent to output format converter 59。
S34: described output format converter 59, for signal format is changed, and exports data logger 510 to;
S35: described data logger 510 carries out color output and the output of lvds vision signal simultaneously.
Than prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathering,On main frame backstage, increase by a figure image intensifying chip, carry out secondary figure image intensifying, make the image of last output more clear.
First, in picture processing chip, be divided into multiple functional modules, respectively and by each functional module independence co-ordination,Can realize low-power consumption, low-light (level), and can be the picture high definition more of output. Meanwhile, further at this image processorIn a white balance permanent circuit is set, for this white balance parameter is fixed, without carry out the adjusting of white balance in when work,Thereby prevent the phenomenon that aberration disturbs.
Then, in figure image intensifying chip, be also divided into multiple functional modules, respectively and by each functional module independence co-ordination,Can realize the enhancing processing to image. Meanwhile, an image border intensifier circuit is further set in this image intensifier, usesTo strengthen the definition of image border.
In addition, in order to improve the stability of signal transmission, the present invention is by first bt1120 signal being converted to lvds signal, therebyStable transmission, and there is low noise ability. Then, lvds signal is being reduced to bt1120 signal, thereby is ensureing follow-upThe quality of the picture of playing.
The present invention is not limited to above-mentioned embodiment, if various changes of the present invention or distortion are not departed to spirit of the present inventionAnd scope, if within these changes and distortion belong to claim of the present invention and equivalent technologies scope, the present invention is also intended toComprise these changes and distortion.
Claims (9)
1. the image of medical endoscope is processed enhancing, video record and a display circuit, it is characterized in that: comprise image processing coreSheet, signal conversion chip, figure image intensifying chip, video record chip and display driver chip; Described signal conversion chipComprise first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signalBe converted to lvds signal; Described secondary signal conversion chip is for being converted to bt1120 signal by lvds signal;
Picture signal after treatment is sent to first signal conversion chip by described picture processing chip, and changed by this first signalChip is sent to secondary signal conversion chip;
Described secondary signal conversion chip will be sent to figure image intensifying chip after signal conversion;
The video image of reception is strengthened processing by described figure image intensifying chip, and be sent to video record chip and demonstration simultaneouslyDrive chip, recorded by this video record chip, play in real time by this display driver chip;
Described video record chip completes after video record, is sent to display driver chip, carries out video playback;
Wherein, described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the described data sink of corresponding control, imageThe duty of processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit,It,, for according to default parameter, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting view data after treatment;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, numberAccording to follower;
---described controller, it is for receiving outside triggering signal, and control data reader, signal format converter,The work of serializer and data logger;
---described data reader, it is for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it is for bt1120 vision signal being converted to the vision signal of lvds, and is sent toSerializer;
---described serializer, it is for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, numberAccording to follower;
---described controller, it is for receiving outside triggering signal, and control data reader, signal format converter,The work of deserializer and data logger;
---described data reader, it is for receiving the lvds video transfer signal of first signal conversion chip, and is sent to letterNumber format converter;
---described signal format converter, it is for lvds vision signal being converted to the vision signal of bt1120, and is sent toDeserializer;
---described deserializer, it is for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described figure image intensifying chip comprises: data sink, controller, static memory, image intensifier, data are defeatedGo out device and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and corresponding control data sink, image intensifier and numberAccording to the duty of follower;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is used for strengthening figureThe definition at picture edge;
---described data logger, it is for receiving image intensifier view data after treatment, and carries out data output;
---described clock generator, it is used to figure image intensifying chip clocking;
Described video record chip comprises: data sink, video encoder, Video Decoder, data logger and locateReason device;
---described data sink, for receiving outside vision signal, and is sent to video encoder;
---described video encoder, for encoding video signal is recorded;
---described Video Decoder, for to decoding video signal playback;
---described data logger, for vision signal is exported;
---described processor, for controlling the work of data sink, video encoder, Video Decoder and data logger;
Described display driver chip comprises: receiver of the analog signal, digit signal receiver, analog-digital converter, multiplexer,Output format converter, data logger and controller;
---described receiver of the analog signal, for receiving analog signal, and is sent to analog-digital converter;
---described analog-digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;
---described digit signal receiver, for receiving data-signal, and is sent to multiplexer;
---described multiplexer, for two paths of signals is integrated, the line output of going forward side by side is to output format converter;
---described output format converter, for signal format is changed, and exports data logger to;
---described data logger, by signal output, and shows;
---described controller, for control simulation signal receiver, digit signal receiver, analog-digital converter, multiplexer,The work of output format converter and data logger.
2. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 1, it is characterized in that:Described picture processing chip also comprises a frequency multiplier, and it is for the frequency of the triggering signal of outside input being increased to doubly processing,Be sent to again master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected with signal format converter and serializer respectively, forUnified integration clock signal;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected with signal format converter and deserializer respectively, forUnified integration clock signal;
Described figure image intensifying chip also comprises a de-noising processor; The viewdata signal that described data sink receives, sendsCarry out noise reduction process to de-noising processor, then be forwarded to image intensifier;
Described video record chip also comprises an image processor, processes for the video that data sink is received, andImage after treatment is sent to video encoder;
Described display driver chip also comprises a Video Decoder, field flyback data processor and memory;
Described Video Decoder, decodes for the analog signal that receiver of the analog signal is received, and is sent to field flyback numberAccording to processor;
Described field flyback data processor, for by capable decoded analog signal data inserting, and be sent to described memory and enterRow storage;
Described memory, for storing the data after field flyback data processor processes, and is sent to output format converter.
3. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 2, it is characterized in that:
The image processor of described picture processing chip also comprises an exposure gain circuitry, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for believing from transmissionIn the distortion in road and noise, recover data;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for believing from transmissionIn the distortion in road and noise, recover data;
Described figure image intensifying chip also comprises a dynamic memory; Described de-noising processor view data after treatment, is first sent toDynamic memory is stored, then is forwarded to image intensifier;
The image processor of described video record chip comprises edge intensifier circuit and the interfered circuit that abates the noise;
Described display driver chip also comprises an image border smoothing processing device, for receiving the signal of restorer, and to video figureThe edge of picture carries out smoothing processing, then is sent to format converter.
4. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 3, it is characterized in that:Described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flickerSituation, and result of detection is sent to exposure gain circuitry;
Described figure image intensifying chip also comprises a pixel self adaptation proofreading equipment; Described image intensifier is first by view data after treatmentBe sent to described pixel self adaptation proofreading equipment, carry out pixel by this pixel self adaptation proofreading equipment and adapt to check and correction, then be sent to numberAccording to follower.
5. the video acquisition intensifier circuit of medical endoscope according to claim 4, is characterized in that: described figure image intensifying chipAlso comprise a vision signal multiplier and a storage signal multiplier; Described clock generator, divides the clock signal of generationBe not sent to vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal be sent toData sink, is sent to dynamic memory and static memory by this storage signal multiplier by clock signal.
6. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 1, it is characterized in that:Described picture processing chip outside is provided with: for receiving the power port of supply voltage, for receiving the signal of picture signalReceiving port, for the video signal port of outputting video signal, for exporting row field signal port, the use of row field signalIn the clock signal port of reception external timing signal, for receiving the data receiver port and of storing data for receivingThe PORT COM of external communication order;
Described first signal conversion chip outside is provided with: for receiving the power port of supply voltage, for receiving bt1120The receiver port of vision signal, for exporting the video signal port of lvds vision signal and for exporting row field signalRow field signal port;
Described secondary signal conversion chip outside is provided with: for receiving the receiver port of lvds vision signal, for defeatedGo out video signal port and the row field signal port of bt1120 vision signal;
Described figure image intensifying chip exterior is provided with: for receiving the power port of supply voltage, for receiving picture signalReceiver port, for the video signal port of outputting video signal, for receiving the clock signal of external timing signalPort and for exporting the row field signal port of row field signal;
Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM;Described video input port is connected with the data sink of this video record chip internal, for receiving outside video data;Described video-out port, is connected with described data logger, for output video data; Described PORT COM, with instituteState processor and connect, for receiving outside serial port command;
Described display driver chip outside is provided with: power port, video reception port and VT mouth;Described video reception port is connected with receiver of the analog signal and the digit signal receiver of display driver chip inside;Described video-out port is connected with the data logger of display driver chip inside.
7. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 6, it is characterized in that:The power port of described picture processing chip is circumscribed with a filter circuit for voltage stabilizing; Described filter circuit comprises an electricitySense and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with electric capacity one end respectively, described inThe other end ground connection of electric capacity; One end access power port that described inductance is connected with electric capacity;
The power port of described video record chip is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at leastAn electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected inBetween magnetic bead and electric capacity;
Described display driver chip power port comprises the power pins of a 1.2V and the power pins of 3.3V; Described 1.2VPin is circumscribed with two electric capacity in parallel, for filtering AC signal; Described 3.3V is circumscribed with 5 shunt capacitances, for mistakeThe AC signal of filter different frequency.
8. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 7, it is characterized in that:The external clock circuit of clock signal port of described picture processing chip, it comprises the clock chip that shakes; The described clock chip that shakesPower end be connected with power supply by a filter circuit, the shake output of chip of this clock passes through a debug circuit and described clockSignal port connects; Described filter circuit is made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply,The other end is connected with electric capacity, and the other end ground connection of this electric capacity; The shake power end of chip of described clock is connected in inductance and electric capacityBetween; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen,The other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port be connected in this resistance and electric capacity itBetween;
The external clock circuit of clock signal port of described figure image intensifying chip, it comprises the clock chip that shakes; Described clock shakesThe power end of chip is connected with power supply by a filter circuit, this clock shake output and the described clock signal port company of chipConnect; Described filter circuit is made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, the other end and electricityHold and connect, and the other end ground connection of this electric capacity.
9. the image of medical endoscope is processed enhancing, video record and display circuit according to claim 8, it is characterized in that:The data receiver port of described picture processing chip is circumscribed with a memory circuitry, and it comprises a memory, be connected to this depositsThe filter circuit of the voltage port of reservoir, and be connected to the resistance of the output port of this memory.
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Denomination of invention: A circuit for image processing, enhancement, video recording and display of medical endoscope Effective date of registration: 20220331 Granted publication date: 20160518 Pledgee: Zengcheng sub branch of Bank of Guangzhou Co.,Ltd. Pledgor: GUANGZHOU SOFTLINK MEDICAL INNOVATION Co. LTO Registration number: Y2022980003649 |
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Denomination of invention: An Image Processing Enhancement, Video Recording, and Display Circuit for Medical Endoscopes Effective date of registration: 20230524 Granted publication date: 20160518 Pledgee: Zengcheng sub branch of Bank of Guangzhou Co.,Ltd. Pledgor: GUANGZHOU SOFTLINK MEDICAL INNOVATION Co. LTO Registration number: Y2023980041627 |