CN205195853U - Video acquisition , transmission and intensifier circuit of medical treatment camera system - Google Patents
Video acquisition , transmission and intensifier circuit of medical treatment camera system Download PDFInfo
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- CN205195853U CN205195853U CN201520726889.1U CN201520726889U CN205195853U CN 205195853 U CN205195853 U CN 205195853U CN 201520726889 U CN201520726889 U CN 201520726889U CN 205195853 U CN205195853 U CN 205195853U
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Abstract
The utility model relates to a video acquisition, transmission and intensifier circuit of medical treatment camera system, sky including setting up above the operating table hangs the formula camera lens, sets up at the dive formula camera lens of implementing surgery location to and be used for the receipt sky to hang the formula camera lens and the video signal's of dive formula camera lens host computer, it is equipped with video capture chip in hanging the formula camera lens, the first signal changes chip and the 2nd signal conversion chip, it video image signal that hangs the collection of formula camera lens is the LVDS signal, video capture chip is used for gathering outside image information to send the first signal conversion chip, the first signal changes the chip, is the BT1120 signal with this LVDS signal conversion to with this BT1120 signal transmission to the 2nd signal conversion chip, the 2nd signal conversion chip is the SDI signal with BT1120 signal conversion to send to the host computer in, inside the 3rd signal conversion chip that is equipped with of host computer for be the BT1120 signal with SDI signal conversion.
Description
Technical field
The utility model relates to a kind of camera system, particularly a kind of video acquisition of medical camera system, transmission and intensifier circuit.
Background technology
When clinical treatment, particularly when doctor is when performing the operation, often needing to carry out carrying out observation surgical procedure by shooting, play in real time and record, can conveniently watch in surgical procedure, also can carry out demonstration lesson by video recording simultaneously.
But existing pick-up lens is single, the limited angle of shooting, is difficult to reduce the scene of whole operation and details.Particularly, at the discreet portions of operation, be difficult to shooting especially.
Therefore, for existing problem, need to provide a kind of can the medical camera system of omnidirectional shooting surgical.
Utility model content
The utility model is that the shortcoming overcoming prior art is with not enough, provides a kind of video acquisition of medical camera system, transmission and intensifier circuit.
The utility model is achieved through the following technical solutions: a kind of video acquisition of medical camera system, transmission and intensifier circuit, comprise and be arranged on sky hanging camera lens above operating table, be arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;
Video capture processor, the first signal conversion chip and secondary signal conversion chip is provided with in described sky hanging camera lens; The video signal of described sky hanging camera lens collection is LVDS signal; Described video capture processor for gathering outside image information, and sends the first signal conversion chip; Described first signal conversion chip, is converted to BT1120 signal by this LVDS signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal;
Be provided with video capture processor in described submersible type camera lens, it for gathering outside image information, and is sent to main frame; The video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for this CVBS signal is converted to BT656 signal.
Compared to prior art, the utility model is by arranging two camera lenses, a sky hanging camera lens simultaneously, a submersible type camera lens, can respectively on and under observe the overall situation surgical procedure, meanwhile, the subtlety of the operation of doctor on operating table can be observed by submersible type camera lens.Meanwhile, by a main frame, the video gathered by two camera lenses carries out merging and plays and record, and is convenient to the viewing in surgical process, also may be used for formality instructional video and uses.
As further improvement of the utility model, described main frame inside is also provided with an image enhaucament chip, for receiving the vision signal of day hanging camera lens and submersible type camera lens, and carries out enhancing process.
As further improvement of the utility model, the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module and output module;
Described control module, it sends triggering signal to driver module for receiving outside triggering signal;
Described driver module, it for receiving the triggering signal of control module, and drives illuminant module work;
Described illuminant module, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampling module, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module by it;
Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
As further improvement of the utility model, described video capture processor also comprises one times of frequency module, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module.
As further improvement of the utility model, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal.
As further improvement of the utility model, described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
Described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
Described data reader, it for receiving LVDS video transfer signal, and is sent to signal format converter;
Described signal format converter, it for LVDS vision signal being converted to the vision signal of BT1120, and is sent to deserializer;
Described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
Described data logger, for exporting BT1120 video signal data.
As further improvement of the utility model, described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;
Described data buffer, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders;
Described low noise phase-locked loop, it is connected with data buffer, stable for holding frequency and phase place;
Described ASI synchronization encoders, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer;
Described serializer, for parallel signal is converted to serial signal, and is sent to serial image scrambler;
Described serial image scrambler, for being encrypted signal data, and is sent to cable driver;
Described cable driver, for being sent to main frame by this sdi signal.
As further improvement of the utility model, described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI sync decoder, data extractor and data buffer;
Described cable equalizer, for receiving sdi signal and carrying out correction process, then is sent to data recoverer;
Described data recoverer, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler;
Described serial image descrambler, for being decrypted by signal data, and is sent to deserializer;
Described deserializer, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder;
Described ASI sync decoder, for decoding data, is converted to BT1120 signal, and is sent to data extractor;
Described data extractor, for decoded data being extracted, and is sent to data buffer;
Described data buffer, for sending the signal of reception.
As further improvement of the utility model, described 4th signal conversion chip comprises: the contrast saturation control circuit of the data amplitude limiter of analog to digital converter, analog controller, many standards, data bypass sampling filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;
Described analog to digital converter, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller;
Described analog controller, for receiving this BT656 digital signal, and is sent to data amplitude limiter, the data bypass sampling filter of many standards simultaneously, and the contrast saturation control circuit of colourity and brightness;
The data amplitude limiter of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device;
Described data bypass sampling filter, for filtering interference signal, and is sent to formatted output device;
The contrast saturation control circuit of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device;
Described synchronous circuit is connected with the contrast saturation control circuit of colourity and brightness and clock generator respectively, for the contrast saturation control circuit of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;
Described formatted output device, for being BT656 by Signal form translate, and exports this signal.
As further improvement of the utility model, described image enhaucament chip internal comprises: data sink, de-noising processor, dynamic memory, image intensifier, pixel self adaptation proofreading equipment, data logger, static memory, controller, vision signal multiplier, storage signal multiplier and clock generator;
Described data sink, it for receiving viewdata signal, and is sent to de-noising processor;
The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to dynamic memory;
After the view data of described dynamic memory after receiving de-noising processor 2 process, then be forwarded to image intensifier;
Described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border, view data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carry out pixel by this pixel self adaptation proofreading equipment and adapt to check and correction, then be sent to data logger;
Described data logger, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator, its for centered by process chip clocking, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
Be divided into multiple functional module further by image enhaucament chip, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is the connection diagram of the video acquisition of medical camera system of the present utility model, transmission and intensifier circuit.
Fig. 2 is the inside chip connection diagram of the video acquisition of medical camera system of the present utility model, transmission and intensifier circuit.
The internal circuit connection diagram of Fig. 3 formula video capture processor.
Fig. 4 is the outside port schematic diagram of video capture processor.
Fig. 5 is the circuit diagram of the power unit of video capture processor.
Fig. 6 is the circuit diagram of the 2.7V of video capture processor.
Fig. 7 is the circuit diagram of the 1.8V of video capture processor.
Fig. 8 is the circuit diagram of the 1.2V of video capture processor.
Fig. 9 is the interface enlarged drawing of video capture processor row field signal.
Figure 10 is the partial enlarged drawing of the reference signal port of video capture processor.
Figure 11 is the circuit diagram of the clock circuit of video capture processor.
Figure 12 is the circuit diagram of the configuration circuit of video capture processor.
Figure 13 is the internal circuit connection diagram of the first signal conversion chip.
Figure 14 is the outside port connection diagram of the first signal conversion chip.
Figure 15 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 16 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 17 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 18 is the internal circuit connection diagram of secondary signal conversion chip.
Figure 19 is the outside port connection diagram of secondary signal conversion chip.
Figure 20 is the partial enlarged drawing of the power port of secondary signal conversion chip.
Figure 21 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 22 is the signal output port partial enlarged drawing of secondary signal conversion chip.
Figure 23 is the partial enlarged drawing of the reseting port of secondary signal conversion chip.
Figure 24 is the internal circuit connection diagram of the 3rd signal conversion chip.
Figure 25 is the outside port connection diagram of the 3rd signal conversion chip.
Figure 26 is the partial enlarged drawing of power port.
Figure 27 is the voltage conversion circuit that 3.3V is converted to 1.2V.
Figure 28 is the partial enlarged drawing of signal input port.
Figure 29 is the partial enlarged drawing of signal output port.
Figure 30 is the internal circuit connection diagram of the 4th signal conversion chip.
Figure 31 is the outside port connection diagram of the 4th signal chip.
Figure 32 is the voltage filtering circuit figure of the 4th signal chip.
Figure 33 is CVBS signal input circuit figure.
Figure 34 is the internal circuit connection diagram of image enhaucament chip.
Figure 35 and Figure 36 is the outside connecting circuit figure of image enhaucament chip respectively.
Figure 37 is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.
Figure 38-39 is the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V respectively.
Figure 40 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 41 is the partial enlarged drawing of the video signal port of image enhaucament chip.
Figure 42 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 43 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is the connection diagram of the video acquisition of medical camera system of the present utility model, transmission and intensifier circuit.The utility model provides a kind of video acquisition of medical camera system, transmission and intensifier circuit, it comprises and is arranged on sky hanging camera lens 1 above operating table, is arranged on the submersible type camera lens 2 implementing surgery location, and for the main frame 3 of the vision signal that receives day hanging camera lens 1 and submersible type camera lens 2.
Concrete, refer to Fig. 2, it is the inside chip connection diagram of the video acquisition of medical camera system of the present utility model, transmission and intensifier circuit.
Be provided with video capture processor 11 in described sky hanging camera lens 1, it for gathering outside image information, and is sent to main frame 3;
Be provided with video capture processor 21 in described submersible type camera lens 2, it for gathering outside image information, and is sent to main frame 3.
Further, in order to reduce the attenuation degree of day hanging camera lens 1 and submersible type camera lens 2 signal in the process of transmission, the stability of inhibit signal transmission.The preferred mode of another kind as the present embodiment, is provided with the first signal conversion chip 13 and secondary signal conversion chip 14 in described sky hanging camera lens; The video signal of described sky hanging camera lens collection 1 is LVDS signal; Described first signal conversion chip 13, this BT1120 signal for this LVDS signal is converted to BT1120 signal, and is sent to secondary signal conversion chip 14 by it; BT1120 signal is converted to sdi signal by described secondary signal conversion chip 14, and is sent in main frame 3; Described main frame 3 inside is provided with the 3rd signal conversion chip 31, for sdi signal is converted to BT1120 signal.
Further, the video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip 32, for this CVBS signal is converted to BT656 signal.
Further in order to strengthen show in main frame time image readability, as the optimal way of the present embodiment, described main frame inside is also provided with an image enhaucament chip 33, for receiving the vision signal of day hanging camera lens 1 and submersible type camera lens 2, and carry out enhancing process, then be sent to video record chip 35 respectively and drive display chip 34.
Further, below the connection of the internal circuit blocks of said chip is described respectively, specific as follows:
Refer to Fig. 3, it is the internal circuit connection diagram of video capture processor.
The video capture processor 11 of hanging camera lens inside, described sky and the video capture processor 21 of submersible type camera lens inside all comprise: control module 111, driver module 112, illuminant module 113, sampling module 114, output module 115 and doubly frequency module 116;
Described control module 111, it sends triggering signal to driver module 112 for receiving outside triggering signal;
Described driver module 112, it is for receiving the triggering signal of control module, and drives illuminant module 113 to work;
Described illuminant module 113, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampling module 114, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module 115 by it;
Described output module 115, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
Described times of frequency module 116, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module 111.
Concrete, refer to Fig. 4, it is the outside port schematic diagram of video capture processor.
Described video capture processor outside is provided with: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.
Please refer to Fig. 5, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.
Please refer to Fig. 6-8, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.
Refer to Fig. 9, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 10, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.
Refer to Figure 11, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 12, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
Refer to Figure 13, it is the internal circuit connection diagram of the first signal conversion chip.
Described first signal conversion chip 13 comprises: controller 131, data reader 132, signal format converter 133, deserializer 134, data logger 135, phase-locked loop 136 and clock data restorer 137;
Described controller 131, it is for receiving outside triggering signal, and the work of control data reader 132, signal format converter 133, deserializer 134 and data logger 135;
Described data reader 132, its LVDS video transfer signal for video capture processor is gathered, and be sent to signal format converter 133;
Described signal format converter 133, it for LVDS vision signal being converted to the vision signal of bt1120, and is sent to deserializer 134;
Described deserializer 134, it is for being converted to parallel data by serial data, and is sent to data logger 135;
Described data logger 135, for exporting bt1120 video signal data.
Described phase-locked loop 136, is connected with signal format converter 133 and deserializer 134 respectively, for unified integration clock signal.
Described clock data restorer 137, it is connected with data reader 132, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 14, it is the outside port connection diagram of the first signal conversion chip.
In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for receive LVDS vision signal receiver port 301, for exporting video signal port 302 and the row field signal port 303 of bt1120 vision signal.
Refer to Figure 15, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 301, it is connected with described data reader 132; Concrete, this receiver port includes 4 pins, for receiving the LVDS vision signal that picture processing chip exports.
Refer to Figure 16, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 302 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.
Refer to Figure 17, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 303 includes a line signal output pin and a field signal output pin; Described row field signal port 303 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 18, it is the internal circuit connection diagram of secondary signal conversion chip.
Described secondary signal conversion chip 14 comprises: data buffer 141, low noise phase-locked loop 142, ASI synchronization encoders 143, serializer 144, serial image scrambler 145, cable driver 146 and end noise phase-locked loop 147;
Described data buffer 141, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders 142;
Described low noise phase-locked loop 142, it is connected with data buffer, stable for holding frequency and phase place;
Described ASI synchronization encoders 143, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer 144;
Described serializer 144, for parallel signal is converted to serial signal, and is sent to serial image scrambler 145;
Described serial image scrambler 145, for being encrypted signal data, and is sent to cable driver 146;
Described cable driver 146, for being sent to main frame 30 by this sdi signal.
Refer to Figure 19, it is the outside port connection diagram of secondary signal conversion chip.
In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for carry out powering for chip power port 401, for receiving the receiver port 402 of the BT1120 signal of the first signal conversion chip,, for exporting the signal output port 403 of sdi signal, and for the reseting port 404 of chip reset.
Please refer to Figure 20, it is the partial enlarged drawing of the power port of secondary signal conversion chip.Described power port 401 comprises the pin of 8 access power supplys, and the power supply wherein accessed is 1.2V.
Please refer to Figure 21, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 402 comprises 20 signal access pins.
Please refer to Figure 22, it is the signal output port partial enlarged drawing of secondary signal conversion chip.Described signal output port 403 is for exporting sdi signal, and this port comprises a reset pin and two output pins.
Please refer to Figure 23, it is the partial enlarged drawing of the reseting port of secondary signal conversion chip.Described reseting port is external passes through a resistance R83 and electric capacity C73 ground connection; Meanwhile, power supply VCC is connected between resistance R83 and electric capacity C73 by a resistance R84.
Refer to Figure 24, it is the internal circuit connection diagram of the 3rd signal conversion chip.
Described 3rd signal conversion chip 31 comprises: cable equalizer 311, data recoverer 312, crystal oscillator 313, serial image descrambler 314, deserializer 315, ASI sync decoder 316, data extractor 317 and data buffer 318;
Described cable equalizer 311, for receiving sdi signal and carrying out correction process, then is sent to data recoverer 312;
Described data recoverer 312, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler 314;
Described crystal oscillator 313, for providing pulse clock signal for data recoverer 312;
Described serial image descrambler 314, for being decrypted by signal data, and is sent to deserializer 315;
Described deserializer 315, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder 316;
Described ASI sync decoder 316, for decoding data, is converted to BT1120 signal, and is sent to data extractor 317;
Described data extractor 317, for decoded data being extracted, and is sent to data buffer 318;
Described data buffer 318, for sending the signal of reception.
Please refer to Figure 25, it is the outside port connection diagram of the 3rd signal conversion chip.
Further, in order to adapt to the application of the 3rd signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 3rd signal conversion chip is provided with: for for chip power supply power port 501, for receive sdi signal signal input port 502, for export BT1120 signal signal output port 503, for receiving the PORT COM 504 of external communication order, and for the clock signal port 505 of receive clock signal; Described clock signal port 505 is circumscribed with a crystal oscillator, for providing clock signal.
Please refer to Figure 26, it is the partial enlarged drawing of power port.Described power port comprises 15 power input pin, and the supply voltage wherein inputted comprises 1.2V and 3.3V two kinds.And in order to realize the conversion of voltage, the present embodiment also provides voltage conversion circuit.Specifically refer to Figure 27, it is converted to the voltage conversion circuit of 1.2V for 3.3V.Described voltage conversion circuit comprises an electric pressure converter; The input of described electric pressure converter is connected with 3.3V voltage; Concrete, the voltage of this 3.3V is connected with the input IN of electric pressure converter by an inductance L 9, and holds at the IN of this inductance and electric pressure converter, by two capacity earths in parallel, to play the effect of filtering.The output OUT of described electric pressure converter exports 1.2V voltage; Concrete, the output voltage of this 1.2V passes through the capacity earth of two parallel connections, to play the effect of filtering.
Refer to Figure 28, it is the partial enlarged drawing of signal input port.Described signal input port 502 is for receiving sdi signal, and this sdi signal carries out impedance matching, to improve through-put power by connecting inductance, electric capacity and resistance.
Refer to Figure 29, it is the partial enlarged drawing of signal output port.Described signal output port 503 is for exporting BT1120 signal, and this signal output port comprises the signal output pin of 20 BT1120, and row field signal output pin.
Refer to Figure 30, it is the internal circuit connection diagram of the 4th signal conversion chip.
Described 4th signal conversion chip 32 comprises: the contrast saturation control circuit 325 of the data amplitude limiter 323 of analog to digital converter 321, analog controller 322, many standards, data bypass sampling filter 324, colourity and brightness, synchronous circuit 326, clock generator 327 and formatted output device 328;
Described analog to digital converter 321, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller 322;
Described analog controller 322, for receiving this BT656 digital signal, and is sent to data amplitude limiter 323, the data bypass sampling filter 324 of many standards simultaneously, and the contrast saturation control circuit 325 of colourity and brightness;
The data amplitude limiter 323 of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device 328;
Described data bypass sampling filter 324, for filtering interference signal, and is sent to formatted output device 328;
The contrast saturation control circuit 325 of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device 328;
Described synchronous circuit 326 is connected with the contrast saturation control circuit 325 of colourity and brightness and clock generator 327 respectively, for the contrast saturation control circuit 325 of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;
Described formatted output device 328, for being BT656 by Signal form translate, and exports this signal.
Please refer to Figure 31, it is the outside port connection diagram of the 4th signal chip.
Further, in order to adapt to the application of the 4th signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 4th signal conversion chip is provided with: for for chip power supply power port 601, for receive CVBS signal signal input port 602, for export BT656 signal signal output port 603, for receiving the PORT COM 604 of external communication order, and for the clock signal port 605 of receive clock signal; Described clock signal port 605 is circumscribed with a crystal oscillator, for providing clock signal.
Please refer to Figure 32, it is the voltage filtering circuit figure of the 4th signal chip.Described voltage signal port is circumscribed with a voltage filtering circuit.The voltage of the .33V inputted accesses the power port of the 4th signal chip by this filter circuit.
Please refer to Figure 33, it is CVBS signal input circuit figure.Described signal input port 603 is for receiving CVBS signal; Described CVBS signal, when inputting, by contact resistance and electric capacity, carries out leading anti-coupling, provides signal power during input.
Refer to Figure 34, it is the internal circuit connection diagram of image enhaucament chip.
Described image enhaucament chip internal comprises: data sink 331, de-noising processor 332, dynamic memory 333, image intensifier 334, pixel self adaptation proofreading equipment 335, data logger 336, static memory 337, controller 338, vision signal multiplier 339, storage signal multiplier 3310 and clock generator 3311.
Described data sink 331, it is for receiving viewdata signal, and is sent to de-noising processor 332;
The viewdata signal that described data sink 331 receives, is sent to de-noising processor 332 and carries out noise reduction process, then be forwarded to dynamic memory 333.
After the view data of described dynamic memory 333 after receiving de-noising processor 2 process, then be forwarded to image intensifier 334.
Described image intensifier 334, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 335 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 336 by this pixel self adaptation proofreading equipment 335.
Described data logger 336, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 337, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 338, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 3311, its for centered by process chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 339 and storage signal multiplier 3310, and by this vision signal multiplier 339, clock signal is sent to data sink, by this storage signal multiplier 3310, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 35 and Figure 36, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 701, for outputting video signal video signal port 702, for receive external timing signal clock signal port 703, for exporting the row field signal port 704 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 37, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 38-39, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 40, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 701 comprises 20 signal pins, is connected with the data sink 331 of inside, for receiving the picture signal of input.
Refer to Figure 41, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 702 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 336.
Refer to Figure 42, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 703, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 43, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 704 comprises a row signal pins and a field signal pin.Described row field signal port 704 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Compared to prior art, the utility model is by arranging two camera lenses, a sky hanging camera lens simultaneously, a submersible type camera lens, can respectively on and under observe the overall situation surgical procedure, meanwhile, the subtlety of the operation of doctor on operating table can be observed by submersible type camera lens.Meanwhile, by a main frame, the video gathered by two camera lenses carries out merging and plays and record, and is convenient to the viewing in surgical process, also may be used for formality instructional video and uses.
Be divided into multiple functional module further by image enhaucament chip, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (10)
1. the video acquisition of a medical camera system, transmission and intensifier circuit, it is characterized in that: comprise and be arranged on sky hanging camera lens above operating table, be arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;
Video capture processor, the first signal conversion chip and secondary signal conversion chip is provided with in described sky hanging camera lens; The video signal of described sky hanging camera lens collection is LVDS signal; Described video capture processor for gathering outside image information, and sends the first signal conversion chip; Described first signal conversion chip, is converted to BT1120 signal by this LVDS signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal;
Be provided with video capture processor in described submersible type camera lens, it for gathering outside image information, and is sent to main frame; The video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for this CVBS signal is converted to BT656 signal.
2. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 1, it is characterized in that: described main frame inside is also provided with an image enhaucament chip, for receiving the vision signal of day hanging camera lens and submersible type camera lens, and carry out enhancing process.
3. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 1, is characterized in that: the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module and output module;
Described control module, it sends triggering signal to driver module for receiving outside triggering signal;
Described driver module, it for receiving the triggering signal of control module, and drives illuminant module work;
Described illuminant module, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampling module, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to by it
Output module;
Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
4. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 3, it is characterized in that: described video capture processor also comprises one times of frequency module, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module.
5. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 4, is characterized in that: described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal.
6. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 1, is characterized in that: described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
Described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
Described data reader, it for receiving LVDS video transfer signal, and is sent to signal format converter;
Described signal format converter, it for LVDS vision signal being converted to the vision signal of BT1120, and is sent to deserializer;
Described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
Described data logger, for exporting BT1120 video signal data.
7. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 6, is characterized in that: described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;
Described data buffer, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders;
Described low noise phase-locked loop, it is connected with data buffer, stable for holding frequency and phase place;
Described ASI synchronization encoders, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer;
Described serializer, for parallel signal is converted to serial signal, and is sent to serial image scrambler;
Described serial image scrambler, for being encrypted signal data, and is sent to cable driver;
Described cable driver, for being sent to main frame by this sdi signal.
8. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 7, is characterized in that: described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI sync decoder, data extractor and data buffer;
Described cable equalizer, for receiving sdi signal and carrying out correction process, then is sent to data recoverer;
Described data recoverer, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler;
Described serial image descrambler, for being decrypted by signal data, and is sent to deserializer;
Described deserializer, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder;
Described ASI sync decoder, for decoding data, is converted to BT1120 signal, and is sent to data extractor;
Described data extractor, for decoded data being extracted, and is sent to data buffer;
Described data buffer, for sending the signal of reception.
9. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 8, is characterized in that: described 4th signal conversion chip comprises: the contrast saturation control circuit of the data amplitude limiter of analog to digital converter, analog controller, many standards, data bypass sampling filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;
Described analog to digital converter, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller;
Described analog controller, for receiving this BT656 digital signal, and is sent to data amplitude limiter, the data bypass sampling filter of many standards simultaneously, and the contrast saturation control circuit of colourity and brightness;
The data amplitude limiter of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device;
Described data bypass sampling filter, for filtering interference signal, and is sent to formatted output device;
The contrast saturation control circuit of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device;
Described synchronous circuit is connected with the contrast saturation control circuit of colourity and brightness and clock generator respectively, for the contrast saturation control circuit of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;
Described formatted output device, for being BT656 by Signal form translate, and exports this signal.
10. the video acquisition of medical camera system, transmission and intensifier circuit according to claim 2, is characterized in that: described image enhaucament chip internal comprises: data sink, de-noising processor, dynamic memory, image intensifier, pixel self adaptation proofreading equipment, data logger, static memory, controller, vision signal multiplier, storage signal multiplier and clock generator;
Described data sink, it for receiving viewdata signal, and is sent to de-noising processor;
The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to dynamic memory;
After the view data of described dynamic memory after receiving de-noising processor 2 process, then be forwarded to image intensifier;
Described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border, view data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carry out pixel by this pixel self adaptation proofreading equipment and adapt to check and correction, then be sent to data logger;
Described data logger, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator, its for centered by process chip clocking, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
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| CN201520726889.1U CN205195853U (en) | 2015-09-18 | 2015-09-18 | Video acquisition , transmission and intensifier circuit of medical treatment camera system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105208331A (en) * | 2015-09-18 | 2015-12-30 | 广东实联医疗器械有限公司 | Video capturing, transmitting and enhancing circuit for medical camera system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105208331A (en) * | 2015-09-18 | 2015-12-30 | 广东实联医疗器械有限公司 | Video capturing, transmitting and enhancing circuit for medical camera system |
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