CN105208256A - Medical double-camera shooting system - Google Patents

Abstract

The invention relates to a medical double-camera shooting system which comprises a medical camera system and a camera shooting tripod head control system, wherein the medical camera system comprises a suspended lens arranged above an operating table, a submersible lens arranged at an operation applying position, and a main unit used for receiving video signals of the suspended lens and the submersible lens; the camera shooting tripod head control system comprises an operation platform used for sending control signals and a universal tripod head used for receiving signals; the operation platform is used for receiving operating orders of a user, and sending the operating orders to the universal tripod head. Compared with the prior art, as the system comprises the two lenses, namely the suspended lens and the submersible lens, the user can see the whole operation process from the top down, while a tiny operation point of a doctor on the operating table during the operation can be seen through the submersible lens; the shooting angle of the suspended lens can be adjusted by adjusting the shooting direction of the suspended lens.

Description

The two camera system of a kind of medical treatment

Technical field

The present invention relates to a kind of camera system, especially for two camera systems of medical treatment.

Background technology

When clinical treatment, particularly when doctor is when performing the operation, often needing to carry out carrying out observation surgical procedure by shooting, play in real time and record, can conveniently watch in surgical procedure, also can carry out demonstration lesson by video recording simultaneously.

But existing pick-up lens is single, the limited angle of shooting, is difficult to reduce the scene of whole operation and details.Particularly, at the discreet portions of operation, be difficult to shooting especially.

Therefore, for existing problem, need to provide a kind of can the medical camera system of omnidirectional shooting surgical.

Summary of the invention

The invention reside in the shortcoming that overcomes prior art with not enough, provide a kind of can the two camera system of medical treatment of omnidirectional shooting surgical scene.

The present invention is achieved through the following technical solutions: the two camera system of a kind of medical treatment, and it comprises medical camera system and camera cradle head control system;

Described medical camera system comprises and is arranged on sky hanging camera lens above operating table, is arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;

Described camera cradle head control system comprises the operating platform for transmitting control signal and the universal turning bench for Received signal strength; Described operating platform for receiving the operational order of user, and is sent to universal turning bench;

Described control The Cloud Terrace comprises:

Support portion is installed;

Vertical rotating part, its inside is provided with the first stepping motor and by this first stepper motor driven vertical swing pinion, described vertical rotating part is connected with installation support portion by vertical swing pinion;

Transverse rotation portion, it is fixedly mounted on vertical rotating part, and described transverse rotation portion has transverse circular shell, is provided with the second stepping motor and by this second stepper motor driven transverse rotation gear in this transverse circular shell;

Longitudinal rotating part, it is arranged on transverse rotation gear by a right angle supporting bracket, is provided with the 3rd stepping motor and by the 3rd stepper motor driven longitudinal swing pinion in described longitudinal rotating part;

Camera assembly, it is arranged on described longitudinal swing pinion, and described sky hanging camera lens is arranged in described camera assembly; And,

Motor-drive circuit, for the operational order of outside, controls the work of described three stepping motors after row relax of going forward side by side, to control the rotation of described sky hanging camera lens.

Compared to prior art, the present invention is by arranging two camera lenses, a sky hanging camera lens simultaneously, a submersible type camera lens, can respectively on and under observe the overall situation surgical procedure, meanwhile, the subtlety of the operation of doctor on operating table can be observed by submersible type camera lens.

As a further improvement on the present invention, video capture processor and picture processing chip is provided with in described sky hanging camera lens; Described video capture processor is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Video capture processor and picture processing chip is provided with in described submersible type camera lens; Described picture processing chip is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Described main frame inside is provided with and drives display chip and video record chip; Described driving display chip, carries out broadcasting display for the video information of sky hanging camera lens collection that will receive and the video information of submersible type camera lens collection; Described video record chip, preserves for the video information of sky hanging camera lens collection and the video information of submersible type camera lens collection being carried out recording.

As a further improvement on the present invention, the first signal conversion chip and secondary signal conversion chip is provided with in described sky hanging camera lens; The video signal of described sky hanging camera lens collection is LVDS signal; Described first signal conversion chip, it is connected with picture processing chip, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal.

As a further improvement on the present invention, the video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for this CVBS signal is converted to BT656 signal.

As a further improvement on the present invention, described main frame inside is also provided with an image enhaucament chip, for receiving the vision signal of day hanging camera lens and submersible type camera lens, and carries out enhancing process, then is sent to video record chip respectively and drives display chip.

As a further improvement on the present invention, the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module and output module;

Described control module, it sends triggering signal to driver module for receiving outside triggering signal;

Described driver module, it for receiving the triggering signal of control module, and drives illuminant module work;

Described illuminant module, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;

Described sampling module, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module by it;

Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.

As a further improvement on the present invention, described video capture processor also comprises one times of frequency module, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module.

As a further improvement on the present invention, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal.

As a further improvement on the present invention, the picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink, master controller, image processor and data logger;

Described data sink, it is for receiving outside view data;

Described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;

Described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;

Described data logger, it is for exporting the view data after process.

As a further improvement on the present invention, described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller.

As a further improvement on the present invention, described image processor also comprises an exposure gain circuit, for increasing exposure gain size.

As a further improvement on the present invention, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.

As a further improvement on the present invention, described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving.

As a further improvement on the present invention, the video record chip of described main frame inside comprises: data sink, video encoder, Video Decoder, data logger and processor;

Described data sink, for receiving outside vision signal, and is sent to video encoder;

Described video encoder, for recording encoding video signal;

Described Video Decoder, for decoding video signal playback;

Described data logger, for exporting vision signal;

Described processor, for the work of control data receiver, video encoder, Video Decoder and data logger.

As a further improvement on the present invention, described video record chip also comprises an image processor, processes for the video received data sink, and the image after process is sent to video encoder.

As a further improvement on the present invention, described image processor comprises edge intensifier circuit and the interfered circuit that abates the noise.

As a further improvement on the present invention, described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video input port is connected with the data sink of this center processing chip internal, for receiving outside video data; Described video-out port, is connected with described data logger, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.

As a further improvement on the present invention, the driving display chip of described main frame inside comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger and controller;

Described receiver of the analog signal, for receiving analog signal, and is sent to analog to digital converter;

Described analog to digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;

Described data signal receiver, for receiving data-signal, and is sent to multiplexer;

Described multiplexer, for being integrated by two paths of signals, line output of going forward side by side is to output format transducer;

Described output format transducer, for signal format being changed, and exports data logger to;

Described data logger, exports signal, and shows;

Described controller, for the work of control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and data logger.

As a further improvement on the present invention, described driving display chip also comprises a Video Decoder, field flyback data processor and memory;

Described Video Decoder, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor;

Described field flyback data processor, for by capable for decoded analog signal data inserting, and be sent to described memory and store;

Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer.

As a further improvement on the present invention, described driving display chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter.

As a further improvement on the present invention, described data logger carries out color output and the output of LVDS vision signal simultaneously.

As a further improvement on the present invention, the outside of described driving display chip is provided with: power port, video reception port and VT mouth; Receiver of the analog signal and the data signal receiver of described video reception port and center processing chip internal are connected; Described video-out port is connected with the data logger of center processing chip internal.

As a further improvement on the present invention, described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;

Described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;

Described data reader, it for receiving LVDS video transfer signal, and is sent to signal format converter;

Described signal format converter, it for LVDS vision signal being converted to the vision signal of BT1120, and is sent to deserializer;

Described deserializer, it for serial data is converted to parallel data, and is sent to data logger;

Described data logger, for exporting BT1120 video signal data.

As a further improvement on the present invention, described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;

Described data buffer, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders;

Described low noise phase-locked loop, it is connected with data buffer, stable for holding frequency and phase place;

Described ASI synchronization encoders, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer;

Described serializer, for parallel signal is converted to serial signal, and is sent to serial image scrambler;

Described serial image scrambler, for being encrypted signal data, and is sent to cable driver;

Described cable driver, for being sent to main frame by this sdi signal.

As a further improvement on the present invention, described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI sync decoder, data extractor and data buffer;

Described cable equalizer, for receiving sdi signal and carrying out correction process, then is sent to data recoverer;

Described data recoverer, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler;

Described serial image descrambler, for being decrypted by signal data, and is sent to deserializer;

Described deserializer, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder;

Described ASI sync decoder, for decoding data, is converted to BT1120 signal, and is sent to data extractor;

Described data extractor, for decoded data being extracted, and is sent to data buffer;

Described data buffer, for sending the signal of reception.

As a further improvement on the present invention, described 4th signal conversion chip comprises: the contrast saturation control circuit of the data amplitude limiter of analog to digital converter, analog controller, many standards, data bypass sampling filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;

Described analog to digital converter, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller;

Described analog controller, for receiving this BT656 digital signal, and is sent to data amplitude limiter, the data bypass sampling filter of many standards simultaneously, and the contrast saturation control circuit of colourity and brightness;

The data amplitude limiter of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device;

Described data bypass sampling filter, for filtering interference signal, and is sent to formatted output device;

The contrast saturation control circuit of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device;

Described synchronous circuit is connected with the contrast saturation control circuit of colourity and brightness and clock generator respectively, for the contrast saturation control circuit of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;

Described formatted output device, for being BT656 by Signal form translate, and exports this signal.

As a further improvement on the present invention, described operating platform comprises command input device and instruction handling circuit;

This instruction for receiving the operational order of user, and is sent to instruction handling circuit by described command input device; Described instruction handling circuit, for receiving described operational order, after processing, occurs to universal turning bench.

As a further improvement on the present invention, described instruction handling circuit comprises control chip; Described control chip outside is provided with: for receive external power source power supply receiving port, for receive instruction command reception port, for the signal output port of output order, for receiving the clock signal port of external timing signal and the configured port for receiving configuration signal; Described command reception port is connected with described command input device, for receiving operational order, after control chip internal processor processes, by described signal output port by command to universal turning bench.

As a further improvement on the present invention, the power port of described control chip is connected to a filter circuit, and external voltage is by the power port of this filter circuit access control chip; Described filter circuit comprises inductance and the electric capacity of series connection; One end of described inductance connects external voltage, and the other end is by this capacity earth, and the access of described power port is between this inductance and electric capacity.

As a further improvement on the present invention, there is a crystal oscillating circuit described clock signal port outside; Described crystal oscillating circuit is used for providing clock signal for control chip.

As a further improvement on the present invention, described command input equipment comprises keyboard and rocking bar; The signal input port of described control chip comprises keyboard signal receiving port and rocking bar receiver port;

Being provided with circuits for triggering in described keyboard, for receiving the operation of user, sending the keyboard signal receiving port of triggering command to control chip; Being provided with circuits for triggering in described rocking bar, for receiving the operation of user, sending the rocking bar receiver port of triggering command to control chip.

As a further improvement on the present invention, described keyboard circuits for triggering comprise 12 trigger buttons; Described trigger button arranges according to 4 row 3 row modes, and described line triggering signal is followed successively by: BD1, BD2, BD3 and BD4; Described row triggering signal is followed successively by: BD5, BD6 and BD7; When pressing described trigger button, trigger rows triggering signal and row triggering signal simultaneously, to distinguish different trigger buttons.

As a further improvement on the present invention, described rocking bar circuits for triggering comprise three road output ports, are respectively used to the control command in output three directions.

As a further improvement on the present invention, the external AT24C02 chip of signal configures port of described control chip, serial data pin SDA and the serial clock pin SCL of this chip access in the configured port of control chip respectively; Pin A0, A1 and A2 ground connection respectively of the address date selection of this chip.

As a further improvement on the present invention, described command reception circuit also comprises a signal conversion chip; Described signal conversion chip, for receiving the instruction output signal of control chip, and is converted to RS485 signal, and transfers to universal turning bench.

As a further improvement on the present invention, the motor-drive circuit of described universal turning bench comprises communication chip, single-chip microcomputer, the first modulus conversion chip, the second modulus conversion chip, the first motor drive ic, the second motor drive ic and the 3rd motor drive ic;

Described communication chip, for the operational order that Received signal strength conversion chip sends, and is sent to single-chip microcomputer after carrying out signal transacting;

Described single-chip microcomputer, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip and the second modulus conversion chip respectively;

The digital signal that this monolithic exports is converted to analog signal by described first modulus conversion chip and the second modulus conversion chip, and is sent to the first motor drive ic, the second motor drive ic and the 3rd motor drive ic respectively;

After described first motor drive ic, the second motor drive ic and the 3rd motor drive ic receive the control signal of the first modulus conversion chip and the second modulus conversion chip, the work of respective drive stepping motor.

As a further improvement on the present invention, described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the signal transmission of Received signal strength conversion chip, and are exported by described receiver input.

As a further improvement on the present invention, described single-chip microcomputer comprises power end, signal input part, signal output part, reset terminal, external memory storage receiving terminal and earth terminal; Described signal input part is for receiving the output signal of communication chip; Described signal output part, exports point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip.

As a further improvement on the present invention, described first modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to analog signal and is sent to the first motor drive ic and the second motor drive ic;

Described second modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to analog signal and is sent to the second motor drive ic and the 3rd motor drive ic.

As a further improvement on the present invention, described first motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip, and passes through this signal output part output drive signal to the first stepping motor;

Described second motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part output drive signal to the second stepping motor;

Described 3rd motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepping motor.

In order to understand better and implement, describe the present invention in detail below in conjunction with accompanying drawing.

Accompanying drawing explanation

Fig. 1 is the connection diagram of medical camera system of the present invention.

Fig. 2 is the inside chip connection diagram of medical camera system of the present invention.

The internal circuit connection diagram of Fig. 3 formula video capture processor.

Fig. 4 is the outside port schematic diagram of video capture processor.

Fig. 5 is the circuit diagram of the power unit of video capture processor.

Fig. 6 is the circuit diagram of the 2.7V of video capture processor.

Fig. 7 is the circuit diagram of the 1.8V of video capture processor.

Fig. 8 is the circuit diagram of the 1.2V of video capture processor.

Fig. 9 is the interface enlarged drawing of video capture processor row field signal.

Figure 10 is the partial enlarged drawing of the reference signal port of video capture processor.

Figure 11 is the circuit diagram of the clock circuit of video capture processor.

Figure 12 is the circuit diagram of the configuration circuit of video capture processor.

Figure 13 is the internal circuit connection diagram of picture processing chip of the present invention.

Figure 14 is the circuit module schematic diagram of image processor of the present invention.

The voltage segment port circuit figure of Figure 15 picture processing chip.

Figure 16 is picture processing chip outside port circuit diagram.

Figure 17-19 is the power supply of picture processing chip is respectively the circuit diagram of 3.3V, 1.8V and 1.2V.

Figure 20 is the partial enlarged drawing of the receiver port of picture processing chip.

Figure 21 is the partial enlarged drawing of the video signal port of picture processing chip.

Figure 22 is the partial enlarged drawing of the row field signal port of picture processing chip.

Figure 23 is the schematic diagram of the clock circuit of picture processing chip.

Figure 24 is the schematic diagram of the memory circuit of picture processing chip.

Figure 25 is the partial enlarged drawing of the PORT COM of picture processing chip.

Figure 26 is the internal circuit connection diagram of the first signal conversion chip.

Figure 27 is the outside port connection diagram of the first signal conversion chip.

Figure 28 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.

Figure 29 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.

Figure 30 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.

Figure 31 is the internal circuit connection diagram of secondary signal conversion chip.

Figure 32 is the outside port connection diagram of secondary signal conversion chip.

Figure 33 is the partial enlarged drawing of the power port of secondary signal conversion chip.

Figure 34 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.

Figure 35 is the signal output port partial enlarged drawing of secondary signal conversion chip.

Figure 36 is the partial enlarged drawing of the reseting port of secondary signal conversion chip.

Figure 37 is the internal circuit connection diagram of the 3rd signal conversion chip.

Figure 38 is the outside port connection diagram of the 3rd signal conversion chip.

Figure 39 is the partial enlarged drawing of power port.

Figure 40 is the voltage conversion circuit that 3.3V is converted to 1.2V.

Figure 41 is the partial enlarged drawing of signal input port.

Figure 42 is the partial enlarged drawing of signal output port.

Figure 43 is the internal circuit connection diagram of the 4th signal conversion chip.

Figure 44 is the outside port connection diagram of the 4th signal chip.

Figure 45 is the voltage filtering circuit figure of the 4th signal chip.

Figure 46 is CVBS signal input circuit figure.

Figure 47 is the internal circuit connection diagram of image enhaucament chip.

Figure 48 and Figure 49 is the outside connecting circuit figure of image enhaucament chip respectively.

Figure 50 is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.

Figure 51-52 is the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V respectively.

Figure 53 is the partial enlarged drawing of the receiver port of image enhaucament chip.

Figure 54 is the partial enlarged drawing of the video signal port of image enhaucament chip.

Figure 55 is the circuit diagram of the clock circuit of image enhaucament chip.

Figure 56 is the partial enlarged drawing of the row field signal port of image enhaucament chip.

Figure 57 is the internal circuit connection diagram driving display chip.

Figure 58-59 drives the signal input of display chip and signal to export schematic diagram.

Figure 60 is the partial enlarged drawing of the power port driving display chip.

Figure 61 is the partial enlarged drawing of the video input port driving display chip.

Figure 62 is the partial enlarged drawing of the video-out port driving display chip.

Figure 63 is the internal circuit connection diagram of video record chip.

Figure 64-66 is outside port connection diagrams of video record chip.

Figure 67 is the partial enlarged drawing of power port.

Figure 68 is the partial enlarged drawing of PORT COM.

Figure 69 is the model calling schematic diagram of remote control universal turning bench control system.

Figure 70 is the external interface circuit figure of control chip.

Figure 71 is the partial enlarged drawing of the power port of control chip.

Figure 72 is the circuit diagram of 3.3V voltage.

Figure 73 is the partial enlarged drawing of keyboard signal receiving port.

Figure 74 is the circuits for triggering figure of keyboard.

Figure 75 is rocking bar triggering signal receiving port.

Figure 76 is rocking bar circuit diagram.

Figure 77 is the circuit diagram of the AT24C02 chip of control chip.

Figure 78 is the circuit diagram of the signal conversion chip of signal conversion chip.

Figure 79 is medical shooting universal turning bench device overall structure stereogram of the present invention.

Figure 80 is the critical piece exploded view of medical shooting universal turning bench device of the present invention.

Figure 81 is the explosive view of medical shooting universal turning bench device of the present invention.

Figure 82 is the circuit diagram of communication chip.

Figure 83 is the circuit diagram of single-chip microcomputer.

Figure 84 is the circuit diagram of storage circuit.

Figure 85 is the circuit diagram of the first modulus conversion chip.

Figure 86 is the circuit diagram of reference voltage.

Figure 87 is the circuit diagram of the second modulus conversion chip.

Figure 88 is the circuit diagram of reference voltage.

Figure 89 is the circuit diagram of the first motor drive ic.

Figure 90 is the circuit diagram of voltage conversion circuit.

Figure 91 is the circuit diagram of filter circuit.

Figure 92 is the partial enlarged drawing of the signal input port of the first motor drive ic

Figure 93 is signal annexation figure.

Figure 94 is the circuit diagram of the signal input of the first electric machine spacing switch.

Figure 95 is the circuit diagram of the second motor drive ic.

Figure 96 is the partial enlarged drawing of the signal input port of the second motor drive ic.

Figure 97 is the circuit diagram of the signal input of the second electric machine spacing switch.

Figure 98 is the circuit diagram of the 3rd motor drive ic.

Figure 99 is the partial enlarged drawing of the signal output port of the 3rd motor drive ic.

Figure 100 is the circuit diagram of the signal input of the second electric machine spacing switch.

Embodiment

For in existing medical practice to doctor implement in surgical procedure cannot the multi-angle technological deficiency of taking, the invention provides the two camera system of a kind of medical treatment.

Present invention also offers the two camera system of a medical treatment, to realize the two image capture method of above-mentioned medical treatment.Below, the two camera system of medical treatment of the present invention is described in detail.

The two camera system of described medical treatment comprises medical camera system and camera cradle head control system.Described medical camera system, for taking the picture of doctor in surgical procedure, and carries out recording and playing; Described camera cradle head control system, for controlling the rotation direction of the pick-up lens of medical camera system, thus adjusts shooting angle and the house of medical camera system.Below, respectively these two systems are described in detail.

Refer to Fig. 1, it is the connection diagram of medical camera system of the present invention.The invention provides a kind of medical camera system, it comprises and is arranged on sky hanging camera lens 1 above operating table, is arranged on the submersible type camera lens 2 implementing surgery location, and for the main frame 3 of the vision signal that receives day hanging camera lens 1 and submersible type camera lens 2.

Concrete, refer to Fig. 2, it is the inside chip connection diagram of the two camera system of medical treatment of the present invention.

Video capture processor 11 and picture processing chip 12 is provided with in described sky hanging camera lens 1; Described video capture processor is for gathering outside image information, and described picture processing chip 12 for this image information being processed, and is sent to main frame 3;

Video capture processor 21 and picture processing chip 22 is provided with in described submersible type camera lens; Described picture processing chip 21 is for gathering outside image information, and described picture processing chip 22 for this image information being processed, and is sent to main frame 3;

Described main frame 3 inside is provided with and drives display chip 34 and video record chip 35; Described driving display chip 34, the video information gathered for the video information that gathered by the sky received hanging camera lens 1 and submersible type camera lens 2 carries out broadcasting display; Described video record chip 35, the video information gathered for the video information that gathered by sky hanging camera lens 1 and submersible type camera lens 2 is carried out recording and is preserved.

Further, in order to reduce the attenuation degree of day hanging camera lens 1 and submersible type camera lens 2 signal in the process of transmission, the stability of inhibit signal transmission.The preferred mode of another kind as the present embodiment, is provided with the first signal conversion chip 13 and secondary signal conversion chip 14 in described sky hanging camera lens; The video signal of described sky hanging camera lens collection 1 is LVDS signal; Described first signal conversion chip 13, it is connected with picture processing chip 12, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip 14; BT1120 signal is converted to sdi signal by described secondary signal conversion chip 14, and is sent in main frame 3; Described main frame 3 inside is provided with the 3rd signal conversion chip 31, for sdi signal is converted to BT1120 signal.

Further, the video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip 32, for this CVBS signal is converted to BT656 signal.

Further in order to strengthen show in main frame time image readability, as the optimal way of the present embodiment, described main frame inside is also provided with an image enhaucament chip 33, for receiving the vision signal of day hanging camera lens 1 and submersible type camera lens 2, and carry out enhancing process, then be sent to video record chip 35 respectively and drive display chip 34.

Further, below the connection of the internal circuit blocks of said chip is described respectively, specific as follows:

Refer to Fig. 3, it is the internal circuit connection diagram of video capture processor.

The video capture processor 11 of hanging camera lens inside, described sky and the video capture processor 21 of submersible type camera lens inside all comprise: control module 111, driver module 112, illuminant module 113, sampling module 114, output module 115 and doubly frequency module 116;

Described control module 111, it sends triggering signal to driver module 112 for receiving outside triggering signal;

Described driver module 112, it is for receiving the triggering signal of control module, and drives illuminant module 113 to work;

Described illuminant module 113, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;

Described sampling module 114, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module 115 by it;

Described output module 115, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.

Described times of frequency module 116, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module 111.

Concrete, refer to Fig. 4, it is the outside port schematic diagram of video capture processor.

Described video capture processor outside is provided with: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.

Please refer to Fig. 5, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.

Please refer to Fig. 6-8, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.

Refer to Fig. 9, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 10, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.

Refer to Figure 11, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.

Refer to Figure 12, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.

Refer to Figure 13, it is the internal circuit connection diagram of picture processing chip of the present invention.

The picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink 121, master controller 122, image processor 123 and data logger 124;

Described data sink 121, it is for receiving outside view data;

Described master controller 122, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;

Described image processor 123, it is for processing image;

Described data logger 124, it is for exporting the view data after process.

Further, described picture processing chip also comprises a frequency multiplier 125, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 122.

Refer to Figure 14, it is the circuit module schematic diagram of image processor of the present invention.

Concrete, described image processor 123 comprises a Lens Shading Compensation circuit 1231, optical detection circuit 1232, flash detection circuit 1233, exposure gain circuit 1234 and white balance permanent circuit 1235.

Described Lens Shading Compensation circuit 1231, it compensates process for the shade produced by camera lens.

Described optical detection circuit 1232 and flash detection circuit 1233, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.

Described exposure gain circuit 1234, for increasing exposure gain size.

Described white balance permanent circuit 1235, it, for according to the parameter preset, carries out the fixed adjustment of white balance.

Please refer to Figure 15 and Figure 16, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip.In addition, in order to the application in order to adapt to this video capture processor, be provided with in described video capture processor outside further: for receive supply power voltage power port 201, for receive picture signal receiver port 202, for outputting video signal video signal port 203, for export row field signal row field signal port 204, for receive external timing signal clock signal port 205, for receive store data data receiver port 206 and one for receiving the PORT COM 207 of external communication order.

Refer to Figure 17-19, its power supply being respectively picture processing chip is the circuit diagram of 3.3V, 1.8V and 1.2V.Further, described power port 201 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of video capture processor of the present invention comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.

Refer to Figure 20, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 202 comprises 8 pins, for receiving outside video signal.

Refer to Figure 21, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 203 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.

Refer to Figure 22, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port 204 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 23, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 205, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.

Refer to Figure 24, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 206 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.

Refer to Figure 25, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 207, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.

Refer to Figure 26, it is the internal circuit connection diagram of the first signal conversion chip.

Described first signal conversion chip 13 comprises: controller 131, data reader 132, signal format converter 133, deserializer 134, data logger 135, phase-locked loop 136 and clock data restorer 137;

Described controller 131, it is for receiving outside triggering signal, and the work of control data reader 132, signal format converter 133, deserializer 134 and data logger 135;

Described data reader 132, its LVDS video transfer signal for video capture processor is gathered, and be sent to signal format converter 133;

Described signal format converter 133, it for LVDS vision signal being converted to the vision signal of bt1120, and is sent to deserializer 134;

Described deserializer 134, it is for being converted to parallel data by serial data, and is sent to data logger 135;

Described data logger 135, for exporting bt1120 video signal data.

Described phase-locked loop 136, is connected with signal format converter 133 and deserializer 134 respectively, for unified integration clock signal.

Described clock data restorer 137, it is connected with data reader 132, for recovering data from the distortion and noise of transmission channel.

Refer to Figure 27, it is the outside port connection diagram of the first signal conversion chip.

In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for receive LVDS vision signal receiver port 301, for exporting video signal port 302 and the row field signal port 303 of bt1120 vision signal.

Refer to Figure 28, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 301, it is connected with described data reader 132; Concrete, this receiver port includes 4 pins, for receiving the LVDS vision signal that picture processing chip exports.

Refer to Figure 29, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 302 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.

Refer to Figure 30, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 303 includes a line signal output pin and a field signal output pin; Described row field signal port 303 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 31, it is the internal circuit connection diagram of secondary signal conversion chip.

Described secondary signal conversion chip 14 comprises: data buffer 141, low noise phase-locked loop 142, ASI synchronization encoders 143, serializer 144, serial image scrambler 145, cable driver 146 and end noise phase-locked loop 147;

Described data buffer 141, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders 142;

Described low noise phase-locked loop 142, it is connected with data buffer, stable for holding frequency and phase place;

Described ASI synchronization encoders 143, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer 144;

Described serializer 144, for parallel signal is converted to serial signal, and is sent to serial image scrambler 145;

Described serial image scrambler 145, for being encrypted signal data, and is sent to cable driver 146;

Described cable driver 146, for being sent to main frame 30 by this sdi signal.

Refer to Figure 32, it is the outside port connection diagram of secondary signal conversion chip.

In addition, in order to the application in order to adapt to this first signal conversion chip, be provided with in described signal conversion chip outside further: for carry out powering for chip power port 401, for receiving the receiver port 402 of the BT1120 signal of the first signal conversion chip,, for exporting the signal output port 403 of sdi signal, and for the reseting port 404 of chip reset.

Please refer to Figure 33, it is the partial enlarged drawing of the power port of secondary signal conversion chip.Described power port 401 comprises the pin of 8 access power supplys, and the power supply wherein accessed is 1.2V.

Please refer to Figure 34, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 402 comprises 20 signal access pins.

Please refer to Figure 35, it is the signal output port partial enlarged drawing of secondary signal conversion chip.Described signal output port 403 is for exporting sdi signal, and this port comprises a reset pin and two output pins.

Please refer to Figure 36, it is the partial enlarged drawing of the reseting port of secondary signal conversion chip.Described reseting port is external passes through a resistance R83 and electric capacity C73 ground connection; Meanwhile, power supply VCC is connected between resistance R83 and electric capacity C73 by a resistance R84.

Refer to Figure 37, it is the internal circuit connection diagram of the 3rd signal conversion chip.

Described 3rd signal conversion chip 31 comprises: cable equalizer 311, data recoverer 312, crystal oscillator 313, serial image descrambler 314, deserializer 315, ASI sync decoder 316, data extractor 317 and data buffer 318;

Described cable equalizer 311, for receiving sdi signal and carrying out correction process, then is sent to data recoverer 312;

Described data recoverer 312, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler 314;

Described crystal oscillator 313, for providing pulse clock signal for data recoverer 312;

Described serial image descrambler 314, for being decrypted by signal data, and is sent to deserializer 315;

Described deserializer 315, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder 316;

Described ASI sync decoder 316, for decoding data, is converted to BT1120 signal, and is sent to data extractor 317;

Described data extractor 317, for decoded data being extracted, and is sent to data buffer 318;

Described data buffer 318, for sending the signal of reception.

Please refer to Figure 38, it is the outside port connection diagram of the 3rd signal conversion chip.

Further, in order to adapt to the application of the 3rd signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 3rd signal conversion chip is provided with: for for chip power supply power port 501, for receive sdi signal signal input port 502, for export BT1120 signal signal output port 503, for receiving the PORT COM 504 of external communication order, and for the clock signal port 505 of receive clock signal; Described clock signal port 505 is circumscribed with a crystal oscillator, for providing clock signal.

Please refer to Figure 39, it is the partial enlarged drawing of power port.Described power port comprises 15 power input pin, and the supply voltage wherein inputted comprises 1.2V and 3.3V two kinds.And in order to realize the conversion of voltage, the present embodiment also provides voltage conversion circuit.Specifically refer to Figure 40, it is converted to the voltage conversion circuit of 1.2V for 3.3V.Described voltage conversion circuit comprises an electric pressure converter; The input of described electric pressure converter is connected with 3.3V voltage; Concrete, the voltage of this 3.3V is connected with the input IN of electric pressure converter by an inductance L 9, and holds at the IN of this inductance and electric pressure converter, by two capacity earths in parallel, to play the effect of filtering.The output OUT of described electric pressure converter exports 1.2V voltage; Concrete, the output voltage of this 1.2V passes through the capacity earth of two parallel connections, to play the effect of filtering.

Refer to Figure 41, it is the partial enlarged drawing of signal input port.Described signal input port 502 is for receiving sdi signal, and this sdi signal carries out impedance matching, to improve through-put power by connecting inductance, electric capacity and resistance.

Refer to Figure 42, it is the partial enlarged drawing of signal output port.Described signal output port 503 is for exporting BT1120 signal, and this signal output port comprises the signal output pin of 20 BT1120, and row field signal output pin.

Refer to Figure 43, it is the internal circuit connection diagram of the 4th signal conversion chip.

Described 4th signal conversion chip 32 comprises: the contrast saturation control circuit 325 of the data amplitude limiter 323 of analog to digital converter 321, analog controller 322, many standards, data bypass sampling filter 324, colourity and brightness, synchronous circuit 326, clock generator 327 and formatted output device 328;

Described analog to digital converter 321, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller 322;

Described analog controller 322, for receiving this BT656 digital signal, and is sent to data amplitude limiter 323, the data bypass sampling filter 324 of many standards simultaneously, and the contrast saturation control circuit 325 of colourity and brightness;

The data amplitude limiter 323 of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device 328;

Described data bypass sampling filter 324, for filtering interference signal, and is sent to formatted output device 328;

The contrast saturation control circuit 325 of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device 328;

Described synchronous circuit 326 is connected with the contrast saturation control circuit 325 of colourity and brightness and clock generator 327 respectively, for the contrast saturation control circuit 325 of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;

Described formatted output device 328, for being BT656 by Signal form translate, and exports this signal.

Please refer to Figure 44, it is the outside port connection diagram of the 4th signal chip.

Further, in order to adapt to the application of the 4th signal conversion chip, the outside port for this chip is now needed to be configured, concrete, the outside of described 4th signal conversion chip is provided with: for for chip power supply power port 601, for receive CVBS signal signal input port 602, for export BT656 signal signal output port 603, for receiving the PORT COM 604 of external communication order, and for the clock signal port 605 of receive clock signal; Described clock signal port 605 is circumscribed with a crystal oscillator, for providing clock signal.

Please refer to Figure 45, it is the voltage filtering circuit figure of the 4th signal chip.Described voltage signal port is circumscribed with a voltage filtering circuit.The voltage of the .33V inputted accesses the power port of the 4th signal chip by this filter circuit.

Please refer to Figure 46, it is CVBS signal input circuit figure.Described signal input port 603 is for receiving CVBS signal; Described CVBS signal, when inputting, by contact resistance and electric capacity, carries out leading anti-coupling, provides signal power during input.

Refer to Figure 47, it is the internal circuit connection diagram of image enhaucament chip.

Described image enhaucament chip internal comprises: data sink 331, de-noising processor 332, dynamic memory 333, image intensifier 334, pixel self adaptation proofreading equipment 335, data logger 336, static memory 337, controller 338, vision signal multiplier 339, storage signal multiplier 3310 and clock generator 3311.

Described data sink 331, it is for receiving viewdata signal, and is sent to de-noising processor 332;

The viewdata signal that described data sink 331 receives, is sent to de-noising processor 332 and carries out noise reduction process, then be forwarded to dynamic memory 333.

After the view data of described dynamic memory 333 after receiving de-noising processor 2 process, then be forwarded to image intensifier 334.

Described image intensifier 334, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 335 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 336 by this pixel self adaptation proofreading equipment 335.

Described data logger 336, it for receiving the view data after image intensifier process, and carries out data output;

Described static memory 337, it is for the driving data of memory image booster, to drive the work of this image intensifier;

Described controller 338, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;

Described clock generator 3311, its for centered by process chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 339 and storage signal multiplier 3310, and by this vision signal multiplier 339, clock signal is sent to data sink, by this storage signal multiplier 3310, clock signal is sent to dynamic memory and static memory.

Please refer to Figure 48 and Figure 49, it is respectively the outside connecting circuit figure of image enhaucament chip.

Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 701, for outputting video signal video signal port 702, for receive external timing signal clock signal port 703, for exporting the row field signal port 704 of row field signal.

Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 50, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.

Refer to Figure 51-52, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.

Refer to Figure 53, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 701 comprises 20 signal pins, is connected with the data sink 331 of inside, for receiving the picture signal of input.

Refer to Figure 54, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 702 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 336.

Refer to Figure 55, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 703, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.

Refer to Figure 56, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 704 comprises a row signal pins and a field signal pin.Described row field signal port 704 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.

Refer to Figure 57, it is the internal circuit connection diagram driving display chip.

The driving display chip 34 of described main frame inside comprises: receiver of the analog signal 341, digit signal receiver 342, analog to digital converter 343, multiplexer 344, image border smoothing processor 345, Video Decoder 346, field flyback data processor 347, memory 348, output format transducer 349, data logger 3410 and controller 3411.

Described receiver of the analog signal 341, for receiving analog signal, and is sent to analog to digital converter 343;

Described data signal receiver 342, for receiving data-signal, and is sent to multiplexer 344;

Described analog to digital converter 343, for analog signal is converted to data-signal, and is sent to multiplexer 344;

Described multiplexer 344, for being integrated by two paths of signals, line output of going forward side by side is to output image edge-smoothing processor 345;

Described image border smoothing processor 345, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter 349.

Described Video Decoder 346, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor 347;

Described field flyback data processor 347, for by capable for decoded analog signal data inserting, and be sent to described memory 348 and store;

Described memory 348, for storing the data after field flyback data processor processes, and is sent to output format transducer 349.

Described output format transducer 349, for signal format being changed, and exports data logger 3410 to;

Described data logger 3410 carries out color simultaneously and exports and the output of lvds vision signal.

Described controller 3411, for the work of control simulation signal receiver 341, digit signal receiver 342, analog to digital converter 343, multiplexer 344, image border smoothing processor 345, Video Decoder 346, field flyback data processor 347, memory 348, output format transducer 349 and data logger 3410.

Please refer to Figure 58-59, it is drive the signal input of display chip and signal to export schematic diagram.

The outside of described driving display chip is provided with: power port 801, video reception port 802 and VT mouth 803; Described video reception port 802 is connected with the receiver of the analog signal 341 and data signal receiver 342 driving display chip 34 inside; Described video-out port 803 is connected with driving the data logger 3410 of display chip inside.

Refer to Figure 60, it is the partial enlarged drawing of the power port driving display chip.Described power port 801 comprises the power pins of a 1.2V and the power pins of 3.3V; Described 1.2V pin is circumscribed with two electric capacity in parallel, for filtering AC signal; Described 3.3V is circumscribed with 5 shunt capacitances, for filtering the AC signal of different frequency.

Refer to Figure 61, it is the partial enlarged drawing of the video input port driving display chip.Described video input port 802 comprises two groups of pins, and record the recording signal of circuit for receiving for one group, another group is for receiving the vision signal play in real time.Wherein, pin B5 ~ B8, A5 ~ A8 record the recording signal of circuit for receiving, and pin B1 ~ B4, A1 ~ A4 are for receiving the vision signal play in real time.

Refer to Figure 62, it is the partial enlarged drawing of the video-out port driving display chip.Described video-out port 803 comprises 12 groups of pins, is connected respectively with data logger 3410, for exporting playback video signal and real time video signals.

Refer to Figure 63, it is the internal circuit connection diagram of video record chip.

The video record chip 35 of described main frame inside comprises: data sink 351, image processor 352, video encoder 353, Video Decoder 354, data logger 355 and processor 356;

Described data sink 351, for receiving outside vision signal, and is sent to image processor 352;

Described image processor 352, the video sent for receiving data sink carries out, and processes video image, then is sent to video encoder 353; Wherein, described image processor comprises the edge intensifier circuit of the definition for strengthening image border and the interfered circuit that abates the noise for erasure signal interference.

Described video encoder 353, for recording encoding video signal;

Described Video Decoder 354, for decoding video signal playback;

Described data logger 355, for exporting vision signal;

Described processor 356, for the work of control data receiver 351, image processor 352, video encoder 353, Video Decoder 354 and data logger 355.

Refer to Figure 64-66, it is the outside port connection diagram of video record chip.

Further, described video record chip exterior is provided with: power port 901, video input port 902, video-out port 903 and PORT COM 904; Described video input port 902 is connected with the data sink 351 of this video chip inside, for receiving outside video data; Described video-out port 903, is connected with described data logger 355, for output video data; Described PORT COM 904, is connected with described processor 356, for receiving outside serial port command.

Refer to Figure 67, it is the partial enlarged drawing of power port.Described power port 901 is circumscribed with a filter circuit; Described filter circuit comprises a magnetic bead and at least one electric capacity; Described magnetic bead is connected with one end of electric capacity, and the other end ground connection of this electric capacity; Described power port is connected between magnetic bead and electric capacity.

Refer to Figure 68, it is the partial enlarged drawing of PORT COM.Described PORT COM 904 includes two pins, carries out communication as serial ports and external command.By the mode of serial communication, the data wire of use is few, can save communications cost.

Refer to Figure 69, it is the model calling schematic diagram of remote control universal turning bench control system.

The present invention also provides a kind of remote control universal turning bench control system, comprises the operating platform for transmitting control signal and the universal turning bench for Received signal strength; Described operating platform comprises command input device and instruction handling circuit;

This instruction for receiving the operational order of user, and is sent to instruction handling circuit by described command input device; Described instruction handling circuit, for receiving described operational order, after processing, occurs to universal turning bench;

Described universal turning bench, according to the operational order of operating platform, controls to be arranged on turning to, to realize the operation technique picture of multi-angled shooting doctor of sky hanging camera lens on this universal turning bench.

Below, be described in detail for operation screen and universal turning bench respectively.

Please refer to Figure 70, it is the external interface circuit figure of control chip.

Further, described instruction handling circuit comprises control chip; Described control chip 10 outside is provided with: for receive the power supply receiving port 101a of external power source, command reception port, for the signal output port 104a of output order, for receiving the clock signal port 105a of external timing signal and the configured port 106a for receiving configuration signal.There is a crystal oscillating circuit described clock signal port 105a outside; Described crystal oscillating circuit is used for providing clock signal for control chip.

Please refer to Figure 71, it is the partial enlarged drawing of the power port of control chip.

Concrete, the power port 101a of described control chip comprises VDD1, VDD2, VDD3 and VDDA tetra-power pins; Wherein VDD1, VDD2, VDD3 and VDDA access the voltage of 3.3V respectively;

Described VDDA is circumscribed with a filter circuit, and external voltage is by the power port of this filter circuit access control chip; Described filter circuit comprises inductance L 1 and the electric capacity C3 of series connection; One end of described inductance connects external voltage, and the other end is by this capacity earth, and the access of described power port is between this inductance and electric capacity.

Please refer to Figure 72, it is the circuit diagram of 3.3V voltage.Described 3.3V voltage is connected to the electric capacity of multiple parallel connection, and the capacity earth of described parallel connection.By the electric capacity of this parallel connection, the alternating current part in voltage can be drained.

Described command reception port is connected with described command input device, for receiving operational order, after control chip internal processor processes, by described signal output port by command to universal turning bench.Concrete, the command reception port of the present embodiment comprises keyboard signal receiving port 102a and rocking bar receiver port 103a.Described command input equipment comprises keyboard 11a and rocking bar 12a.

Refer to Figure 73 and Figure 74, it is respectively the partial enlarged drawing of keyboard signal receiving port and the circuits for triggering figure of keyboard.

Described keyboard signal receiving port 102a comprises 7 Signal reception pins, for receiving the output signal of keyboard.Concrete, described Signal reception pin is respectively: BD1, BD2, BD3, BD4, BD5, BD6 and BD7.

Being provided with circuits for triggering in described keyboard, for receiving the operation of user, sending the keyboard signal receiving port of triggering command to control chip; Being provided with circuits for triggering in described rocking bar, for receiving the operation of user, sending the rocking bar receiver port of triggering command to control chip.Wherein, described keyboard circuits for triggering comprise 12 trigger buttons, are respectively S1 ~ S12; Described trigger button arranges according to 4 row 3 row modes, and described line triggering signal is followed successively by: BD1, BD2, BD3 and BD4; Described row triggering signal is followed successively by: BD5, BD6 and BD7; When pressing described trigger button, trigger rows triggering signal and row triggering signal simultaneously, to distinguish different trigger buttons.Such as: as user's button click S1, triggering signal BD1 and BD2 simultaneously, these two signals are sent in the pin of BD1 and BD2 of keyboard signal receiving port by the circuits for triggering in keyboard simultaneously, thus differentiation is the triggering signal of which button.

Concrete, please refer to Figure 75 and Figure 76, it is respectively rocking bar triggering signal receiving port and rocking bar circuit diagram.

Described rocking bar receiver port 103a comprises these three pins of ADC1, ADC2 and ADC3.Accordingly, described rocking bar circuits for triggering also comprise three triggering signal output pins, are respectively used to the control command in output three directions, and are sent to respectively in three pins of rocking bar receiver port 103a.

Please refer to Figure 77, it is the circuit diagram of the AT24C02 chip of control chip.

The signal configures port of described control chip, comprises two pins, is respectively SDA and SCL pin, and a simultaneously external AT24C02 chip, serial data pin SDA and the serial clock pin SCL of this chip access in the configured port of control chip respectively; Pin A0, A1 and A2 ground connection respectively of the address date selection of this chip.

Further, described command reception circuit also comprises a signal conversion chip; Described signal conversion chip, for receiving the instruction output signal of control chip, and is converted to RS485 signal, and transfers to universal turning bench.

Refer to Figure 78, it is the circuit diagram of the signal conversion chip of signal conversion chip.

Described signal conversion chip 20 comprises power port 201a, receiver port 202a, signal output port 203a and earth terminal; Described power port is for receiving the voltage of 3.3V, and this power port is by electric capacity C4 ground connection, for alternating current part being got rid of.Described receiver port 202a comprises two signal pins, for receiving the output signal of control chip.

Refer to shown in Figure 79 to 81, described universal turning bench be used for assist physician carry out when operation operation picture live or recording, realize the 3 D auto multi-angle rotary of camera intrinsic vertical pivot, transverse axis and the longitudinal axis, facilitate doctor to carry out operation technique.The overall cylindrical cramped construction of described universal turning bench, its structure mainly comprises: install support portion 1b, vertical rotating part 2b, transverse rotation portion 3b, longitudinal rotating part 4b, camera assembly 5b and motor-drive circuit; Described vertical rotating part 2b refers to the component combination realizing camera intrinsic vertical pivot and rotate, and described transverse rotation portion 3b refers to the component combination realizing camera intrinsic transverse axis and rotate, and described longitudinal rotating part 4b refers to the component combination realizing the camera intrinsic longitudinal axis and rotate.Concrete structure is as follows:

Described installation support portion 1b is for being fixedly mounted on whole medical shooting universal turning bench device on some moveable support (the chassis support etc. as movable expanding) of operating room, to coordinate shooting operation regional display being carried out to multi-angle, described installation support portion is provided with horizontal threading spacer 11b for finishing circuit cable and longitudinal threading spacer 12b, prevents cable entanglement and knotting.The head of described installation support portion 1b is used for being connected with the end face of the vertical swing pinion of vertical rotating part 2b, and connected mode adopts screw.

The vertical swing pinion 22b that described vertical rotating part 2b inside is provided with the first stepping motor 21b and is driven by the first stepping motor 21b, described vertical rotating part 2b is connected with installation support portion 1b by vertical swing pinion 22b; Further, described vertical rotating part 2b is provided with a longitudinal direction matched with transverse circular shell 33b and rotates round base 23b, and this longitudinal direction rotation round base 23b rear portion is provided with vertical rotating avoiding hole 231b; Described installation support portion 1b is connected with the end face of vertical swing pinion 22b through after vertical rotating avoiding hole 231b.The longitudinal rotating parts mounting bracket 24b for installing the first stepping motor 21b and vertical swing pinion 22b is provided with in described longitudinally rotation round base 23b; Described first stepping motor 21b is connected with vertical swing pinion 22b by the vertical cingulum 25 that rotates.

Described transverse rotation portion 3b is fixedly mounted on vertical rotating part 2b, and described transverse rotation portion 3b has transverse circular shell 33b, the transverse rotation gear 32b being provided with the second stepping motor 31b in this transverse circular shell 33b and being driven by the second stepping motor 31b; Further, described transverse rotation portion 3b is provided with and is fixed on transverse circular enclosure, for installing the transverse rotation part mounting rack 34b of the second stepping motor 31b and transverse rotation gear 32b; Described second stepping motor 31b is connected with transverse rotation gear 33b by transverse rotation cingulum 35b.

Described longitudinal rotating part 4b is arranged on transverse rotation gear 32b by a right angle supporting bracket 44b, the longitudinal swing pinion 42b being provided with the 3rd stepping motor 41b in described longitudinal rotating part 4b and being driven by the 3rd stepping motor 41b; Described longitudinal rotating part 4b is provided with semicircular cylinder shell 43b, and this semicircular cylinder shell 43b inside is fixedly connected with right angle supporting bracket 44b.Described right angle supporting bracket 44b comprises orthogonal transverse rotation mounting edge 441b and longitudinal rotating parts mounting edge 442b; Described transverse rotation mounting edge 441b is fixedly connected with the end face of transverse rotation gear 32b; Described longitudinal rotating parts mounting edge 442b is fixed in semicircular cylinder shell 43b, and above it, installation the 3rd stepping motor 41b and longitudinal swing pinion 42b, described 3rd stepping motor 41b are connected with longitudinal swing pinion 42b by longitudinally rotating cingulum 45b.

Further, be provided with a circular dust cap 7b matched with transverse circular shell between described longitudinal rotating part 4b and transverse rotation portion 3b, this circular dust cap 7b is fixedly connected with right angle supporting bracket 44b.Be specially, the transverse rotation mounting edge 441b elder generation of described right angle supporting bracket 44b and the end face fixed-link of transverse rotation gear 32b, then circular dust cap 7b inserts and fixes with transverse rotation mounting edge 441b.That is, described transverse rotation gear 32b can drive right angle supporting bracket 44b and circular dust cap 7b to rotate around the transverse axis of transverse rotation gear simultaneously.

Described camera assembly 5b is arranged on described longitudinal swing pinion 42b, is provided with video camera 51b in described camera assembly 5b; Described camera assembly 5b has a video camera semicircular cylinder shell 52b matched with semicircular cylinder shell shape, this video camera semicircular cylinder shell 52b is fixedly connected with the end face of longitudinal swing pinion 42b, and the pallet stand 53b be provided with in described video camera semicircular cylinder shell 52b for installing video camera, this pallet stand 53b are fixed by screws in video camera semicircular cylinder shell 52b inside.Video camera 51b is fixed on pallet stand 53b by supporting plate fixed head 54b.

Present invention also offers the motor driving controling circuit of camera cradle head.Below, the circuit control part for camera cradle head is described in detail:

Further, the motor-drive circuit of described universal turning bench comprises communication chip 30, single-chip microcomputer 40, first modulus conversion chip 50, second modulus conversion chip 60, first motor drive ic 70, second motor drive ic 80 and the 3rd motor drive ic 90;

Described communication chip 30, for the operational order that Received signal strength conversion chip sends, and is sent to single-chip microcomputer after carrying out signal transacting;

Described single-chip microcomputer 40, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip and the second modulus conversion chip respectively;

The digital signal that this monolithic exports is converted to analog signal by described first modulus conversion chip 50 and the second modulus conversion chip 60, and is sent to the first motor drive ic, the second motor drive ic and the 3rd motor drive ic respectively;

After described first motor drive ic 70, second motor drive ic 80 and the 3rd motor drive ic 90 receive the control signal of the first modulus conversion chip and the second modulus conversion chip, the work of respective drive stepping motor.

Refer to Figure 82, it is the circuit diagram of communication chip.

Described communication chip 30 comprises power end 301a, signal input part 302a and signal output part 303a.Concrete, described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the output signal of Received signal strength conversion chip, and export signal to single-chip microcomputer 40 by described receiver input and receiver Enable Pin.

Refer to Figure 83, it is the circuit diagram of single-chip microcomputer.

Further, described single-chip microcomputer 40 comprises power end 401a, signal input part 402a, the first signal output part 403a, secondary signal output 404a, the 3rd signal output part 405a, the 4th signal output part 406a, reset terminal, external memory storage receiving terminal 407a and earth terminal; Described signal input part 402a is for receiving the output signal of communication chip; Described first signal output part 403a ~ the 4th signal output part 406a, for exporting point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip respectively.

Concrete, described external memory storage receiving terminal 407a is circumscribed with a storage circuit.Refer to Figure 84, it is the circuit diagram of storage circuit.

Described storage circuit comprises a storage chip, VCC and the A0 end of this storage chip accesses 5V voltage respectively; Described A1, A2, VSS, WP hold ground connection; Described SCL and SDA accesses in two pins of the external reception end 407a in shop respectively.

Refer to Figure 85, it is the circuit diagram of the first modulus conversion chip.

Described first modulus conversion chip 50 comprises power end 501a, data receiver 502a, analog signal output 503a and reference voltage incoming end 504a; Described data receiver 501a for receiving the output signal of single-chip microcomputer, and is converted to analog signal, is sent to the first motor drive ic 70 and the second motor drive ic 80 by analog signal output 503a.

Concrete, what described power end 501a accessed is 5V voltage, and this power end is by an electric capacity C21 ground connection, thus gets rid of alternating current portion voltage.

Described signal input part 502a comprises four pins, is respectively serial line interface, interface clock signal, LDAC and LOAD interface; Described LDAC interface, for loading DAC, when high level appears in pin, also can not upgrade the output of DAC even if there is digital quantity to be read into serial port.Only have when pin becomes low level from high level, DAC exports and just upgrades.Described LOAD interface is used for serial ports Loading Control.When LDAC is low level, and when trailing edge appears in LOAD pin, digital quantity is saved to latch, and output produces analog voltage subsequently.

Described signal output port 503a comprises DACA, DACB, DACC and DACD tetra-output pins.

Described reference voltage access interface 504a comprises four voltage access pins, is respectively REFA, REFB, REFC and REFD tetra-pins.And described reference voltage access interface 504a is circumscribed with a reference voltage circuit.

Refer to Figure 86, it is the circuit diagram of reference voltage.

The voltage of described reference voltage circuit is input as 5V, this voltage carries out dividing potential drop by the resistance of two series connection, export the first voltage REFA and REFB two pins to reference voltage input terminal mouth 504a, carry out dividing potential drop by two other series resistance, export the second voltage REFC and REFD two pins to reference voltage input terminal mouth 504a.

Refer to Figure 87, it is the circuit diagram of the second modulus conversion chip.

Described second modulus conversion chip 60 comprises power end 601a, data receiver 602a, analog signal output 603a and reference voltage incoming end 604a; Described data receiver 601a for receiving the output signal of single-chip microcomputer 40, and is converted to analog signal, is sent to the second motor drive ic 80 and the 3rd motor drive ic 90 by analog signal output mouth 603a.

Concrete, what described power end 601a accessed is 5V voltage, and this power end is by an electric capacity C22 ground connection, thus gets rid of alternating current portion voltage.

Described signal input part 602a comprises four pins, is respectively serial line interface, interface clock signal, LDAC and LOAD interface; Described LDAC interface, for loading DAC, when high level appears in pin, also can not upgrade the output of DAC even if there is digital quantity to be read into serial port.Only have when pin becomes low level from high level, DAC exports and just upgrades.Described LOAD interface is used for serial ports Loading Control.When LDAC is low level, and when trailing edge appears in LOAD pin, digital quantity is saved to latch, and output produces analog voltage subsequently.

Described signal output port 603a comprises DACA and DACB two output pins.

Described reference voltage access interface 604a comprises four voltage access pins, is respectively REFA, REFB, REFC and REFD tetra-pins.And described reference voltage access interface 604a is circumscribed with a reference voltage circuit.

Refer to Figure 88, it is the circuit diagram of reference voltage.

The voltage of described reference voltage circuit is input as 5V, and this voltage carries out dividing potential drop by the resistance of two series connection, and output voltage is to REFA, REFB, REFC and REFD tetra-pins of reference voltage input terminal mouth 604a.

Refer to Figure 89, it is the circuit diagram of the first motor drive ic.

Further, described first motor drive ic 70 comprises power end 701a, signal receiving end 702a, signal output part 703a, clock signal incoming end 704a and earth terminal; Described signal receiving end 702a for receiving the output signal of the first modulus conversion chip, and passes through this signal output part 703a output drive signal to the first stepping motor.

Described power end 701a comprises three pins, is respectively VCC, VMM1 and VMM2, and wherein VCC accesses 5V voltage, VMM1 and VMM2 accesses 12V voltage.In order to realize the conversion of 12V voltage and 5V voltage, the present embodiment additionally provides a voltage conversion circuit.

Refer to Figure 90, it is the circuit diagram of voltage conversion circuit.

Described voltage conversion circuit comprises voltage conversion chip, its input access 12V voltage, and output exports 5V voltage; Described input also passes through the capacity earth of two parallel connections, to be got rid of by the AC portion in input voltage; Described output also passes through a capacity earth, to be got rid of by the AC portion of output voltage.

In addition, described 12V input voltage also connects a filter circuit.Refer to Figure 91, it is the circuit diagram of filter circuit.Described filter circuit comprises inductance and four electric capacity parallel with one another; One end of described inductance is connected with the input of 12V voltage, and the other end is connected with four electric capacity in parallel, one end output voltage that described shunt capacitance is connected with inductance, other end ground connection.

Please refer to Figure 92 and Figure 93, it is respectively partial enlarged drawing and the annexation figure of the signal input port of the first motor drive ic.Described signal input port 502a comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access PE5 and PE6 respectively, CD1 and CD2 accesses PE7, and described PE5, PE6 and PE7 export from the first signal output port 403a of single-chip microcomputer.Described VR1 and VR2 accesses HDAC_VR1 and HDAC_VR2, and it exports from DACA and DACB two pins of the first modulus conversion chip signal output part 503a.

Further, in order to control the switch of motor, in the present embodiment, described first stepping motor comprises a limit switch circuit.Refer to Figure 94, it is the circuit diagram of the signal input of the first electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PD7_H signal, and this PD7_H signal exports from the PD7_H pin the 3rd signal output port 405a of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.

Refer to Figure 95, it is the circuit diagram of the second motor drive ic.

Described second motor drive ic 80 comprises power end 801a, signal receiving end 802a, signal output part 803a, clock signal incoming end 804a and earth terminal; Described signal receiving end 802a for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part 803a output drive signal to the second stepping motor.

Please refer to Figure 96 and Figure 93, it is partial enlarged drawing and the annexation figure of the signal input port of the second motor drive ic.Described signal input port 502a comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access PE3 and PE4 respectively, CD1 and CD2 accesses PE7, and described PE3, PE4 and PE7 export from the first signal output port 403 of single-chip microcomputer.Described VR1 and VR2 accesses VDAC_VR1 and VDAC_VR2, and it exports from DACC and DACD two pins of the first modulus conversion chip signal output part 503.

Further, in order to control the switch of motor, in the present embodiment, described second stepping motor comprises a limit switch circuit.Refer to Figure 97, it is the circuit diagram of the signal input of the second electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PB7_V signal, and this PB7_V signal exports from the PB7_V pin the 3rd signal output port 405a of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.

Refer to Figure 98, it is the circuit diagram of the 3rd motor drive ic.

Described 3rd motor drive ic 90 comprises power end 901a, signal receiving end 902a, signal output part 903a, clock signal incoming end 904a and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepping motor.

Please refer to Figure 99, it is the partial enlarged drawing of the signal output port of the 3rd motor drive ic.Described signal output port 903a comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access Z_Phase1 and Z_Phase1 respectively, CD1 and CD2 accesses PE7, and described PE7 exports from the first signal output port 403a of single-chip microcomputer, and described Z_Phase1 and Z_Phase2 exports from the 4th output port 407a.Described VR1 and VR2 accesses ZDAC_VR1 and ZDAC_VR2, and it exports from DACA and DACB two pins of the second modulus conversion chip signal output part 603a.

Further, in order to control the switch of motor, in the present embodiment, described second stepping motor comprises a limit switch circuit.Refer to Figure 100, it is the circuit diagram of the signal input of the second electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PB1_Z signal, and this PB1_Z signal exports from the PB1_Z pin the 3rd signal output port 405a of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.

Compared to prior art, the invention provides a kind of control system of universal turning bench, by the input of the instruction at operating platform, and transfer to universal turning bench, thus control the rotation of camera lens, the shooting angle of adjustment camera lens.

The present invention is not limited to above-mentioned execution mode, if do not depart from the spirit and scope of the present invention to various change of the present invention or distortion, if these are changed and distortion belongs within claim of the present invention and equivalent technologies scope, then the present invention is also intended to comprise these changes and distortion.

Claims (11)

1. the two camera system of medical treatment, is characterized in that: comprise medical camera system and camera cradle head control system;

Described medical camera system comprises and is arranged on sky hanging camera lens above operating table, is arranged on the submersible type camera lens implementing surgery location, and for the main frame of the vision signal that receives day hanging camera lens and submersible type camera lens;

Described camera cradle head control system comprises the operating platform for transmitting control signal and the universal turning bench for Received signal strength; Described operating platform for receiving the operational order of user, and is sent to universal turning bench;

Described control The Cloud Terrace comprises:

Support portion is installed;

Vertical rotating part, its inside is provided with the first stepping motor and by this first stepper motor driven vertical swing pinion, described vertical rotating part is connected with installation support portion by vertical swing pinion;

Transverse rotation portion, it is fixedly mounted on vertical rotating part, and described transverse rotation portion has transverse circular shell, is provided with the second stepping motor and by this second stepper motor driven transverse rotation gear in this transverse circular shell;

Longitudinal rotating part, it is arranged on transverse rotation gear by a right angle supporting bracket, is provided with the 3rd stepping motor and by the 3rd stepper motor driven longitudinal swing pinion in described longitudinal rotating part;

Camera assembly, it is arranged on described longitudinal swing pinion, and described sky hanging camera lens is arranged in described camera assembly; And,

Motor-drive circuit, for the operational order of outside, controls the work of described three stepping motors after row relax of going forward side by side, to control the rotation of described sky hanging camera lens.

2. the two camera system of medical treatment according to claim 1, is characterized in that: be provided with video capture processor and picture processing chip in described sky hanging camera lens; Described video capture processor is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Video capture processor and picture processing chip is provided with in described submersible type camera lens; Described picture processing chip is for gathering outside image information, and described picture processing chip is used for this image information to process, and is sent to main frame;

Described main frame inside is provided with and drives display chip and video record chip; Described driving display chip, carries out broadcasting display for the video information of sky hanging camera lens collection that will receive and the video information of submersible type camera lens collection; Described video record chip, preserves for the video information of sky hanging camera lens collection and the video information of submersible type camera lens collection being carried out recording.

3. the two camera system of medical treatment according to claim 2, is characterized in that: be provided with the first signal conversion chip and secondary signal conversion chip in described sky hanging camera lens; The video signal of described sky hanging camera lens collection is LVDS signal; Described first signal conversion chip, it is connected with picture processing chip, and this LVDS signal is converted to BT1120 signal, and this BT1120 signal is sent to secondary signal conversion chip; BT1120 signal is converted to sdi signal by described secondary signal conversion chip, and is sent in main frame; Described main frame inside is provided with the 3rd signal conversion chip, for sdi signal is converted to BT1120 signal;

The video signal of described submersible type camera lens collection is CVBS signal; Described main frame inside is provided with the 4th signal conversion chip, for should

CVBS signal is converted to BT656 signal.

4. the two camera system of medical treatment according to claim 3, is characterized in that: the video capture processor of described sky hanging camera lens and submersible type camera lens inside all comprises: control module, driver module, illuminant module, sampling module, output module and doubly frequency module;

Described control module, it sends triggering signal to driver module for receiving outside triggering signal;

Described driver module, it for receiving the triggering signal of control module, and drives illuminant module work;

Described illuminant module, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;

Described sampling module, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of illuminant module, and is sent to output module by it;

Described output module, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side;

Described times of frequency module, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to control module;

Described video capture processor outside is provided with: for receiving power port, the video signal port for outputting video signal, the use of supply power voltage

In the row field signal port of output row field signal, for receiving reference voltage electricity reference signal port and frequently for receiving external timing signal

Clock signal port.

5. the two camera system of medical treatment according to claim 4, is characterized in that: the picture processing chip of described sky hanging camera lens and submersible type camera lens inside all comprises: data sink, master controller, image processor, data logger and frequency multiplier;

Described data sink, it is for receiving outside view data;

Described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;

Described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it is preset for basis

Parameter, carry out the fixed adjustment of white balance; Described image processor also comprises an exposure gain circuit, for increasing exposure gain size;

Described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and will visit

Survey result and be sent to exposure gain circuit;

Described data logger, it is for exporting the view data after process;

Described frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;

Described picture processing chip outside is provided with: for receive supply power voltage power port, for receiving receiver port, the use of picture signal

In outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock of external timing signal

Signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving.

6. the two camera system of medical treatment according to claim 5, is characterized in that: the video record chip of described main frame inside comprises: data sink, video encoder, Video Decoder, data logger, processor and image processor;

Described data sink, for receiving outside vision signal, and is sent to video encoder;

Described video encoder, for recording encoding video signal;

Described Video Decoder, for decoding video signal playback;

Described data logger, for exporting vision signal;

Described processor, for the work of control data receiver, video encoder, Video Decoder and data logger;

Described image processor, processes for the video received data sink, and the image after process is sent to video encoder;

Described image processor comprises edge intensifier circuit and the interfered circuit that abates the noise;

Described video record chip exterior is provided with: power port, video input port, video-out port and PORT COM; Described video inputs

Mouth is connected with the data sink of this center processing chip internal, for receiving outside video data; Described video-out port, with described

Data logger connects, for output video data; Described PORT COM, is connected with described processor, for receiving outside serial port command.

7. the two camera system of medical treatment according to claim 6, is characterized in that: the driving display chip of described main frame inside comprises: receiver of the analog signal, digit signal receiver, analog to digital converter, multiplexer, output format transducer, data logger, controller, Video Decoder, field flyback data processor and memory;

Described receiver of the analog signal, for receiving analog signal, and is sent to analog to digital converter;

Described analog to digital converter, for analog signal is converted to data-signal, and is sent to multiplexer;

Described data signal receiver, for receiving data-signal, and is sent to multiplexer;

Described multiplexer, for being integrated by two paths of signals, line output of going forward side by side is to output format transducer;

Described output format transducer, for signal format being changed, and exports data logger to;

Described data logger, exports signal, and shows;

Described controller, for control simulation signal receiver, digit signal receiver, analog to digital converter, multiplexer, output format transducer and

The work of data logger;

Described Video Decoder, decodes for the analog signal received by receiver of the analog signal, and is sent to field flyback data processor;

Described field flyback data processor, for by capable for decoded analog signal data inserting, and be sent to described memory and store;

Described memory, for storing the data after field flyback data processor processes, and is sent to output format transducer; Described driving display chip also comprises an image border smoothing processor, for receiving the signal of restorer, and to the smoothing process in the edge of video image, then is sent to format converter;

The outside of described driving display chip is provided with: power port, video reception port and VT mouth; Receiver of the analog signal and the data signal receiver of described video reception port and center processing chip internal are connected; Described video-out port is connected with the data logger of center processing chip internal.

8. the two camera system of medical treatment according to claim 7, is characterized in that: described first signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;

Described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;

Described data reader, it for receiving LVDS video transfer signal, and is sent to signal format converter;

Described signal format converter, it for LVDS vision signal being converted to the vision signal of BT1120, and is sent to deserializer;

Described deserializer, it for serial data is converted to parallel data, and is sent to data logger;

Described data logger, for exporting BT1120 video signal data;

Described secondary signal conversion chip comprises: data buffer, low noise phase-locked loop, ASI synchronization encoders, serializer, serial image scrambler, cable driver and end noise phase-locked loop;

Described data buffer, for receiving the BT1120 signal of the first signal conversion chip, and is sent to ASI synchronization encoders;

Described low noise phase-locked loop, it is connected with data buffer, stable for holding frequency and phase place;

Described ASI synchronization encoders, for this BT1120 signal is carried out coded treatment, is converted to sdi signal, and is sent to serializer;

Described serializer, for parallel signal is converted to serial signal, and is sent to serial image scrambler;

Described serial image scrambler, for being encrypted signal data, and is sent to cable driver;

Described cable driver, for being sent to main frame by this sdi signal;

Described 3rd signal conversion chip comprises: cable equalizer, data recoverer, crystal oscillator, serial image descrambler, deserializer, ASI

Sync decoder, data extractor and data buffer;

Described cable equalizer, for receiving sdi signal and carrying out correction process, then is sent to data recoverer;

Described data recoverer, for recovering data from the distortion and noise of transmission channel, and is sent to serial image descrambler;

Described serial image descrambler, for being decrypted by signal data, and is sent to deserializer;

Described deserializer, for serial signal data are converted to parallel signal data, and is sent to ASI sync decoder;

Described ASI sync decoder, for decoding data, is converted to BT1120 signal, and is sent to data extractor;

Described data extractor, for decoded data being extracted, and is sent to data buffer;

Described data buffer, for sending the signal of reception;

Described 4th signal conversion chip comprises: analog to digital converter, analog controller, the data amplitude limiter of many standards, data bypass are adopted

The contrast saturation control circuit of sample filter, colourity and brightness, synchronous circuit, clock generator and formatted output device;

Described analog to digital converter, for receiving CVBS signal, and is converted to digital signal by this analog signal, and sends to analog controller;

Described analog controller, for receiving this BT656 digital signal, and is sent to data amplitude limiter, the data bypass sampling filter of many standards simultaneously, and the contrast saturation control circuit of colourity and brightness;

The data amplitude limiter of described many standards, for the stability of inhibit signal transmission, and is sent to formatted output device;

Described data bypass sampling filter, for filtering interference signal, and is sent to formatted output device;

The contrast saturation control circuit of described colourity and brightness, for controlling the colourity of image data, the contrast saturation of brightness, and is sent to formatted output device;

Described synchronous circuit is connected with the contrast saturation control circuit of colourity and brightness and clock generator respectively, for the contrast saturation control circuit of colourity and brightness provides pulse clock signal, makes itself and main system synchronous operation;

Described formatted output device, for being BT656 by Signal form translate, and exports this signal.

9. the two camera system of medical treatment according to claim 8, is characterized in that: described operating platform comprises command input device and instruction handling circuit;

This instruction for receiving the operational order of user, and is sent to instruction handling circuit by described command input device; Described instruction handling circuit, for receiving described operational order, after processing, occurs to universal turning bench;

Described instruction handling circuit comprises control chip; Described control chip outside is provided with: for receive external power source power supply receiving port, for receive instruction command reception port, for the signal output port of output order, for receiving the clock signal port of external timing signal and the configured port for receiving configuration signal; Described command reception port is connected with described command input device, for receiving operational order, after control chip internal processor processes, by described signal output port by command to universal turning bench;

The power port of described control chip is connected to a filter circuit, and external voltage is by the power port of this filter circuit access control chip; Described filter circuit comprises inductance and the electric capacity of series connection; One end of described inductance connects external voltage, and the other end is by this capacity earth, and the access of described power port is between this inductance and electric capacity;

There is a crystal oscillating circuit described clock signal port outside; Described crystal oscillating circuit is used for providing clock signal for control chip;

Described command input equipment comprises keyboard and rocking bar; The signal input port of described control chip comprises keyboard signal receiving port and rocking bar receiver port;

Being provided with circuits for triggering in described keyboard, for receiving the operation of user, sending the keyboard signal receiving port of triggering command to control chip; Being provided with circuits for triggering in described rocking bar, for receiving the operation of user, sending the rocking bar receiver port of triggering command to control chip.

Described keyboard circuits for triggering comprise 12 trigger buttons; Described trigger button arranges according to 4 row 3 row modes, and described line triggering signal is followed successively by: BD1, BD2, BD3 and BD4; Described row triggering signal is followed successively by: BD5, BD6 and BD7; When pressing described trigger button, trigger rows triggering signal and row triggering signal simultaneously, to distinguish different trigger buttons.

Described rocking bar circuits for triggering comprise three road output ports, are respectively used to the control command in output three directions.

10. the two camera system of medical treatment according to claim 9, it is characterized in that: the external AT24C02 chip of signal configures port of described control chip, serial data pin SDA and the serial clock pin SCL of this chip access in the configured port of control chip respectively; Pin A0, A1 and A2 ground connection respectively of the address date selection of this chip;

Described command reception circuit also comprises a signal conversion chip; Described signal conversion chip, for receiving the instruction output signal of control chip, and is converted to RS485 signal, and transfers to universal turning bench.

11. two camera systems of medical treatment according to claim 10, is characterized in that: the motor-drive circuit of described universal turning bench comprises communication chip, single-chip microcomputer, the first modulus conversion chip, the second modulus conversion chip, the first motor drive ic, the second motor drive ic and the 3rd motor drive ic;

Described communication chip, for the operational order that Received signal strength conversion chip sends, and is sent to single-chip microcomputer after carrying out signal transacting;

Described single-chip microcomputer, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip and the second modulus conversion chip respectively;

The digital signal that this monolithic exports is converted to analog signal by described first modulus conversion chip and the second modulus conversion chip, and is sent to the first motor drive ic, the second motor drive ic and the 3rd motor drive ic respectively;

After described first motor drive ic, the second motor drive ic and the 3rd motor drive ic receive the control signal of the first modulus conversion chip and the second modulus conversion chip, the work of respective drive stepping motor;

Described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the signal transmission of Received signal strength conversion chip, and are exported by described receiver input;

Described single-chip microcomputer comprises power end, signal input part, signal output part, reset terminal, external memory storage receiving terminal and earth terminal; Described signal input part is for receiving the output signal of communication chip; Described signal output part, exports point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip;

Described first modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to analog signal and is sent to the first motor drive ic and the second motor drive ic;

Described second modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to analog signal and is sent to the second motor drive ic and the 3rd motor drive ic;

Described first motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip, and passes through this signal output part output drive signal to the first stepping motor;

Described second motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part output drive signal to the second stepping motor;

Described 3rd motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepping motor.