CN204965193U - Cloud platform control circuit makes a video recording - Google Patents
Cloud platform control circuit makes a video recording Download PDFInfo
- Publication number
- CN204965193U CN204965193U CN201520726689.6U CN201520726689U CN204965193U CN 204965193 U CN204965193 U CN 204965193U CN 201520726689 U CN201520726689 U CN 201520726689U CN 204965193 U CN204965193 U CN 204965193U
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- signal
- conversion chip
- motor drive
- modulus conversion
- motor
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Abstract
The utility model relates to a cloud platform control circuit makes a video recording, the cloud platform of making a video recording includes camera lens, is used for to control a step motor, the 2nd step motor and the 3rd step motor that this camera lens is upper and lower, control and rotate to and motor -drive circuit, motor -drive circuit for outside operating instruction, and handle back control three step motor's work is with control camera lens's rotation. Compared with the prior art, the utility model provides a make a video recording control circuit of cloud platform is through receiving outside operating instruction to carry out corresponding processing, thereby pass through the rotation of motor drive chip control camera lens, adjust the shooting angle of camera lens. Consequently, can shoot the scene of making a video recording of the different angles of doctor when the operation all -roundly.
Description
Technical field
The utility model relates to a kind of control system, particularly a kind of camera cradle head control circuit.
Background technology
When clinical treatment, particularly when doctor is when performing the operation, often needing to carry out carrying out observation surgical procedure by shooting, play in real time and record, can conveniently watch in surgical procedure, also can carry out demonstration lesson by video recording simultaneously.
But existing pick-up lens is relatively fixing, the limited angle of shooting, is difficult to reduce the scene of whole operation and details.In addition when needs adjustment camera site, staff is needed to operate, so easy operation affecting doctor, and also inconvenient when adjusting.
Therefore, for existing problem, need to provide a kind of circuit that can control camera lens and carry out rotating.
Utility model content
The utility model is that the shortcoming overcoming prior art is with not enough, provides a kind of control circuit of camera cradle head.
The utility model is achieved through the following technical solutions: a kind of camera cradle head control circuit, described camera cradle head comprise pick-up lens, for control this pick-up lens up and down, the first stepper motor of left and right and rotation, the second stepper motor and the 3rd stepper motor, and motor-drive circuit; Described motor-drive circuit, for the operational order of outside, controls the work of described three stepper motors, to control the rotation of described pick-up lens after row relax of going forward side by side.
Compared to prior art, the utility model provides a kind of control circuit of camera cradle head, by receiving outside operational order, and processes accordingly, thus controls the rotation of camera lens by motor drive ic, the shooting angle of adjustment camera lens.Therefore, the shooting scene of the different angles of doctor when performing the operation can be photographed in all directions.
As further improvement of the utility model, the motor-drive circuit of described camera cradle head comprises communication chip, single-chip microcomputer, the first modulus conversion chip, the second modulus conversion chip, the first motor drive ic, the second motor drive ic and the 3rd motor drive ic;
Described communication chip, for the operational order that Received signal strength conversion chip sends, and is sent to single-chip microcomputer after carrying out signal transacting;
Described single-chip microcomputer, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip and the second modulus conversion chip respectively;
The digital signal that this monolithic exports is converted to simulating signal by described first modulus conversion chip and the second modulus conversion chip, and is sent to the first motor drive ic, the second motor drive ic and the 3rd motor drive ic respectively;
After described first motor drive ic, the second motor drive ic and the 3rd motor drive ic receive the control signal of the first modulus conversion chip and the second modulus conversion chip, the work of respective drive stepper motor.
As further improvement of the utility model, described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input end, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the signal transmission of Received signal strength conversion chip, and are exported by described receiver input end.
As further improvement of the utility model, described single-chip microcomputer comprises power end, signal input part, signal output part, reset terminal, external memory storage receiving end and earth terminal; Described signal input part is for receiving the output signal of communication chip; Described signal output part, exports point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip.
As further improvement of the utility model, described external memory storage receiving end is circumscribed with a storage circuit.
As further improvement of the utility model, described first modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to simulating signal and is sent to the first motor drive ic and the second motor drive ic;
Described second modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to simulating signal and is sent to the second motor drive ic and the 3rd motor drive ic.
As further improvement of the utility model, described first motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip, and passes through this signal output part output drive signal to the first stepper motor;
Described second motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part output drive signal to the second stepper motor;
Described 3rd motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepper motor.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is the model calling schematic diagram of camera cradle head control circuit.
Fig. 2 is the circuit diagram of communication chip.
Fig. 3 is the circuit diagram of single-chip microcomputer.
Fig. 4 is the circuit diagram of storage circuit.
Fig. 5 is the circuit diagram of the first modulus conversion chip.
Fig. 6 is the circuit diagram of reference voltage.
Fig. 7 is the circuit diagram of the second modulus conversion chip.
Fig. 8 is the circuit diagram of reference voltage.
Fig. 9 is the circuit diagram of the first motor drive ic.
Figure 10 is the circuit diagram of voltage conversion circuit.
Figure 11 is the circuit diagram of filtering circuit.
Figure 12 is the partial enlarged drawing of the signal input port of the first motor drive ic
Figure 13 is signal annexation figure.
Figure 14 is the circuit diagram of the signal input of the first electric machine spacing switch.
Figure 15 is the circuit diagram of the second motor drive ic.
Figure 16 is the partial enlarged drawing of the signal input port of the second motor drive ic.
Figure 17 is the circuit diagram of the signal input of the second electric machine spacing switch.
Figure 18 is the circuit diagram of the 3rd motor drive ic.
Figure 19 is the partial enlarged drawing of the signal output port of the 3rd motor drive ic.
Figure 20 is the circuit diagram of the signal input of the second electric machine spacing switch.
Embodiment
Refer to Fig. 1, it is the model calling schematic diagram of camera cradle head control circuit.
The utility model relates to provides a kind of camera cradle head control circuit, comprise pick-up lens, for control this pick-up lens up and down, the first stepper motor of left and right and rotation, the second stepper motor and the 3rd stepper motor, and motor-drive circuit; Described motor-drive circuit, for receiving outside operational order, controls the work of described three stepper motors, to control the rotation of described pick-up lens after row relax of going forward side by side.
Concrete, the motor-drive circuit of described camera cradle head comprises communication chip 30, single-chip microcomputer 40, first modulus conversion chip 50, second modulus conversion chip 60, first motor drive ic 70, second motor drive ic 80 and the 3rd motor drive ic 90.
Described communication chip 30, for receiving the outside operational order sent, and is sent to single-chip microcomputer after carrying out signal transacting;
Described single-chip microcomputer 40, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip 50 and the second modulus conversion chip 60 respectively;
The digital signal that this monolithic exports is converted to simulating signal by described first modulus conversion chip 50 and the second modulus conversion chip 60, and is sent to the first motor drive ic 70, second motor drive ic 80 and the 3rd motor drive ic 90 respectively.
After described first motor drive ic 70, second motor drive ic 80 and the 3rd motor drive ic 90 receive the control signal of the first modulus conversion chip 50 and the second modulus conversion chip 60, the work of respective drive stepper motor.
Refer to Fig. 2, it is the circuit diagram of communication chip.
Described communication chip 30 comprises power end 301, signal input part 302 and signal output part 303.Concrete, described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input end, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the output signal of Received signal strength conversion chip, and export signal to single-chip microcomputer 40 by described receiver input end and receiver Enable Pin.
Refer to Fig. 3, it is the circuit diagram of single-chip microcomputer.
Further, described single-chip microcomputer comprises power end 401, signal input part 402, first signal output part 403, secondary signal output terminal 404, the 3rd signal output part 404, the 4th signal output part 406, reset terminal, external memory storage receiving end 407 and earth terminal; Described signal input part 402 is for receiving the output signal of communication chip; Described first signal output part the 403 ~ four signal output part 406, for exporting point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip respectively.
Concrete, described external memory storage receiving end 407 is circumscribed with a storage circuit.Refer to Fig. 4, it is the circuit diagram of storage circuit.
Described storage circuit comprises a storage chip, VCC and the A0 end of this storage chip accesses 5V voltage respectively; Described A1, A2, VSS, WP hold ground connection; Described SCL and SDA accesses in two pins of the external reception end 407 in shop respectively.
Refer to Fig. 5, it is the circuit diagram of the first modulus conversion chip.
Described first modulus conversion chip comprises power end 501, data receiver 502, analog signal output 503 and reference voltage incoming end 504; Described data receiver 501 for receiving the output signal of single-chip microcomputer, and is converted to simulating signal, is sent to the first motor drive ic 70 and the second motor drive ic 80 by analog signal output 503.
Concrete, what described power end 501 accessed is 5V voltage, and this power end is by an electric capacity C21 ground connection, thus gets rid of alternating current portion voltage.
Described signal input part 502 comprises four pins, is respectively serial line interface, interface clock signal, LDAC and LOAD interface; Described LDAC interface, for loading DAC, when high level appears in pin, also can not upgrade the output of DAC even if there is digital quantity to be read into serial port.Only have when pin becomes low level from high level, DAC exports and just upgrades.Described LOAD interface is used for serial ports Loading Control.When LDAC is low level, and when negative edge appears in LOAD pin, digital quantity is saved to latch, and output terminal produces analog voltage subsequently.
Described signal output port 503 comprises DACA, DACB, DACC and DACD tetra-output pins.
Described reference voltage access interface 504 comprises four voltage access pins, is respectively REFA, REFB, REFC and REFD tetra-pins.And described reference voltage access interface 504 is circumscribed with a reference voltage circuit.
Refer to Fig. 6, it is the circuit diagram of reference voltage.
The voltage of described reference voltage circuit is input as 5V, this voltage carries out dividing potential drop by the resistance of two series connection, export the first voltage REFA and REFB two pins to reference voltage input terminal mouth 504, carry out dividing potential drop by two other resistance in series, export the second voltage REFC and REFD two pins to reference voltage input terminal mouth 504.
Refer to Fig. 7, it is the circuit diagram of the second modulus conversion chip.
Described second modulus conversion chip 60 comprises power end 601, data receiver 602, analog signal output 603 and reference voltage incoming end 604; Described data receiver 601 for receiving the output signal of single-chip microcomputer 40, and is converted to simulating signal, is sent to the second motor drive ic 80 and the 3rd motor drive ic 90 by analog signal output mouth 603.
Concrete, what described power end 601 accessed is 5V voltage, and this power end is by an electric capacity C22 ground connection, thus gets rid of alternating current portion voltage.
Described signal input part 602 comprises four pins, is respectively serial line interface, interface clock signal, LDAC and LOAD interface; Described LDAC interface, for loading DAC, when high level appears in pin, also can not upgrade the output of DAC even if there is digital quantity to be read into serial port.Only have when pin becomes low level from high level, DAC exports and just upgrades.Described LOAD interface is used for serial ports Loading Control.When LDAC is low level, and when negative edge appears in LOAD pin, digital quantity is saved to latch, and output terminal produces analog voltage subsequently.
Described signal output port 603 comprises DACA and DACB two output pins.
Described reference voltage access interface 604 comprises four voltage access pins, is respectively REFA, REFB, REFC and REFD tetra-pins.And described reference voltage access interface 604 is circumscribed with a reference voltage circuit.
Refer to Fig. 8, it is the circuit diagram of reference voltage.
The voltage of described reference voltage circuit is input as 5V, and this voltage carries out dividing potential drop by the resistance of two series connection, and output voltage is to REFA, REFB, REFC and REFD tetra-pins of reference voltage input terminal mouth 604.
Refer to Fig. 9, it is the circuit diagram of the first motor drive ic.
Further, described first motor drive ic comprises power end 701, signal receiving end 702, signal output part 703, clock signal incoming end 704 and earth terminal; Described signal receiving end 702 for receiving the output signal of the first modulus conversion chip, and passes through this signal output part 703 output drive signal to the first stepper motor.
Described power end 701 comprises three pins, is respectively VCC, VMM1 and VMM2, and wherein VCC accesses 5V voltage, VMM1 and VMM2 accesses 12V voltage.In order to realize the conversion of 12V voltage and 5V voltage, the present embodiment additionally provides a voltage conversion circuit.
Refer to Figure 10, it is the circuit diagram of voltage conversion circuit.
Described voltage conversion circuit comprises voltage conversion chip, its input end access 12V voltage, and output terminal exports 5V voltage; Described input end also passes through the capacity earth of two parallel connections, to be got rid of by the AC portion in input voltage; Described output terminal also passes through a capacity earth, to be got rid of by the AC portion of output voltage.
In addition, described 12V input voltage also connects a filtering circuit.Refer to Figure 11, it is the circuit diagram of filtering circuit.Described filtering circuit comprises inductance and four electric capacity parallel with one another; One end of described inductance is connected with the input end of 12V voltage, and the other end is connected with four electric capacity in parallel, one end output voltage that described shunt capacitance is connected with inductance, other end ground connection.
Please refer to Figure 12 and Figure 13, it is respectively partial enlarged drawing and the annexation figure of the signal input port of the first motor drive ic.Described signal input port 502 comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access PE5 and PE6 respectively, CD1 and CD2 accesses PE7, and described PE5, PE6 and PE7 export from the first signal output port 403 of single-chip microcomputer.Described VR1 and VR2 accesses HDAC_VR1 and HDAC_VR2, and it exports from DACA and DACB two pins of the first modulus conversion chip signal output part 503.
Further, in order to control the switch of motor, in the present embodiment, described first stepper motor comprises a limit switch circuit.Refer to Figure 14, it is the circuit diagram of the signal input of the first electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PD7_H signal, and this PD7_H signal exports from the PD7_H pin the 3rd signal output port 405 of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.
Refer to Figure 15, it is the circuit diagram of the second motor drive ic.
Described second motor drive ic comprises power end 801, signal receiving end 802, signal output part 803, clock signal incoming end 804 and earth terminal; Described signal receiving end 802 for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part 803 output drive signal to the second stepper motor.
Please refer to Figure 16 and Figure 13, it is partial enlarged drawing and the annexation figure of the signal input port of the second motor drive ic.Described signal input port 502 comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access PE3 and PE4 respectively, CD1 and CD2 accesses PE7, and described PE3, PE4 and PE7 export from the first signal output port 403 of single-chip microcomputer.Described VR1 and VR2 accesses VDAC_VR1 and VDAC_VR2, and it exports from DACC and DACD two pins of the first modulus conversion chip signal output part 503.
Further, in order to control the switch of motor, in the present embodiment, described second stepper motor comprises a limit switch circuit.Refer to Figure 17, it is the circuit diagram of the signal input of the second electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PB7_V signal, and this PB7_V signal exports from the PB7_V pin the 3rd signal output port 405 of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.
Refer to Figure 18, it is the circuit diagram of the 3rd motor drive ic.
Described 3rd motor drive ic comprises power end 901, signal receiving end 902, signal output part 903, clock signal incoming end 904 and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepper motor.
Please refer to Figure 19, it is the partial enlarged drawing of the signal output port of the 3rd motor drive ic.Described signal output port 903 comprises 6 input pins, is respectively Phase1, CD1, VR1 and Phase2, CD2, VR2.Described Phase1, Phase2 access Z_Phase1 and Z_Phase1 respectively, CD1 and CD2 accesses PE7, and described PE7 exports from the first signal output port 403 of single-chip microcomputer, and described Z_Phase1 and Z_Phase2 exports from the 4th output port 407.Described VR1 and VR2 accesses ZDAC_VR1 and ZDAC_VR2, and it exports from DACA and DACB two pins of the second modulus conversion chip signal output part 603.
Further, in order to control the switch of motor, in the present embodiment, described second stepper motor comprises a limit switch circuit.Refer to Figure 20, it is the circuit diagram of the signal input of the second electric machine spacing switch.Described limit switch signal input circuit comprises a connector; First port of described connector connects PB1_Z signal, and this PB1_Z signal exports from the PB1_Z pin the 3rd signal output port 405 of single-chip microcomputer.Second port of described connector accesses 5V voltage by an inductance, the 3rd port ground connection.
Compared to prior art, the utility model provides a kind of control system of camera cradle head, by the input of the instruction at operating platform, and transfers to camera cradle head, thus controls the rotation of camera lens, the shooting angle of adjustment camera lens.
The utility model is not limited to above-mentioned embodiment, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (7)
1. a camera cradle head control circuit, is characterized in that: described camera cradle head comprise pick-up lens, for control this pick-up lens up and down, the first stepper motor of left and right and rotation, the second stepper motor and the 3rd stepper motor, and motor-drive circuit; Described motor-drive circuit, for the operational order of outside, controls the work of described three stepper motors, to control the rotation of described pick-up lens after row relax of going forward side by side.
2. camera cradle head control circuit according to claim 1, is characterized in that: the motor-drive circuit of described camera cradle head comprises communication chip, single-chip microcomputer, the first modulus conversion chip, the second modulus conversion chip, the first motor drive ic, the second motor drive ic and the 3rd motor drive ic;
Described communication chip, for the operational order that Received signal strength conversion chip sends, and is sent to single-chip microcomputer after carrying out signal transacting;
Described single-chip microcomputer, for receiving the operational order of the forwarding of communication chip, carrying out after after process, outputing signal to the first modulus conversion chip and the second modulus conversion chip respectively;
The digital signal that this monolithic exports is converted to simulating signal by described first modulus conversion chip and the second modulus conversion chip, and is sent to the first motor drive ic, the second motor drive ic and the 3rd motor drive ic respectively;
After described first motor drive ic, the second motor drive ic and the 3rd motor drive ic receive the control signal of the first modulus conversion chip and the second modulus conversion chip, the work of respective drive stepper motor.
3. camera cradle head control circuit according to claim 2, it is characterized in that: described communication chip comprises 8 pins, is respectively: non-oppisite phase end, end of oppisite phase, receiver input end, receiver Enable Pin, driver Enable Pin, driver output end, power access end and earth terminal; Described non-oppisite phase end and end of oppisite phase are used for the signal transmission of Received signal strength conversion chip, and are exported by described receiver input end.
4. camera cradle head control circuit according to claim 3, is characterized in that: described single-chip microcomputer comprises power end, signal input part, signal output part, reset terminal, external memory storage receiving end and earth terminal; Described signal input part is for receiving the output signal of communication chip; Described signal output part, exports point level signal after single-chip microcomputer inter-process to the first modulus conversion chip and the second modulus conversion chip.
5. camera cradle head control circuit according to claim 4, is characterized in that: described external memory storage receiving end is circumscribed with a storage circuit.
6. camera cradle head control circuit according to claim 5, is characterized in that: described first modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to simulating signal and is sent to the first motor drive ic and the second motor drive ic;
Described second modulus conversion chip comprises power end, data receiver, analog signal output and reference voltage incoming end; Described data receiver for receiving the output signal of single-chip microcomputer, and is converted to simulating signal and is sent to the second motor drive ic and the 3rd motor drive ic.
7. camera cradle head control circuit according to claim 6, is characterized in that: described first motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip, and passes through this signal output part output drive signal to the first stepper motor;
Described second motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the first modulus conversion chip and the second modulus conversion chip, and passes through this signal output part output drive signal to the second stepper motor;
Described 3rd motor drive ic comprises power end, signal receiving end, signal output part, clock signal incoming end and earth terminal; Described signal receiving end for receiving the output signal of the second modulus conversion chip, and passes through this signal output part output drive signal to the 3rd stepper motor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520726689.6U CN204965193U (en) | 2015-09-18 | 2015-09-18 | Cloud platform control circuit makes a video recording |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520726689.6U CN204965193U (en) | 2015-09-18 | 2015-09-18 | Cloud platform control circuit makes a video recording |
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| Publication Number | Publication Date |
|---|---|
| CN204965193U true CN204965193U (en) | 2016-01-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520726689.6U Expired - Fee Related CN204965193U (en) | 2015-09-18 | 2015-09-18 | Cloud platform control circuit makes a video recording |
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| CN (1) | CN204965193U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886183A (en) * | 2017-04-10 | 2017-06-23 | 天津市联大通讯发展有限公司 | Industrial heavy-load camera system control panel |
-
2015
- 2015-09-18 CN CN201520726689.6U patent/CN204965193U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886183A (en) * | 2017-04-10 | 2017-06-23 | 天津市联大通讯发展有限公司 | Industrial heavy-load camera system control panel |
| CN106886183B (en) * | 2017-04-10 | 2023-05-16 | 天津市联大通讯发展有限公司 | Industrial heavy-duty camera system control board |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160113 Termination date: 20190918 |