CN203351179U - Ultra-high-definition display frequency multiplication and amplification driving device - Google Patents
Ultra-high-definition display frequency multiplication and amplification driving device Download PDFInfo
- Publication number
- CN203351179U CN203351179U CN 201320370943 CN201320370943U CN203351179U CN 203351179 U CN203351179 U CN 203351179U CN 201320370943 CN201320370943 CN 201320370943 CN 201320370943 U CN201320370943 U CN 201320370943U CN 203351179 U CN203351179 U CN 203351179U
- Authority
- CN
- China
- Prior art keywords
- frequency multiplication
- ddr
- gate array
- connects
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model provides an ultra-high-definition display frequency multiplication and amplification driving device, and aims to solve the problem that no professional chip, at present, can drive the ultra-high-definition panel. The ultra-high-definition display frequency multiplication and amplification driving device includes an HDMI receiver connected with an HDMI connector; the HDMI receiver is respectively connected with a single-chip microcomputer and a programmable logic gate array; the programmable logic gate array is connected to a T control board; the programmable logic gate array includes an image processor connected with the HDMI receiver; the image processor is connected with a DDR controller; the DDR controller is connected with a V-BY-ONE core; the V-BY-ONE core is connected to the T control board; and the DDR controller is connected with a DDR. The Ultra-high-definition display frequency multiplication and amplification driving device performs the amplification and the frequency multiplication of the normal signal which does not reach the 3840 * 2160 resolution, and at the same time can carry out the segmentation display and frequency multiplication of the signal source with the 3840 * 2160 resolution; and the application range is wide.
Description
technical field:
The utility model relates to a kind of ultra high-definition and shows frequency multiplication amplification drive unit, belongs to technical field of liquid crystal display.
background technology:
Ultra high-definition (Ultra High-Definition is called for short UD) shows that from the most newly approved information of International Telecommunications Union (ITU) the formal title of 4K resolution (3840x2160 pixel) is decided to be " ultra high-definition ".And at present HDTV resolution on the market is mostly the physical resolution of 1920x1080.What the high resolution of UD was brought is incredible fine and smooth display effect, and in play pieces, superior camera lens almost can mirror the overall picture in a city, and each details in camera lens a---automobile, a pedestrian, that can see is absolutely clear.
At present, the large LG of panel vendor, three magnitudes are released the UD panel successively in this year, due to the primacy of this technology, do not have temporarily at present and can drive the professional chip of these UD panels to release.Drive scheme becomes the matter of utmost importance of television manufacturer research and development.
the utility model content:
The purpose of this utility model is that the problem for above-mentioned existence provides a kind of ultra high-definition to show that frequency multiplication amplifies drive unit, can realize the driving that ultra high-definition shows, makes it directly to drive the UD Display panel to go out the UD content.
Above-mentioned purpose realizes by following technical scheme:
Ultra high-definition shows frequency multiplication amplification drive unit, comprise with the HDMI joint and be connected the HDMI receiver, described HDMI receiver connects respectively single-chip microcomputer and programmable gate array, described programmable gate array connects T control plate, described programmable gate array comprises the image processor be connected with described HDMI receiver, described image processor connects the DDR controller, described DDR controller connects the V-BY-ONE kernel, described V-BY-ONE kernel connects described T control plate, and described DDR controller connects DDR.
Described ultra high-definition shows frequency multiplication amplification drive unit, and described programmable gate array adopts two, and every programmable gate array connects two described DDR controllers, and each described DDR controller connects two DDR.
Described ultra high-definition shows frequency multiplication amplification drive unit, and it is the SI9135 chip that described HDMI receiver adopts model.
Described ultra high-definition shows frequency multiplication amplification drive unit, and described single-chip microcomputer adopts the single-chip microcomputer that model is STC11L60EX.
Beneficial effect:
1. the utility model has been realized the driving that ultra high-definition shows, can directly drive the UD Display panel to go out the UD content.
2. the utility model amplifies for the signal source (VGA that comprises various resolution, AV, SDI, HDMI signal source) that does not normally reach 3840x2160 resolution and frequency multiplication (to the 120HZ refresh rate); Can be cut apart and be shown and frequency multiplication the signal source of 3840x2160 resolution simultaneously, applied widely.
3. the utility model is used single-chip microcomputer STC11L60EX to pass through I
2c configure SI9135, complete HDMI and turn TTL and output to programmable gate array (FPGA); Adopt fpga chip to be processed, complete color space conversion, model selection, be cached to after DDR amplified, no matter what refresh rate is unified frequency multiplication to 120HZ to the rear class chip.
4. the bandwidth in order to guarantee that DDR is enough, adopted two FPGA, totally 8 DDR.Every FPGA is responsible for processing the displaying contents of half, and every FPGA meets 4 DDR.Every FPGA connects two DDR controllers, is equivalent to two DDR and forms a controller.Each controller is processed the content of screen 1/4th.
the accompanying drawing explanation:
Fig. 1 is structural representation of the present utility model.
embodiment:
Embodiment 1:
Ultra high-definition shows frequency multiplication amplification drive unit, comprise with the HDMI joint and be connected the HDMI receiver, described HDMI receiver connects respectively single-chip microcomputer and programmable gate array, described programmable gate array connects T control plate, described programmable gate array comprises the image processor be connected with described HDMI receiver, described image processor connects the DDR controller, described DDR controller connects the V-BY-ONE kernel, described V-BY-ONE kernel connects described T control plate, and described DDR controller connects DDR.
Embodiment 2:
The described ultra high-definition of embodiment 1 shows frequency multiplication amplification drive unit, and described programmable gate array adopts two, and every programmable gate array connects two described DDR controllers, and each described DDR controller connects two DDR.
Embodiment 3:
The described ultra high-definition of embodiment 1 or embodiment 2 shows frequency multiplication amplification drive unit, and it is the SI9135 chip that described HDMI receiver adopts model.
Embodiment 4:
The described ultra high-definition of embodiment 1 or embodiment 2 shows frequency multiplication amplification drive unit, and described single-chip microcomputer adopts the single-chip microcomputer that model is STC11L60EX.
The disclosed technological means of the utility model scheme is not limited only to the disclosed technological means of above-mentioned technological means, also comprises the technical scheme be comprised of above technical characterictic combination in any.Unaccomplished matter of the present utility model, belong to those skilled in the art's common practise.
Claims (4)
1. a ultra high-definition shows frequency multiplication amplification drive unit, it is characterized in that: comprise with the HDMI joint and be connected the HDMI receiver, described HDMI receiver connects respectively single-chip microcomputer and programmable gate array, described programmable gate array connects T control plate, described programmable gate array comprises the image processor be connected with described HDMI receiver, described image processor connects the DDR controller, described DDR controller connects the V-BY-ONE kernel, described V-BY-ONE kernel connects described T control plate, and described DDR controller connects DDR.
2. ultra high-definition according to claim 1 shows frequency multiplication amplification drive unit, it is characterized in that: described programmable gate array adopts two, every programmable gate array connects two described DDR controllers, and each described DDR controller connects two DDR.
3. ultra high-definition according to claim 1 and 2 shows frequency multiplication amplification drive unit, and it is characterized in that: it is the SI9135 chip that described HDMI receiver adopts model.
4. ultra high-definition according to claim 1 and 2 shows frequency multiplication amplification drive unit, and it is characterized in that: described single-chip microcomputer adopts the single-chip microcomputer that model is STC11L60EX.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320370943 CN203351179U (en) | 2013-06-26 | 2013-06-26 | Ultra-high-definition display frequency multiplication and amplification driving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320370943 CN203351179U (en) | 2013-06-26 | 2013-06-26 | Ultra-high-definition display frequency multiplication and amplification driving device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203351179U true CN203351179U (en) | 2013-12-18 |
Family
ID=49751047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320370943 Expired - Fee Related CN203351179U (en) | 2013-06-26 | 2013-06-26 | Ultra-high-definition display frequency multiplication and amplification driving device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203351179U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104683713A (en) * | 2015-03-20 | 2015-06-03 | 北京京东方多媒体科技有限公司 | Video signal wireless transmitter, receiver, transmission system and display system |
| CN104917988A (en) * | 2014-03-10 | 2015-09-16 | 北京阿格思科技有限公司 | V-BY-ONE interface high-speed image acquisition card |
| CN105118409A (en) * | 2015-08-19 | 2015-12-02 | 武汉精测电子技术股份有限公司 | FPGA-Based V-BY-ONE codec system and method |
| CN105791731A (en) * | 2014-12-15 | 2016-07-20 | 北京阿格思科技有限公司 | V-by-One interface ultrahigh-definition image signal source |
| CN108320694A (en) * | 2018-03-28 | 2018-07-24 | 惠科股份有限公司 | Display device and driving method |
-
2013
- 2013-06-26 CN CN 201320370943 patent/CN203351179U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104917988A (en) * | 2014-03-10 | 2015-09-16 | 北京阿格思科技有限公司 | V-BY-ONE interface high-speed image acquisition card |
| CN105791731A (en) * | 2014-12-15 | 2016-07-20 | 北京阿格思科技有限公司 | V-by-One interface ultrahigh-definition image signal source |
| CN105791731B (en) * | 2014-12-15 | 2018-04-20 | 北京阿格思科技有限公司 | V by One interface ultra high-definition image signal sources |
| CN104683713A (en) * | 2015-03-20 | 2015-06-03 | 北京京东方多媒体科技有限公司 | Video signal wireless transmitter, receiver, transmission system and display system |
| US10230926B2 (en) | 2015-03-20 | 2019-03-12 | Boe Technology Group Co., Ltd. | Wireless video signal transmitter, receiver, transmission system and display system |
| CN105118409A (en) * | 2015-08-19 | 2015-12-02 | 武汉精测电子技术股份有限公司 | FPGA-Based V-BY-ONE codec system and method |
| CN105118409B (en) * | 2015-08-19 | 2017-12-26 | 武汉精测电子技术股份有限公司 | V BY ONE coding/decoding systems and method based on FPGA |
| CN108320694A (en) * | 2018-03-28 | 2018-07-24 | 惠科股份有限公司 | Display device and driving method |
| WO2019184453A1 (en) * | 2018-03-28 | 2019-10-03 | 惠科股份有限公司 | Display device and driving method therefor |
| CN108320694B (en) * | 2018-03-28 | 2021-03-30 | 惠科股份有限公司 | Display device and driving method |
| US11024244B2 (en) | 2018-03-28 | 2021-06-01 | HKC Corporation Limited | Display device and driving method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203351179U (en) | Ultra-high-definition display frequency multiplication and amplification driving device | |
| CN201577135U (en) | Matrix with multiple input formats and high rate | |
| CN103957374A (en) | 8K ultrahigh-definition display system based on DP interface | |
| CN103248797A (en) | Video resolution enhancing method and module based on FPGA (field programmable gate array) | |
| CN207752739U (en) | display device with splicing function | |
| CN203691512U (en) | Splicer having video storage function | |
| KR20160146645A (en) | Data processing method and device for led television, and led television | |
| CN204681493U (en) | A kind of 4K multi-screen splicing processor | |
| CN103778893A (en) | Backlight control method, backlight control device and display device | |
| CN201655249U (en) | Integrated audio/video controller for LED display | |
| CN203787060U (en) | Display screen test device provided with plurality of VGA output interfaces | |
| CN212413298U (en) | Image processing device based on 4K signal | |
| CN204206361U (en) | A kind of chip with 3D Projection Display | |
| CN203012698U (en) | Split joint screen synchronous playing device | |
| CN204031327U (en) | Based on DisplayPort, realize the control device of video wall splicing | |
| CN101552897B (en) | Method and apparatus for achieving the display of mosaicing high definition base image by using a U disk or/and a flash memory | |
| CN204143840U (en) | A kind of LED display control system | |
| CN203136042U (en) | Device for expanding camera output interface | |
| CN107707829A (en) | A kind of method that multiplex roles intelligence SDI video switching boxs are realized based on FPGA | |
| CN101227598B (en) | High-resolution video monitoring system | |
| CN203387601U (en) | Plug-in type high definition hybrid matrix device with central control function | |
| CN202205442U (en) | Multi-picture LCD control circuit | |
| CN105744364A (en) | Improving method for image definition and contrast of 4K ultra high definition liquid crystal display television | |
| CN202721742U (en) | High definition hybrid matrix seamless switching DVI digital interface system | |
| CN202362766U (en) | Liquid crystal splicing wall applicable to synchronously displaying multipath image data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: No. 3 Gu Tan Road in Gaochun Economic Development Zone of Nanjing city in Jiangsu province 211300 Patentee after: NANJING ODIN TECHNOLOGY Co.,Ltd. Address before: 211300, No. 3 Tan Avenue, Gaochun economic and Technological Development Zone, Nanjing, Jiangsu Patentee before: NANJING ODIN TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170728 Address after: 210000 Jiangsu Province, Nanjing city Yuhuatai district road 18, building 3, Phoenix Patentee after: JIANGSU OUDI ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: No. 3 Gu Tan Road in Gaochun Economic Development Zone of Nanjing city in Jiangsu province 211300 Patentee before: NANJING ODIN TECHNOLOGY Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: No. 12-9 Fengji road in Yuhuatai District of Nanjing City, Jiangsu province 210039 Patentee after: JIANGSU OUDI ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 210000 Jiangsu Province, Nanjing city Yuhuatai district road 18, building 3, Phoenix Patentee before: JIANGSU OUDI ELECTRONIC TECHNOLOGY Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131218 |